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68 Updated specification, includes well illustrated pipeline discussion. dgisselq 2503d 19h /
67 Includes timing diagrams in support of a very descriptive specification section. dgisselq 2503d 19h /
66 Adjusted the support for the DEBUG_SCOPE within these so that it can be
compiled in, or not, based upon an external build configuration file: cpudefs.v.
That allows me to make that file project specific, while the rest of the CPU
is shared among all projects.
dgisselq 2529d 18h /
65 Lots of logic simplifications to the core, in addition to better support for
illegal instruction detection and bus error detection. The biggest change
had to deal with pushing the debug write interface into the ALU write
processing path. This simplifies the logic of adjusting the PC and CC
registers primarily, but also any writes to other registers. It also delays
these register writes by a clock, but since the debug interface is already
ridiculously slow I doubt that matters any.
dgisselq 2529d 18h /
64 Shuffled some comments into here from elsewhere. dgisselq 2529d 18h /
63 Simplified bus interactions, and added support for detecting illegal
instructions (i.e. bus errors) in the pipefetch routine.
dgisselq 2529d 18h /
62 Simplified the subtraction logic, so the carry bit no longer depends on
a separate 32-bit operation but becomes part of the subtract operation.
dgisselq 2529d 19h /
61 Simplified the bus delay logic. Depends upon the stall line being irrelevant
outside of a bus cycle.
dgisselq 2529d 19h /
60 Fixed assembler processing of jump instructions, so that the new fast
return instruction can be used. The test file was modified to test
pipelined value passing within the CPU. That's where the value gets
(re)used before being stored back in the register file. As of this release,
all tests work.
dgisselq 2529d 19h /
59 Adjusted these library routines to use the new stack frame and calling
conventions.
dgisselq 2529d 19h /

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