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https://opencores.org/ocsvn/ethmac/ethmac/trunk
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[/] [ethmac/] [trunk/] [rtl/] [verilog/] - Rev 244
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Last modification
- Rev 244, 2002-11-14 18:37:20 GMT
- Author: mohor
- Log message:
- r_Rst signal does not reset any module any more and is removed from the design.