Subversion Repositories minsoc

[/] [minsoc/] [trunk/] [bench/] [verilog/] - Rev 71


Directory listing | View Log | Compare with Previous | RSS feed

Last modification

  • Rev 71, 2011-05-10 10:34:10 GMT
  • Author: rfajardo
  • Log message:
    Modelsim whines about missing timescales:
    -minsoc_bench.v, minsoc_memory_model.v and dbg_comm_vpi.v updated to include timescale.v

    modelsim simulation working under Windows. Modelsim PE Student Edition 10.0a

    Simulation<->adv_jtag_bridge<->gdb communication not working perfectly. I believe VPI module has to be recompiled, used pre-compiled one for now.

powered by: WebSVN 2.1.0

© copyright 1999-2024, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.