URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] - Rev 30

Rev 30, 2012-11-07 09:37:37 GMT
Author: JonasDC
Log message:
put last cell logic of the pipeline in a separate design unit, tested and working

Path
/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
/mod_sim_exp/trunk/rtl/vhdl/core/sys_last_cell_logic.vhd
/mod_sim_exp/trunk/rtl/vhdl/core/sys_pipeline.vhd
/mod_sim_exp/trunk/sim/Makefile