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https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk
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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] - Rev 31
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Last modification
- Rev 31, 2012-11-07 10:01:55 GMT
- Author: JonasDC
- Log message:
- put first cell logic of the pipeline in a separate design unit, tested and working