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https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk
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[/] [open8_urisc/] [trunk/] [VHDL/] - Rev 254
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Last modification
- Rev 254, 2020-06-10 00:21:03 GMT
- Author: jshamlet
- Log message:
- Simplified the ISR address logic so that the upper 12 bits are constant (set by generic) and only the lower 4 bits are registered/computed.