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[/] - Rev 205

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Last modification

  • Rev 205, 2015-07-15 20:59:52 GMT
  • Author: olivier.girard
  • Log message:
    Thanks again to Johan W. good feedback, the following updates are implemented:
    - Change code to fix delta cycle issues on some simulators in mixed VHDL/Verilog environment.
    - Update oscillators enable generation to relax a critical timing paths in the ASIC version.
    - Add option to scan fix inverted clocks in the ASIC version (disabled by default as this is supported by most tools).
Path
/openmsp430/trunk/core/bench/verilog/tb_openMSP430.v
/openmsp430/trunk/core/rtl/verilog/omsp_clock_module.v
/openmsp430/trunk/core/rtl/verilog/omsp_clock_mux.v
/openmsp430/trunk/core/rtl/verilog/omsp_mem_backbone.v
/openmsp430/trunk/core/rtl/verilog/openMSP430_defines.v
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_clock_module.v
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_clock_mux.v
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_mem_backbone.v
/openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430_defines.v
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_clock_module.v
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_clock_mux.v
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_mem_backbone.v
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/openMSP430_defines.v
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/omsp_clock_module.v
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/omsp_clock_mux.v
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/omsp_mem_backbone.v
/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/openMSP430_defines.v
/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_clock_module.v
/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_clock_mux.v
/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_mem_backbone.v
/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430_defines.v

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