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[/] [openrisc/] [trunk/] [orpsocv2/] [bench/] [sysc/] [src/] - Rev 6

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Last modification

  • Rev 6, 2009-05-21 21:32:57 GMT
  • Author: julius
  • Log message:
    Checking in ORPSoCv2
Path
/openrisc/trunk/orpsocv2
/openrisc/trunk/orpsocv2/backend
/openrisc/trunk/orpsocv2/backend/gbuf.v
/openrisc/trunk/orpsocv2/backend/sim_lib.v
/openrisc/trunk/orpsocv2/bench
/openrisc/trunk/orpsocv2/bench/sysc
/openrisc/trunk/orpsocv2/bench/sysc/include
/openrisc/trunk/orpsocv2/bench/sysc/include/Or1200MonitorSC.h
/openrisc/trunk/orpsocv2/bench/sysc/include/OrpsocAccess.h
/openrisc/trunk/orpsocv2/bench/sysc/include/OrpsocMain.h
/openrisc/trunk/orpsocv2/bench/sysc/include/ResetSC.h
/openrisc/trunk/orpsocv2/bench/sysc/include/TraceSC.h
/openrisc/trunk/orpsocv2/bench/sysc/include/UartSC.h
/openrisc/trunk/orpsocv2/bench/sysc/src
/openrisc/trunk/orpsocv2/bench/sysc/src/Modules.make
/openrisc/trunk/orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp
/openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocAccess.cpp
/openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocMain.cpp
/openrisc/trunk/orpsocv2/bench/sysc/src/ResetSC.cpp
/openrisc/trunk/orpsocv2/bench/sysc/src/TraceSC.cpp
/openrisc/trunk/orpsocv2/bench/sysc/src/UartSC.cpp
/openrisc/trunk/orpsocv2/bench/verilog
/openrisc/trunk/orpsocv2/bench/verilog/AT26DFxxx.v
/openrisc/trunk/orpsocv2/bench/verilog/clk_gen.v
/openrisc/trunk/orpsocv2/bench/verilog/mt48lc16m16a2.v
/openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v
/openrisc/trunk/orpsocv2/bench/verilog/orpsoc_testbench.v
/openrisc/trunk/orpsocv2/bench/verilog/orpsoc_testbench_defines.v
/openrisc/trunk/orpsocv2/bench/verilog/timescale.v
/openrisc/trunk/orpsocv2/bench/verilog/uart_decoder.v
/openrisc/trunk/orpsocv2/rtl
/openrisc/trunk/orpsocv2/rtl/verilog
/openrisc/trunk/orpsocv2/rtl/verilog/components
/openrisc/trunk/orpsocv2/rtl/verilog/components/debug_if
/openrisc/trunk/orpsocv2/rtl/verilog/components/debug_if/dbg_cpu.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/debug_if/dbg_cpu_defines.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/debug_if/dbg_cpu_registers.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/debug_if/dbg_crc32_d1.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/debug_if/dbg_defines.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/debug_if/dbg_defines_old.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/debug_if/dbg_register.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/debug_if/dbg_top.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/debug_if/dbg_top_ip.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/debug_if/dbg_wb.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/debug_if/dbg_wb_defines.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/debug_if/debug_if_ip.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/debug_if/Makefile
/openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet
/openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/BUGS
/openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/eth_clockgen.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/eth_cop.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/eth_crc.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/eth_defines.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/eth_fifo.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/eth_maccontrol.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/eth_macstatus.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/eth_miim.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/eth_outputcontrol.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/eth_random.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/eth_receivecontrol.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/eth_register.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/eth_registers.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/eth_rxaddrcheck.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/eth_rxcounters.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/eth_rxethmac.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/eth_rxstatem.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/eth_shiftreg.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/eth_spram_256x32.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/eth_top.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/eth_top_ip.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/eth_transmitcontrol.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/eth_txcounters.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/eth_txethmac.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/eth_txstatem.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/eth_wishbone.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/filer
/openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/Makefile
/openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/TODO
/openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/xilinx_dist_ram_16x32.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/or1k_startup
/openrisc/trunk/orpsocv2/rtl/verilog/components/or1k_startup/copyright_OR1K_startup.v
/openrisc/trunk/orpsocv2/rtl/verilog/components/or1k_startup/copyright_spi.v