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[/] [spi_master_slave/] - Rev 4


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Last modification

  • Rev 4, 2011-06-16 05:37:23 GMT
  • Author: jdoin
  • Log message:
    v0.97.0068 - streamlined resets and clock enables to reduce area
    v0.97.0075 - redesigned parallel interfaces, with pipelined data transport for async clock domains
    v0.97.0083 - fixed bug "CPHA effect": redesigned SCK output circuit
    v0.97.0086 - removed master MISO input register: got 33MHz.

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