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[/] [yifive/] [trunk/] - Rev 21

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Last modification

  • Rev 21, 2021-06-13 06:33:52 GMT
  • Author: dinesha
  • Log message:
    Simulation clean up and wishbone interconnect added
Path
/yifive/trunk/caravel_yifive/verilog/rtl/digital_core/filelist_rtl.f
/yifive/trunk/caravel_yifive/verilog/rtl/digital_core/src/digital_core.sv
/yifive/trunk/caravel_yifive/verilog/rtl/lib/wb_crossbar.v
/yifive/trunk/caravel_yifive/verilog/rtl/sdram_ctrl/src/core/sdrc_core.v
/yifive/trunk/caravel_yifive/verilog/rtl/sdram_ctrl/src/core/sdrc_req_gen.v
/yifive/trunk/caravel_yifive/verilog/rtl/sdram_ctrl/src/core/sdrc_xfr_ctl.v
/yifive/trunk/caravel_yifive/verilog/rtl/spi_master/src/spim_clkgen.sv
/yifive/trunk/caravel_yifive/verilog/rtl/spi_master/src/spim_ctrl.sv
/yifive/trunk/caravel_yifive/verilog/rtl/spi_master/src/spim_regs.sv
/yifive/trunk/caravel_yifive/verilog/rtl/spi_master/src/spim_rx.sv
/yifive/trunk/caravel_yifive/verilog/rtl/spi_master/src/spim_top.sv
/yifive/trunk/caravel_yifive/verilog/rtl/spi_master/src/spim_tx.sv
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_exu.sv
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_ialu.sv
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_idu.sv
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_ifu.sv
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_lsu.sv
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_mprf.sv
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_top.sv
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_tracelog.sv
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/core/scr1_core_top.sv
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/core/scr1_dm.sv
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/includes/scr1_arch_types.svh
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/includes/scr1_memif.svh
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/includes/scr1_riscv_isa_decoding.svh
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/includes/scr1_scu.svh
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/top/scr1_dmem_ahb.sv
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/top/scr1_dmem_router.sv
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/top/scr1_dmem_wb.sv
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/top/scr1_imem_ahb.sv
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/top/scr1_imem_router.sv
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/top/scr1_imem_wb.sv
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/top/scr1_mem_axi.sv
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/top/scr1_tcm.sv
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/top/scr1_timer.sv
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/top/scr1_top_ahb.sv
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/top/scr1_top_axi.sv
/yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/top/scr1_top_wb.sv
/yifive/trunk/caravel_yifive/verilog/rtl/uprj_netlists.v
/yifive/trunk/caravel_yifive/verilog/rtl/user_project_wrapper.v
/yifive/trunk/caravel_yifive/verilog/rtl/wb_interconnect
/yifive/trunk/caravel_yifive/verilog/rtl/wb_interconnect/src
/yifive/trunk/caravel_yifive/verilog/rtl/wb_interconnect/src/wb_arb.sv
/yifive/trunk/caravel_yifive/verilog/rtl/wb_interconnect/src/wb_interconnect.sv

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