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https://opencores.org/websvn//websvn/listing?repname=ata&path=%2F&
Sun, 23 Aug 2026 21:14:27 +0100
FeedCreator 1.7.2
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Added old uploaded documents to new repository.
https://opencores.org/websvn//websvn/revision?repname=ata&path=%2F&rev=35
<div><strong>Rev 35 - root</strong> (7 file(s) modified)</div><div>Added old uploaded documents to new repository.</div>+ /ata/web_uploads/index.shtml<br />- /ata/web_uploads/oc_checkin.sh<br />- /ata/web_uploads/oc_cvs_checkin.sh<br />+ /ata/web_uploads/preliminary_ata_core.pdf<br />- /ata/web_uploads/svn_checkin.log<br />- /ata/web_uploads/svn_checkin.sh<br />- /ata/web_uploads/temp.sh<br />
root
Tue, 10 Mar 2009 12:27:19 +0100
https://opencores.org/websvn//websvn/revision?repname=ata&path=%2F&rev=35
-
Added old uploaded documents to new repository.
https://opencores.org/websvn//websvn/revision?repname=ata&path=%2F&rev=34
<div><strong>Rev 34 - root</strong> (5 file(s) modified)</div><div>Added old uploaded documents to new repository.</div>+ /ata/web_uploads/oc_checkin.sh<br />+ /ata/web_uploads/oc_cvs_checkin.sh<br />+ /ata/web_uploads/svn_checkin.log<br />+ /ata/web_uploads/svn_checkin.sh<br />+ /ata/web_uploads/temp.sh<br />
root
Mon, 09 Mar 2009 19:03:08 +0100
https://opencores.org/websvn//websvn/revision?repname=ata&path=%2F&rev=34
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New directory structure.
https://opencores.org/websvn//websvn/revision?repname=ata&path=%2F&rev=33
<div><strong>Rev 33 - root</strong> (8 file(s) modified)</div><div>New directory structure.</div>+ /ata<br />+ /ata/branches<br />+ /ata/tags<br />+ /ata/trunk<br />+ /ata/web_uploads<br />- /branches<br />- /tags<br />- /trunk<br />
root
Mon, 09 Mar 2009 19:02:09 +0100
https://opencores.org/websvn//websvn/revision?repname=ata&path=%2F&rev=33
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Fixed a potential bug where the core was forced into ...
https://opencores.org/websvn//websvn/revision?repname=ata&path=%2F&rev=32
<div><strong>Rev 32 - rherveille</strong> (9 file(s) modified)</div><div>Fixed a potential bug where the core was forced into ...</div>~ /trunk/rtl/verilog/ocidec-1/atahost_controller.v<br />~ /trunk/rtl/verilog/ocidec-1/revision_history.txt<br />~ /trunk/rtl/verilog/ocidec-2/atahost_controller.v<br />~ /trunk/rtl/verilog/ocidec-2/revision_history.txt<br />~ /trunk/rtl/vhdl/ocidec1/atahost_controller.vhd<br />~ /trunk/rtl/vhdl/ocidec1/revision_history.txt<br />~ /trunk/rtl/vhdl/ocidec2/atahost_controller.vhd<br />~ /trunk/rtl/vhdl/ocidec2/atahost_pio_actrl.vhd<br />~ /trunk/rtl/vhdl/ocidec2/revision_history.txt<br />
rherveille
Sun, 19 May 2002 06:07:09 +0100
https://opencores.org/websvn//websvn/revision?repname=ata&path=%2F&rev=32
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Changed internal counter libraries.
Split counter.vhd into separate files.
Core is in ...
https://opencores.org/websvn//websvn/revision?repname=ata&path=%2F&rev=31
<div><strong>Rev 31 - rherveille</strong> (6 file(s) modified)</div><div>Changed internal counter libraries.<br />
Split counter.vhd into separate files.<br />
Core is in ...</div>+ /trunk/rtl/vhdl/ocidec1/ro_cnt.vhd<br />+ /trunk/rtl/vhdl/ocidec1/ud_cnt.vhd<br />+ /trunk/rtl/vhdl/ocidec2/ro_cnt.vhd<br />+ /trunk/rtl/vhdl/ocidec2/ud_cnt.vhd<br />+ /trunk/rtl/vhdl/ocidec3/ro_cnt.vhd<br />+ /trunk/rtl/vhdl/ocidec3/ud_cnt.vhd<br />
rherveille
Fri, 01 Mar 2002 03:49:25 +0100
https://opencores.org/websvn//websvn/revision?repname=ata&path=%2F&rev=31
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Fixed data-latch bug (posedge ata_diow instead of negedge ata_diow).
https://opencores.org/websvn//websvn/revision?repname=ata&path=%2F&rev=30
<div><strong>Rev 30 - rherveille</strong> (1 file(s) modified)</div><div>Fixed data-latch bug (posedge ata_diow instead of negedge ata_diow).</div>~ /trunk/bench/verilog/ata_device.v<br />
rherveille
Mon, 25 Feb 2002 06:07:21 +0100
https://opencores.org/websvn//websvn/revision?repname=ata&path=%2F&rev=30
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no message
https://opencores.org/websvn//websvn/revision?repname=ata&path=%2F&rev=29
<div><strong>Rev 29 - rherveille</strong> (1 file(s) modified)</div><div>no message</div>~ /trunk/doc/preliminary_ata_core.pdf<br />
rherveille
Mon, 18 Feb 2002 14:35:01 +0100
https://opencores.org/websvn//websvn/revision?repname=ata&path=%2F&rev=29
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renamed IO names
revised document
https://opencores.org/websvn//websvn/revision?repname=ata&path=%2F&rev=28
<div><strong>Rev 28 - rherveille</strong> (1 file(s) modified)</div><div>renamed IO names<br />
revised document</div>~ /trunk/doc/src/ata_core.doc<br />
rherveille
Mon, 18 Feb 2002 14:34:35 +0100
https://opencores.org/websvn//websvn/revision?repname=ata&path=%2F&rev=28
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renamed all files to 'atahost_***.vhd'
broke-up 'counter.vhd' into 'ud_cnt.vhd' and 'ro_cnt. ...
https://opencores.org/websvn//websvn/revision?repname=ata&path=%2F&rev=27
<div><strong>Rev 27 - rherveille</strong> (23 file(s) modified)</div><div>renamed all files to 'atahost_***.vhd'<br />
broke-up 'counter.vhd' into 'ud_cnt.vhd' and 'ro_cnt.vhd'<br />
changed ...</div>- /trunk/rtl/vhdl/ocidec3/atahost.vhd<br />+ /trunk/rtl/vhdl/ocidec3/atahost_controller.vhd<br />+ /trunk/rtl/vhdl/ocidec3/atahost_dma_actrl.vhd<br />+ /trunk/rtl/vhdl/ocidec3/atahost_dma_tctrl.vhd<br />+ /trunk/rtl/vhdl/ocidec3/atahost_fifo.vhd<br />+ /trunk/rtl/vhdl/ocidec3/atahost_lfsr.vhd<br />+ /trunk/rtl/vhdl/ocidec3/atahost_pio_actrl.vhd<br />+ /trunk/rtl/vhdl/ocidec3/atahost_pio_controller.vhd<br />+ /trunk/rtl/vhdl/ocidec3/atahost_pio_tctrl.vhd<br />+ /trunk/rtl/vhdl/ocidec3/atahost_reg_buf.vhd<br />+ /trunk/rtl/vhdl/ocidec3/atahost_top.vhd<br />+ /trunk/rtl/vhdl/ocidec3/atahost_wb_slave.vhd<br />- /trunk/rtl/vhdl/ocidec3/controller.vhd<br />- /trunk/rtl/vhdl/ocidec3/counter.vhd<br />- /trunk/rtl/vhdl/ocidec3/dma_actrl.vhd<br />- /trunk/rtl/vhdl/ocidec3/dma_tctrl.vhd<br />- /trunk/rtl/vhdl/ocidec3/fifo.vhd<br />- /trunk/rtl/vhdl/ocidec3/lfsr.vhd<br />- /trunk/rtl/vhdl/ocidec3/piocontroller.vhd<br />- /trunk/rtl/vhdl/ocidec3/pio_actrl.vhd<br />- /trunk/rtl/vhdl/ocidec3/pio_tctrl.vhd<br />- /trunk/rtl/vhdl/ocidec3/reg_buf.vhd<br />~ /trunk/rtl/vhdl/ocidec3/revision_history.txt<br />
rherveille
Mon, 18 Feb 2002 14:32:12 +0100
https://opencores.org/websvn//websvn/revision?repname=ata&path=%2F&rev=27
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renamed 'atahost.vhd' to 'atahost_top.vhd'
renamed 'controller.vhd' to 'atahost_controller. ...
https://opencores.org/websvn//websvn/revision?repname=ata&path=%2F&rev=26
<div><strong>Rev 26 - rherveille</strong> (11 file(s) modified)</div><div>renamed 'atahost.vhd' to 'atahost_top.vhd'<br />
renamed 'controller.vhd' to 'atahost_controller.vhd'<br />
renamed 'pio_tctrl.vhd' to 'atahost_pio_tctrl.vhd'<br />
broke-up ...</div>- /trunk/rtl/vhdl/ocidec2/atahost.vhd<br />+ /trunk/rtl/vhdl/ocidec2/atahost_controller.vhd<br />+ /trunk/rtl/vhdl/ocidec2/atahost_pio_actrl.vhd<br />+ /trunk/rtl/vhdl/ocidec2/atahost_pio_tctrl.vhd<br />+ /trunk/rtl/vhdl/ocidec2/atahost_top.vhd<br />+ /trunk/rtl/vhdl/ocidec2/atahost_wb_slave.vhd<br />- /trunk/rtl/vhdl/ocidec2/controller.vhd<br />- /trunk/rtl/vhdl/ocidec2/counter.vhd<br />- /trunk/rtl/vhdl/ocidec2/pio_actrl.vhd<br />- /trunk/rtl/vhdl/ocidec2/pio_tctrl.vhd<br />~ /trunk/rtl/vhdl/ocidec2/revision_history.txt<br />
rherveille
Mon, 18 Feb 2002 14:30:48 +0100
https://opencores.org/websvn//websvn/revision?repname=ata&path=%2F&rev=26
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renamed 'atahost.vhd' to 'atahost_top.vhd'
renamed 'controller.vhd' to 'atahost_controller. ...
https://opencores.org/websvn//websvn/revision?repname=ata&path=%2F&rev=25
<div><strong>Rev 25 - rherveille</strong> (9 file(s) modified)</div><div>renamed 'atahost.vhd' to 'atahost_top.vhd'<br />
renamed 'controller.vhd' to 'atahost_controller.vhd'<br />
renamed 'pio_tctrl.vhd' to 'atahost_pio_tctrl.vhd'<br />
broke-up ...</div>- /trunk/rtl/vhdl/ocidec1/atahost.vhd<br />+ /trunk/rtl/vhdl/ocidec1/atahost_controller.vhd<br />+ /trunk/rtl/vhdl/ocidec1/atahost_pio_tctrl.vhd<br />+ /trunk/rtl/vhdl/ocidec1/atahost_top.vhd<br />+ /trunk/rtl/vhdl/ocidec1/atahost_wb_slave.vhd<br />- /trunk/rtl/vhdl/ocidec1/controller.vhd<br />- /trunk/rtl/vhdl/ocidec1/counter.vhd<br />- /trunk/rtl/vhdl/ocidec1/pio_tctrl.vhd<br />~ /trunk/rtl/vhdl/ocidec1/revision_history.txt<br />
rherveille
Mon, 18 Feb 2002 14:29:39 +0100
https://opencores.org/websvn//websvn/revision?repname=ata&path=%2F&rev=25
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Initial Verilog HDL release
https://opencores.org/websvn//websvn/revision?repname=ata&path=%2F&rev=24
<div><strong>Rev 24 - rherveille</strong> (10 file(s) modified)</div><div>Initial Verilog HDL release</div>+ /trunk/rtl/verilog/ocidec-2<br />+ /trunk/rtl/verilog/ocidec-2/atahost_controller.v<br />+ /trunk/rtl/verilog/ocidec-2/atahost_pio_actrl.v<br />+ /trunk/rtl/verilog/ocidec-2/atahost_pio_tctrl.v<br />+ /trunk/rtl/verilog/ocidec-2/atahost_top.v<br />+ /trunk/rtl/verilog/ocidec-2/atahost_wb_slave.v<br />+ /trunk/rtl/verilog/ocidec-2/revision_history.txt<br />+ /trunk/rtl/verilog/ocidec-2/ro_cnt.v<br />+ /trunk/rtl/verilog/ocidec-2/timescale.v<br />+ /trunk/rtl/verilog/ocidec-2/ud_cnt.v<br />
rherveille
Mon, 18 Feb 2002 14:26:46 +0100
https://opencores.org/websvn//websvn/revision?repname=ata&path=%2F&rev=24
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Moved wishbone interface into 'atahost_wb_slave.v'
Major revisions in all cores.
https://opencores.org/websvn//websvn/revision?repname=ata&path=%2F&rev=23
<div><strong>Rev 23 - rherveille</strong> (5 file(s) modified)</div><div>Moved wishbone interface into 'atahost_wb_slave.v'<br />
Major revisions in all cores.</div>~ /trunk/rtl/verilog/ocidec-1/atahost_controller.v<br />~ /trunk/rtl/verilog/ocidec-1/atahost_pio_tctrl.v<br />~ /trunk/rtl/verilog/ocidec-1/atahost_top.v<br />+ /trunk/rtl/verilog/ocidec-1/atahost_wb_slave.v<br />~ /trunk/rtl/verilog/ocidec-1/revision_history.txt<br />
rherveille
Mon, 18 Feb 2002 14:25:43 +0100
https://opencores.org/websvn//websvn/revision?repname=ata&path=%2F&rev=23
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Added disclaimer
Added CVS information
Changed core for new internal counter libraries ...
https://opencores.org/websvn//websvn/revision?repname=ata&path=%2F&rev=22
<div><strong>Rev 22 - rherveille</strong> (6 file(s) modified)</div><div>Added disclaimer<br />
Added CVS information<br />
Changed core for new internal counter libraries ...</div>~ /trunk/rtl/verilog/ocidec-1/atahost_controller.v<br />~ /trunk/rtl/verilog/ocidec-1/atahost_pio_tctrl.v<br />~ /trunk/rtl/verilog/ocidec-1/atahost_top.v<br />~ /trunk/rtl/verilog/ocidec-1/revision_history.txt<br />~ /trunk/rtl/verilog/ocidec-1/ro_cnt.v<br />~ /trunk/rtl/verilog/ocidec-1/ud_cnt.v<br />
rherveille
Sat, 16 Feb 2002 10:42:17 +0100
https://opencores.org/websvn//websvn/revision?repname=ata&path=%2F&rev=22
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Changed atahost_top pin-information.
https://opencores.org/websvn//websvn/revision?repname=ata&path=%2F&rev=21
<div><strong>Rev 21 - rherveille</strong> (1 file(s) modified)</div><div>Changed atahost_top pin-information.</div>~ /trunk/bench/verilog/test_bench_top.v<br />
rherveille
Sat, 16 Feb 2002 10:41:16 +0100
https://opencores.org/websvn//websvn/revision?repname=ata&path=%2F&rev=21
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Some minor bug fixes
https://opencores.org/websvn//websvn/revision?repname=ata&path=%2F&rev=20
<div><strong>Rev 20 - rherveille</strong> (1 file(s) modified)</div><div>Some minor bug fixes</div>~ /trunk/rtl/vhdl/ocidec3/dma_actrl.vhd<br />
rherveille
Thu, 25 Oct 2001 14:46:39 +0100
https://opencores.org/websvn//websvn/revision?repname=ata&path=%2F&rev=20
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Changed RST_LVL define to parameter.
Removed atahost_define.v
https://opencores.org/websvn//websvn/revision?repname=ata&path=%2F&rev=19
<div><strong>Rev 19 - rherveille</strong> (3 file(s) modified)</div><div>Changed RST_LVL define to parameter.<br />
Removed atahost_define.v</div>- /trunk/rtl/verilog/ocidec-1/atahost_define.v<br />~ /trunk/rtl/verilog/ocidec-1/atahost_top.v<br />~ /trunk/rtl/verilog/ocidec-1/revision_history.txt<br />
rherveille
Tue, 16 Oct 2001 09:00:08 +0100
https://opencores.org/websvn//websvn/revision?repname=ata&path=%2F&rev=19
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Changed dd_padoen_o portname into dd_pad_oe_o, because it is active high.
https://opencores.org/websvn//websvn/revision?repname=ata&path=%2F&rev=18
<div><strong>Rev 18 - rherveille</strong> (1 file(s) modified)</div><div>Changed dd_padoen_o portname into dd_pad_oe_o, because it is active high.</div>~ /trunk/rtl/verilog/ocidec-1/atahost_top.v<br />
rherveille
Tue, 18 Sep 2001 05:36:50 +0100
https://opencores.org/websvn//websvn/revision?repname=ata&path=%2F&rev=18
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Changed top-level. Made asynchronous reset programmable.
https://opencores.org/websvn//websvn/revision?repname=ata&path=%2F&rev=17
<div><strong>Rev 17 - rherveille</strong> (3 file(s) modified)</div><div>Changed top-level. Made asynchronous reset programmable.</div>+ /trunk/rtl/verilog/ocidec-1/atahost_define.v<br />~ /trunk/rtl/verilog/ocidec-1/atahost_top.v<br />~ /trunk/rtl/verilog/ocidec-1/revision_history.txt<br />
rherveille
Wed, 12 Sep 2001 08:43:40 +0100
https://opencores.org/websvn//websvn/revision?repname=ata&path=%2F&rev=17
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- Added Test Bench
- Added Synthesis scripts for Design Compiler
- ...
https://opencores.org/websvn//websvn/revision?repname=ata&path=%2F&rev=16
<div><strong>Rev 16 - rudi</strong> (19 file(s) modified)</div><div>- Added Test Bench<br />
- Added Synthesis scripts for Design Compiler<br />
- ...</div>+ /trunk/bench<br />+ /trunk/bench/verilog<br />+ /trunk/bench/verilog/ata_device.v<br />+ /trunk/bench/verilog/tests.v<br />+ /trunk/bench/verilog/test_bench_top.v<br />+ /trunk/bench/verilog/wb_mast_model.v<br />+ /trunk/bench/verilog/wb_model_defines.v<br />+ /trunk/bench/verilog/wb_slv_model.v<br />~ /trunk/rtl/verilog/ocidec-1/atahost_top.v<br />+ /trunk/sim<br />+ /trunk/sim/rtl_sim<br />+ /trunk/sim/rtl_sim/bin<br />+ /trunk/sim/rtl_sim/bin/Makefile<br />+ /trunk/syn<br />+ /trunk/syn/bin<br />+ /trunk/syn/bin/comp.dc<br />+ /trunk/syn/bin/design_spec.dc<br />+ /trunk/syn/bin/lib_spec.dc<br />+ /trunk/syn/bin/read.dc<br />
rudi
Thu, 16 Aug 2001 10:01:05 +0100
https://opencores.org/websvn//websvn/revision?repname=ata&path=%2F&rev=16
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