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https://opencores.org/websvn//websvn/listing?repname=c16&path=%2F&
Sat, 13 Jun 2026 22:30:21 +0100
FeedCreator 1.7.2
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changed to newer gcc/bison versions
https://opencores.org/websvn//websvn/revision?repname=c16&path=%2F&rev=33
<div><strong>Rev 33 - jsauermann</strong> (4 file(s) modified)</div><div>changed to newer gcc/bison versions</div>~ /c16/trunk/asm/assembler.bison<br />~ /c16/trunk/asm/assembler.exe<br />~ /c16/trunk/asm/assembler.flex<br />~ /c16/trunk/asm/Makefile<br />
jsauermann
Sun, 05 Aug 2012 18:04:07 +0100
https://opencores.org/websvn//websvn/revision?repname=c16&path=%2F&rev=33
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changed to newer gcc/bison versions
https://opencores.org/websvn//websvn/revision?repname=c16&path=%2F&rev=32
<div><strong>Rev 32 - jsauermann</strong> (1 file(s) modified)</div><div>changed to newer gcc/bison versions</div>~ /c16/trunk/sim/Makefile<br />
jsauermann
Sun, 05 Aug 2012 16:54:52 +0100
https://opencores.org/websvn//websvn/revision?repname=c16&path=%2F&rev=32
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changed to newer gcc/bison versions
https://opencores.org/websvn//websvn/revision?repname=c16&path=%2F&rev=31
<div><strong>Rev 31 - jsauermann</strong> (2 file(s) modified)</div><div>changed to newer gcc/bison versions</div>~ /c16/trunk/memory/Makefile<br />~ /c16/trunk/memory/makemem.exe<br />
jsauermann
Sun, 05 Aug 2012 16:53:29 +0100
https://opencores.org/websvn//websvn/revision?repname=c16&path=%2F&rev=31
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changed to newer gcc/bison versions
https://opencores.org/websvn//websvn/revision?repname=c16&path=%2F&rev=30
<div><strong>Rev 30 - jsauermann</strong> (5 file(s) modified)</div><div>changed to newer gcc/bison versions</div>~ /c16/trunk/asm/assembler.bison<br />~ /c16/trunk/asm/assembler.cc<br />~ /c16/trunk/asm/assembler.exe<br />~ /c16/trunk/asm/assembler.flex<br />~ /c16/trunk/asm/Makefile<br />
jsauermann
Sun, 05 Aug 2012 16:51:08 +0100
https://opencores.org/websvn//websvn/revision?repname=c16&path=%2F&rev=30
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fixed problems reported by buaa.byl
https://opencores.org/websvn//websvn/revision?repname=c16&path=%2F&rev=29
<div><strong>Rev 29 - jsauermann</strong> (8 file(s) modified)</div><div>fixed problems reported by buaa.byl</div>~ /c16/trunk/compiler/ansic.flex<br />~ /c16/trunk/compiler/Backend.cc<br />~ /c16/trunk/compiler/cc80.cc<br />~ /c16/trunk/compiler/cc80.exe<br />~ /c16/trunk/compiler/List.hh<br />~ /c16/trunk/compiler/Makefile<br />- /c16/trunk/compiler/Makefile~<br />~ /c16/trunk/compiler/Node.cc<br />
jsauermann
Sun, 05 Aug 2012 15:46:30 +0100
https://opencores.org/websvn//websvn/revision?repname=c16&path=%2F&rev=29
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Added old uploaded documents to new repository.
https://opencores.org/websvn//websvn/revision?repname=c16&path=%2F&rev=28
<div><strong>Rev 28 - root</strong> (5 file(s) modified)</div><div>Added old uploaded documents to new repository.</div>- /c16/web_uploads/oc_checkin.sh<br />- /c16/web_uploads/oc_cvs_checkin.sh<br />- /c16/web_uploads/svn_checkin.log<br />- /c16/web_uploads/svn_checkin.sh<br />- /c16/web_uploads/temp.sh<br />
root
Tue, 10 Mar 2009 12:36:35 +0100
https://opencores.org/websvn//websvn/revision?repname=c16&path=%2F&rev=28
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Added old uploaded documents to new repository.
https://opencores.org/websvn//websvn/revision?repname=c16&path=%2F&rev=27
<div><strong>Rev 27 - root</strong> (5 file(s) modified)</div><div>Added old uploaded documents to new repository.</div>+ /c16/web_uploads/oc_checkin.sh<br />+ /c16/web_uploads/oc_cvs_checkin.sh<br />+ /c16/web_uploads/svn_checkin.log<br />+ /c16/web_uploads/svn_checkin.sh<br />+ /c16/web_uploads/temp.sh<br />
root
Mon, 09 Mar 2009 19:34:19 +0100
https://opencores.org/websvn//websvn/revision?repname=c16&path=%2F&rev=27
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New directory structure.
https://opencores.org/websvn//websvn/revision?repname=c16&path=%2F&rev=26
<div><strong>Rev 26 - root</strong> (8 file(s) modified)</div><div>New directory structure.</div>- /branches<br />+ /c16<br />+ /c16/branches<br />+ /c16/tags<br />+ /c16/trunk<br />+ /c16/web_uploads<br />- /tags<br />- /trunk<br />
root
Mon, 09 Mar 2009 19:33:21 +0100
https://opencores.org/websvn//websvn/revision?repname=c16&path=%2F&rev=26
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XOR bug fixed
https://opencores.org/websvn//websvn/revision?repname=c16&path=%2F&rev=25
<div><strong>Rev 25 - jsauermann</strong> (1 file(s) modified)</div><div>XOR bug fixed</div>~ /trunk/vhdl/alu8.vhd<br />
jsauermann
Sun, 16 Apr 2006 12:45:15 +0100
https://opencores.org/websvn//websvn/revision?repname=c16&path=%2F&rev=25
-
no message
https://opencores.org/websvn//websvn/revision?repname=c16&path=%2F&rev=24
<div><strong>Rev 24 - jsauermann</strong> (1 file(s) modified)</div><div>no message</div>~ /trunk/rtos.c<br />
jsauermann
Sun, 06 Nov 2005 14:35:47 +0100
https://opencores.org/websvn//websvn/revision?repname=c16&path=%2F&rev=24
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Fixed problem with wishbone wait-states
https://opencores.org/websvn//websvn/revision?repname=c16&path=%2F&rev=23
<div><strong>Rev 23 - jsauermann</strong> (1 file(s) modified)</div><div>Fixed problem with wishbone wait-states</div>~ /trunk/vhdl/cpu_engine.vhd<br />
jsauermann
Sun, 19 Jun 2005 15:27:44 +0100
https://opencores.org/websvn//websvn/revision?repname=c16&path=%2F&rev=23
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This commit was manufactured by cvs2svn to create tag 'Rev_XLNX_7'.
https://opencores.org/websvn//websvn/revision?repname=c16&path=%2F&rev=22
<div><strong>Rev 22 - </strong> (35 file(s) modified)</div><div>This commit was manufactured by cvs2svn to create tag 'Rev_XLNX_7'.</div>+ /tags/Rev_XLNX_7<br />- /tags/Rev_XLNX_7/asm<br />- /tags/Rev_XLNX_7/bin2array.cc<br />- /tags/Rev_XLNX_7/bin2array.exe<br />- /tags/Rev_XLNX_7/compiler<br />- /tags/Rev_XLNX_7/doc<br />- /tags/Rev_XLNX_7/loader.asm<br />- /tags/Rev_XLNX_7/loader.bin<br />- /tags/Rev_XLNX_7/loader.c<br />- /tags/Rev_XLNX_7/loader.ihx<br />- /tags/Rev_XLNX_7/loader.lst<br />- /tags/Rev_XLNX_7/loader.sym<br />- /tags/Rev_XLNX_7/Makefile<br />- /tags/Rev_XLNX_7/memory<br />- /tags/Rev_XLNX_7/polled.c<br />- /tags/Rev_XLNX_7/rtos.asm<br />- /tags/Rev_XLNX_7/rtos.bin<br />- /tags/Rev_XLNX_7/rtos.c<br />- /tags/Rev_XLNX_7/rtos.ihx<br />- /tags/Rev_XLNX_7/rtos.lst<br />- /tags/Rev_XLNX_7/rtos.sym<br />- /tags/Rev_XLNX_7/sim<br />- /tags/Rev_XLNX_7/test.asm<br />- /tags/Rev_XLNX_7/test.bin<br />- /tags/Rev_XLNX_7/test.c<br />- /tags/Rev_XLNX_7/test.ihx<br />- /tags/Rev_XLNX_7/test.lst<br />- /tags/Rev_XLNX_7/test.sym<br />- /tags/Rev_XLNX_7/test.txt<br />- /tags/Rev_XLNX_7/tty.cc<br />- /tags/Rev_XLNX_7/tty.exe<br />- /tags/Rev_XLNX_7/vhdl/board_cpu.bit<br />- /tags/Rev_XLNX_7/vhdl/cpu16.ise<br />- /tags/Rev_XLNX_7/vhdl/cpu16.npl<br />- /tags/Rev_XLNX_7/vhdl/test.tbw<br />
Sun, 19 Jun 2005 10:07:48 +0100
https://opencores.org/websvn//websvn/revision?repname=c16&path=%2F&rev=22
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Changes for Xilinx Proj. Nav. 7.1.02i
https://opencores.org/websvn//websvn/revision?repname=c16&path=%2F&rev=21
<div><strong>Rev 21 - jsauermann</strong> (6 file(s) modified)</div><div>Changes for Xilinx Proj. Nav. 7.1.02i</div>~ /trunk/vhdl/board_cpu.bit<br />+ /trunk/vhdl/cpu16.ise<br />~ /trunk/vhdl/cpu_engine.vhd<br />~ /trunk/vhdl/memory.vhd<br />~ /trunk/vhdl/opcode_decoder.vhd<br />~ /trunk/vhdl/opcode_fetch.vhd<br />
jsauermann
Sun, 19 Jun 2005 10:07:47 +0100
https://opencores.org/websvn//websvn/revision?repname=c16&path=%2F&rev=21
-
This commit was manufactured by cvs2svn to create tag 'Rev_XLNX_5'.
https://opencores.org/websvn//websvn/revision?repname=c16&path=%2F&rev=20
<div><strong>Rev 20 - </strong> (34 file(s) modified)</div><div>This commit was manufactured by cvs2svn to create tag 'Rev_XLNX_5'.</div>+ /tags/Rev_XLNX_5<br />- /tags/Rev_XLNX_5/asm<br />- /tags/Rev_XLNX_5/bin2array.cc<br />- /tags/Rev_XLNX_5/bin2array.exe<br />- /tags/Rev_XLNX_5/compiler<br />- /tags/Rev_XLNX_5/doc<br />- /tags/Rev_XLNX_5/loader.asm<br />- /tags/Rev_XLNX_5/loader.bin<br />- /tags/Rev_XLNX_5/loader.c<br />- /tags/Rev_XLNX_5/loader.ihx<br />- /tags/Rev_XLNX_5/loader.lst<br />- /tags/Rev_XLNX_5/loader.sym<br />- /tags/Rev_XLNX_5/Makefile<br />- /tags/Rev_XLNX_5/memory<br />- /tags/Rev_XLNX_5/polled.c<br />- /tags/Rev_XLNX_5/rtos.asm<br />- /tags/Rev_XLNX_5/rtos.bin<br />- /tags/Rev_XLNX_5/rtos.c<br />- /tags/Rev_XLNX_5/rtos.ihx<br />- /tags/Rev_XLNX_5/rtos.lst<br />- /tags/Rev_XLNX_5/rtos.sym<br />- /tags/Rev_XLNX_5/sim<br />- /tags/Rev_XLNX_5/test.asm<br />- /tags/Rev_XLNX_5/test.bin<br />- /tags/Rev_XLNX_5/test.c<br />- /tags/Rev_XLNX_5/test.ihx<br />- /tags/Rev_XLNX_5/test.lst<br />- /tags/Rev_XLNX_5/test.sym<br />- /tags/Rev_XLNX_5/test.txt<br />- /tags/Rev_XLNX_5/tty.cc<br />- /tags/Rev_XLNX_5/tty.exe<br />- /tags/Rev_XLNX_5/vhdl/board_cpu.bit<br />- /tags/Rev_XLNX_5/vhdl/cpu16.npl<br />- /tags/Rev_XLNX_5/vhdl/test.tbw<br />
Sun, 05 Dec 2004 13:26:36 +0100
https://opencores.org/websvn//websvn/revision?repname=c16&path=%2F&rev=20
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FPGA Pin desription added.
https://opencores.org/websvn//websvn/revision?repname=c16&path=%2F&rev=19
<div><strong>Rev 19 - jsauermann</strong> (1 file(s) modified)</div><div>FPGA Pin desription added.</div>~ /trunk/vhdl/board_cpu.ucf<br />
jsauermann
Sun, 05 Dec 2004 13:26:35 +0100
https://opencores.org/websvn//websvn/revision?repname=c16&path=%2F&rev=19
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Assert ENABLE_INT and DISABLE_INT only in M1.
Thanks to Riccardo Cerulli-Irelly.
Requires ...
https://opencores.org/websvn//websvn/revision?repname=c16&path=%2F&rev=18
<div><strong>Rev 18 - jsauermann</strong> (1 file(s) modified)</div><div>Assert ENABLE_INT and DISABLE_INT only in M1.<br />
Thanks to Riccardo Cerulli-Irelly.<br />
Requires ...</div>~ /trunk/vhdl/board_cpu.bit<br />
jsauermann
Sun, 08 Feb 2004 14:21:00 +0100
https://opencores.org/websvn//websvn/revision?repname=c16&path=%2F&rev=18
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Assert ENABLE_INT and DISABLE_INT only in M1.
Thanks to Riccardo Cerulli-Irelly.
Requires ...
https://opencores.org/websvn//websvn/revision?repname=c16&path=%2F&rev=17
<div><strong>Rev 17 - jsauermann</strong> (1 file(s) modified)</div><div>Assert ENABLE_INT and DISABLE_INT only in M1.<br />
Thanks to Riccardo Cerulli-Irelly.<br />
Requires ...</div>~ /trunk/vhdl/opcode_decoder.vhd<br />
jsauermann
Sun, 08 Feb 2004 14:13:29 +0100
https://opencores.org/websvn//websvn/revision?repname=c16&path=%2F&rev=17
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Enable interrupts at start of each task.
This fix is required ...
https://opencores.org/websvn//websvn/revision?repname=c16&path=%2F&rev=16
<div><strong>Rev 16 - jsauermann</strong> (6 file(s) modified)</div><div>Enable interrupts at start of each task.<br />
This fix is required ...</div>~ /trunk/rtos.asm<br />~ /trunk/rtos.bin<br />~ /trunk/rtos.c<br />~ /trunk/rtos.ihx<br />~ /trunk/rtos.lst<br />~ /trunk/rtos.sym<br />
jsauermann
Sun, 08 Feb 2004 14:06:10 +0100
https://opencores.org/websvn//websvn/revision?repname=c16&path=%2F&rev=16
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sample ucf file
https://opencores.org/websvn//websvn/revision?repname=c16&path=%2F&rev=15
<div><strong>Rev 15 - jsauermann</strong> (1 file(s) modified)</div><div>sample ucf file</div>+ /trunk/vhdl/board_cpu.ucf<br />
jsauermann
Wed, 31 Dec 2003 11:03:31 +0100
https://opencores.org/websvn//websvn/revision?repname=c16&path=%2F&rev=15
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no message
https://opencores.org/websvn//websvn/revision?repname=c16&path=%2F&rev=14
<div><strong>Rev 14 - jsauermann</strong> (1 file(s) modified)</div><div>no message</div>+ /trunk/doc/data_core.pdf<br />
jsauermann
Tue, 23 Dec 2003 09:59:38 +0100
https://opencores.org/websvn//websvn/revision?repname=c16&path=%2F&rev=14
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