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dbg_interface WebSVN RSS feed - dbg_interface https://opencores.org/websvn//websvn/listing?repname=dbg_interface&path=%2F& Mon, 24 Aug 2026 00:23:09 +0100 FeedCreator 1.7.2 ... https://opencores.org/websvn//websvn/revision?repname=dbg_interface&path=%2F&rev=158 <div><strong>Rev 158 - root</strong> (9 file(s) modified)</div><div>...</div>- /branches<br />+ /dbg_interface<br />+ /dbg_interface/branches<br />+ /dbg_interface/tags<br />+ /dbg_interface/trunk<br />+ /dbg_interface/web_uploads<br />- /tags<br />- /trunk<br />- /web_uploads<br /> root Tue, 10 Mar 2009 19:53:58 +0100 https://opencores.org/websvn//websvn/revision?repname=dbg_interface&path=%2F&rev=158 ... https://opencores.org/websvn//websvn/revision?repname=dbg_interface&path=%2F&rev=157 <div><strong>Rev 157 - root</strong> (2 file(s) modified)</div><div>...</div>+ /web_uploads<br />+ /web_uploads/index.shtml<br /> root Tue, 10 Mar 2009 13:57:44 +0100 https://opencores.org/websvn//websvn/revision?repname=dbg_interface&path=%2F&rev=157 Version 3 of the document. https://opencores.org/websvn//websvn/revision?repname=dbg_interface&path=%2F&rev=156 <div><strong>Rev 156 - igorm</strong> (2 file(s) modified)</div><div>Version 3 of the document.</div>~ /trunk/doc/DbgSupp.pdf<br />~ /trunk/doc/src/DbgSupp.doc<br /> igorm Wed, 14 Apr 2004 12:07:17 +0100 https://opencores.org/websvn//websvn/revision?repname=dbg_interface&path=%2F&rev=156 This commit was manufactured by cvs2svn to create tag 'rel_25'. https://opencores.org/websvn//websvn/revision?repname=dbg_interface&path=%2F&rev=155 <div><strong>Rev 155 - </strong> (4 file(s) modified)</div><div>This commit was manufactured by cvs2svn to create tag 'rel_25'.</div>+ /tags/rel_25<br />- /tags/rel_25/bench<br />- /tags/rel_25/doc<br />- /tags/rel_25/sim<br /> Thu, 08 Apr 2004 14:15:13 +0100 https://opencores.org/websvn//websvn/revision?repname=dbg_interface&path=%2F&rev=155 This commit was manufactured by cvs2svn to create tag 'asyst_3'. https://opencores.org/websvn//websvn/revision?repname=dbg_interface&path=%2F&rev=154 <div><strong>Rev 154 - </strong> (4 file(s) modified)</div><div>This commit was manufactured by cvs2svn to create tag 'asyst_3'.</div>+ /tags/asyst_3<br />- /tags/asyst_3/bench<br />- /tags/asyst_3/doc<br />- /tags/asyst_3/sim<br /> Thu, 08 Apr 2004 14:15:12 +0100 https://opencores.org/websvn//websvn/revision?repname=dbg_interface&path=%2F&rev=154 This commit was manufactured by cvs2svn to create tag 'asyst_2'. https://opencores.org/websvn//websvn/revision?repname=dbg_interface&path=%2F&rev=153 <div><strong>Rev 153 - </strong> (4 file(s) modified)</div><div>This commit was manufactured by cvs2svn to create tag 'asyst_2'.</div>+ /tags/asyst_2<br />- /tags/asyst_2/bench<br />- /tags/asyst_2/doc<br />- /tags/asyst_2/sim<br /> Thu, 08 Apr 2004 14:15:11 +0100 https://opencores.org/websvn//websvn/revision?repname=dbg_interface&path=%2F&rev=153 CTRL READ fixed. Stall bit was not shifted out OK. ... https://opencores.org/websvn//websvn/revision?repname=dbg_interface&path=%2F&rev=152 <div><strong>Rev 152 - igorm</strong> (1 file(s) modified)</div><div>CTRL READ fixed. Stall bit was not shifted out OK. ...</div>~ /trunk/rtl/verilog/dbg_cpu.v<br /> igorm Thu, 08 Apr 2004 14:15:10 +0100 https://opencores.org/websvn//websvn/revision?repname=dbg_interface&path=%2F&rev=152 This commit was manufactured by cvs2svn to create tag 'rel_24'. https://opencores.org/websvn//websvn/revision?repname=dbg_interface&path=%2F&rev=151 <div><strong>Rev 151 - </strong> (4 file(s) modified)</div><div>This commit was manufactured by cvs2svn to create tag 'rel_24'.</div>+ /tags/rel_24<br />- /tags/rel_24/bench<br />- /tags/rel_24/doc<br />- /tags/rel_24/sim<br /> Wed, 07 Apr 2004 19:28:56 +0100 https://opencores.org/websvn//websvn/revision?repname=dbg_interface&path=%2F&rev=151 Zero is shifted out when CTRL_READ command is active. https://opencores.org/websvn//websvn/revision?repname=dbg_interface&path=%2F&rev=150 <div><strong>Rev 150 - igorm</strong> (1 file(s) modified)</div><div>Zero is shifted out when CTRL_READ command is active.</div>~ /trunk/rtl/verilog/dbg_cpu.v<br /> igorm Wed, 07 Apr 2004 19:28:55 +0100 https://opencores.org/websvn//websvn/revision?repname=dbg_interface&path=%2F&rev=150 This commit was manufactured by cvs2svn to create tag 'rev_23'. https://opencores.org/websvn//websvn/revision?repname=dbg_interface&path=%2F&rev=149 <div><strong>Rev 149 - </strong> (1 file(s) modified)</div><div>This commit was manufactured by cvs2svn to create tag 'rev_23'.</div>+ /tags/rev_23<br /> Mon, 05 Apr 2004 13:52:56 +0100 https://opencores.org/websvn//websvn/revision?repname=dbg_interface&path=%2F&rev=149 This commit was manufactured by cvs2svn to create tag 'rel_23'. https://opencores.org/websvn//websvn/revision?repname=dbg_interface&path=%2F&rev=148 <div><strong>Rev 148 - </strong> (1 file(s) modified)</div><div>This commit was manufactured by cvs2svn to create tag 'rel_23'.</div>+ /tags/rel_23<br /> Mon, 05 Apr 2004 13:52:55 +0100 https://opencores.org/websvn//websvn/revision?repname=dbg_interface&path=%2F&rev=148 CPU_WR_CTRL and CPU_RD_CTRL defines changed. https://opencores.org/websvn//websvn/revision?repname=dbg_interface&path=%2F&rev=147 <div><strong>Rev 147 - igorm</strong> (1 file(s) modified)</div><div>CPU_WR_CTRL and CPU_RD_CTRL defines changed.</div>~ /trunk/rtl/verilog/dbg_cpu_defines.v<br /> igorm Mon, 05 Apr 2004 13:52:54 +0100 https://opencores.org/websvn//websvn/revision?repname=dbg_interface&path=%2F&rev=147 Changes for the FormalPRO. https://opencores.org/websvn//websvn/revision?repname=dbg_interface&path=%2F&rev=146 <div><strong>Rev 146 - igorm</strong> (1 file(s) modified)</div><div>Changes for the FormalPRO.</div>~ /trunk/rtl/verilog/dbg_wb.v<br /> igorm Thu, 01 Apr 2004 17:21:22 +0100 https://opencores.org/websvn//websvn/revision?repname=dbg_interface&path=%2F&rev=146 Support for 2 CPUs added. https://opencores.org/websvn//websvn/revision?repname=dbg_interface&path=%2F&rev=145 <div><strong>Rev 145 - igorm</strong> (1 file(s) modified)</div><div>Support for 2 CPUs added.</div>~ /trunk/bench/verilog/dbg_tb.v<br /> igorm Thu, 01 Apr 2004 12:50:19 +0100 https://opencores.org/websvn//websvn/revision?repname=dbg_interface&path=%2F&rev=145 Port names and defines for the supported CPUs changed. https://opencores.org/websvn//websvn/revision?repname=dbg_interface&path=%2F&rev=144 <div><strong>Rev 144 - igorm</strong> (3 file(s) modified)</div><div>Port names and defines for the supported CPUs changed.</div>~ /trunk/rtl/verilog/dbg_defines.v<br />~ /trunk/rtl/verilog/dbg_top.v<br />~ /trunk/rtl/verilog/dbg_wb.v<br /> igorm Thu, 01 Apr 2004 11:56:59 +0100 https://opencores.org/websvn//websvn/revision?repname=dbg_interface&path=%2F&rev=144 Signals for easier debugging removed. https://opencores.org/websvn//websvn/revision?repname=dbg_interface&path=%2F&rev=143 <div><strong>Rev 143 - igorm</strong> (1 file(s) modified)</div><div>Signals for easier debugging removed.</div>~ /trunk/rtl/verilog/dbg_cpu.v<br /> igorm Thu, 01 Apr 2004 10:22:45 +0100 https://opencores.org/websvn//websvn/revision?repname=dbg_interface&path=%2F&rev=143 Typo fixed. https://opencores.org/websvn//websvn/revision?repname=dbg_interface&path=%2F&rev=142 <div><strong>Rev 142 - igorm</strong> (1 file(s) modified)</div><div>Typo fixed.</div>~ /trunk/bench/verilog/dbg_tb.v<br /> igorm Thu, 01 Apr 2004 09:33:26 +0100 https://opencores.org/websvn//websvn/revision?repname=dbg_interface&path=%2F&rev=142 data_cnt_lim length changed to reduce number of warnings. https://opencores.org/websvn//websvn/revision?repname=dbg_interface&path=%2F&rev=141 <div><strong>Rev 141 - igorm</strong> (5 file(s) modified)</div><div>data_cnt_lim length changed to reduce number of warnings.</div>~ /trunk/bench/verilog/dbg_tb.v<br />~ /trunk/rtl/verilog/dbg_cpu.v<br />~ /trunk/rtl/verilog/dbg_cpu_defines.v<br />~ /trunk/rtl/verilog/dbg_wb.v<br />~ /trunk/rtl/verilog/dbg_wb_defines.v<br /> igorm Wed, 31 Mar 2004 14:34:13 +0100 https://opencores.org/websvn//websvn/revision?repname=dbg_interface&path=%2F&rev=141 CRC checking of incoming CRC added to all tasks. https://opencores.org/websvn//websvn/revision?repname=dbg_interface&path=%2F&rev=140 <div><strong>Rev 140 - igorm</strong> (1 file(s) modified)</div><div>CRC checking of incoming CRC added to all tasks.</div>~ /trunk/bench/verilog/dbg_tb.v<br /> igorm Tue, 30 Mar 2004 23:10:39 +0100 https://opencores.org/websvn//websvn/revision?repname=dbg_interface&path=%2F&rev=140 New release of the debug interface (3rd. release). https://opencores.org/websvn//websvn/revision?repname=dbg_interface&path=%2F&rev=139 <div><strong>Rev 139 - igorm</strong> (16 file(s) modified)</div><div>New release of the debug interface (3rd. release).</div>~ /trunk/bench/verilog/cpu_behavioral.v<br />~ /trunk/bench/verilog/dbg_tb.v<br />~ /trunk/bench/verilog/timescale.v<br />~ /trunk/bench/verilog/wb_model_defines.v<br />~ /trunk/bench/verilog/wb_slave_behavioral.v<br />~ /trunk/rtl/verilog/dbg_cpu.v<br />~ /trunk/rtl/verilog/dbg_cpu_defines.v<br />~ /trunk/rtl/verilog/dbg_cpu_registers.v<br />~ /trunk/rtl/verilog/dbg_crc32_d1.v<br />~ /trunk/rtl/verilog/dbg_defines.v<br />~ /trunk/rtl/verilog/dbg_register.v<br />~ /trunk/rtl/verilog/dbg_top.v<br />~ /trunk/rtl/verilog/dbg_wb.v<br />~ /trunk/rtl/verilog/dbg_wb_defines.v<br />- /trunk/rtl/verilog/jtag_chain.v<br />~ /trunk/sim/rtl_sim/run/wave.do<br /> igorm Sun, 28 Mar 2004 20:28:08 +0100 https://opencores.org/websvn//websvn/revision?repname=dbg_interface&path=%2F&rev=139

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