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light52 WebSVN RSS feed - light52 https://opencores.org/websvn//websvn/listing?repname=light52&path=%2F& Sat, 29 Aug 2026 22:37:16 +0100 FeedCreator 1.7.2 Changed the VHDL simulation logging code to match the SW ... https://opencores.org/websvn//websvn/revision?repname=light52&path=%2F&rev=26 <div><strong>Rev 26 - ja_rd</strong> (1 file(s) modified)</div><div>Changed the VHDL simulation logging code to match the SW ...</div>~ /light52/trunk/vhdl/tb/light52_tb_pkg.vhdl<br /> ja_rd Fri, 06 Dec 2013 21:44:30 +0100 https://opencores.org/websvn//websvn/revision?repname=light52&path=%2F&rev=26 Pre-generated object code packages updated with new test bench. https://opencores.org/websvn//websvn/revision?repname=light52&path=%2F&rev=25 <div><strong>Rev 25 - ja_rd</strong> (2 file(s) modified)</div><div>Pre-generated object code packages updated with new test bench.</div>~ /light52/trunk/test/cpu_test/full_test_pkg.vhdl<br />~ /light52/trunk/test/cpu_test/obj_code_pkg.vhdl<br /> ja_rd Fri, 06 Dec 2013 21:37:53 +0100 https://opencores.org/websvn//websvn/revision?repname=light52&path=%2F&rev=25 Basic CPU test bench modified to catch previously undetected bug ... https://opencores.org/websvn//websvn/revision?repname=light52&path=%2F&rev=24 <div><strong>Rev 24 - ja_rd</strong> (1 file(s) modified)</div><div>Basic CPU test bench modified to catch previously undetected bug ...</div>~ /light52/trunk/test/cpu_test/src/tb51_cpu.a51<br /> ja_rd Fri, 06 Dec 2013 21:36:45 +0100 https://opencores.org/websvn//websvn/revision?repname=light52&path=%2F&rev=24 Fixed CLR.bit when ACC was the target. Implemented solution suggested by ... https://opencores.org/websvn//websvn/revision?repname=light52&path=%2F&rev=23 <div><strong>Rev 23 - ja_rd</strong> (1 file(s) modified)</div><div>Fixed CLR.bit when ACC was the target.<br /> Implemented solution suggested by ...</div>~ /light52/trunk/vhdl/light52_alu.vhdl<br /> ja_rd Fri, 06 Dec 2013 21:36:01 +0100 https://opencores.org/websvn//websvn/revision?repname=light52&path=%2F&rev=23 Fixed comments in object code package generation script. The comments were ... https://opencores.org/websvn//websvn/revision?repname=light52&path=%2F&rev=22 <div><strong>Rev 22 - ja_rd</strong> (1 file(s) modified)</div><div>Fixed comments in object code package generation script.<br /> The comments were ...</div>~ /light52/trunk/tools/build_rom/src/build_rom.py<br /> ja_rd Mon, 18 Feb 2013 18:22:16 +0100 https://opencores.org/websvn//websvn/revision?repname=light52&path=%2F&rev=22 ... https://opencores.org/websvn//websvn/revision?repname=light52&path=%2F&rev=21 <div><strong>Rev 21 - ja_rd</strong> (2 file(s) modified)</div><div>...</div>~ /light52/trunk<br />~ /light52/trunk/sim/light52_irq_tb_wave.do<br /> ja_rd Sun, 03 Feb 2013 13:36:12 +0100 https://opencores.org/websvn//websvn/revision?repname=light52&path=%2F&rev=21 ... https://opencores.org/websvn//websvn/revision?repname=light52&path=%2F&rev=20 <div><strong>Rev 20 - ja_rd</strong> (1 file(s) modified)</div><div>...</div>~ /light52/trunk/boards/avnet_s3aeval/syn/light52_s3aeval/light52_s3aeval.xise<br /> ja_rd Sun, 03 Feb 2013 13:35:09 +0100 https://opencores.org/websvn//websvn/revision?repname=light52&path=%2F&rev=20 Refactor: interrupts made 100% compatible to original: IRQ priority logic implemented ... https://opencores.org/websvn//websvn/revision?repname=light52&path=%2F&rev=19 <div><strong>Rev 19 - ja_rd</strong> (2 file(s) modified)</div><div>Refactor: interrupts made 100% compatible to original:<br /> IRQ priority logic implemented ...</div>~ /light52/trunk/doc/light52_ds.pdf<br />~ /light52/trunk/doc/src/light52_ds.odt<br /> ja_rd Sun, 03 Feb 2013 13:35:01 +0100 https://opencores.org/websvn//websvn/revision?repname=light52&path=%2F&rev=19 Refactor: interrupts made 100% compatible to original: IRQ priority logic implemented ... https://opencores.org/websvn//websvn/revision?repname=light52&path=%2F&rev=18 <div><strong>Rev 18 - ja_rd</strong> (4 file(s) modified)</div><div>Refactor: interrupts made 100% compatible to original:<br /> IRQ priority logic implemented ...</div>~ /light52/trunk/test/include/LIGHT52.MCU<br />~ /light52/trunk/test/irq_test/obj_code_pkg.vhdl<br />~ /light52/trunk/test/irq_test/readme.txt<br />~ /light52/trunk/test/irq_test/src/irq_test.a51<br /> ja_rd Sun, 03 Feb 2013 13:34:40 +0100 https://opencores.org/websvn//websvn/revision?repname=light52&path=%2F&rev=18 Refactor: interrupts made 100% compatible to original: IRQ priority logic implemented ... https://opencores.org/websvn//websvn/revision?repname=light52&path=%2F&rev=17 <div><strong>Rev 17 - ja_rd</strong> (3 file(s) modified)</div><div>Refactor: interrupts made 100% compatible to original:<br /> IRQ priority logic implemented ...</div>~ /light52/trunk/vhdl/light52_cpu.vhdl<br />~ /light52/trunk/vhdl/light52_mcu.vhdl<br />~ /light52/trunk/vhdl/light52_pkg.vhdl<br /> ja_rd Sun, 03 Feb 2013 13:34:21 +0100 https://opencores.org/websvn//websvn/revision?repname=light52&path=%2F&rev=17 Test bench modified: now tests IRAM and SFR addresses when ... https://opencores.org/websvn//websvn/revision?repname=light52&path=%2F&rev=16 <div><strong>Rev 16 - ja_rd</strong> (1 file(s) modified)</div><div>Test bench modified: now tests IRAM and SFR addresses when ...</div>~ /light52/trunk/test/irq_test/src/irq_test.a51<br /> ja_rd Fri, 01 Feb 2013 17:04:52 +0100 https://opencores.org/websvn//websvn/revision?repname=light52&path=%2F&rev=16 Test bench modified: now tests IRAM and SFR addresses when ... https://opencores.org/websvn//websvn/revision?repname=light52&path=%2F&rev=15 <div><strong>Rev 15 - ja_rd</strong> (3 file(s) modified)</div><div>Test bench modified: now tests IRAM and SFR addresses when ...</div>~ /light52/trunk/test/cpu_test/full_test_pkg.vhdl<br />~ /light52/trunk/test/cpu_test/obj_code_pkg.vhdl<br />~ /light52/trunk/test/cpu_test/src/tb51_cpu.a51<br /> ja_rd Mon, 28 Jan 2013 19:24:28 +0100 https://opencores.org/websvn//websvn/revision?repname=light52&path=%2F&rev=15 BUG FIX: <DJNZ dir, rel> didn't work when addressing an ... https://opencores.org/websvn//websvn/revision?repname=light52&path=%2F&rev=14 <div><strong>Rev 14 - ja_rd</strong> (1 file(s) modified)</div><div>BUG FIX: <DJNZ dir, rel> didn't work when addressing an ...</div>~ /light52/trunk/vhdl/light52_cpu.vhdl<br /> ja_rd Mon, 28 Jan 2013 14:09:16 +0100 https://opencores.org/websvn//websvn/revision?repname=light52&path=%2F&rev=14 BUG FIX: <DJNZ dir, rel> was tested only with IRAM ... https://opencores.org/websvn//websvn/revision?repname=light52&path=%2F&rev=13 <div><strong>Rev 13 - ja_rd</strong> (3 file(s) modified)</div><div>BUG FIX: <DJNZ dir, rel> was tested only with IRAM ...</div>~ /light52/trunk/test/cpu_test/full_test_pkg.vhdl<br />~ /light52/trunk/test/cpu_test/obj_code_pkg.vhdl<br />~ /light52/trunk/test/cpu_test/src/tb51_cpu.a51<br /> ja_rd Mon, 28 Jan 2013 13:58:06 +0100 https://opencores.org/websvn//websvn/revision?repname=light52&path=%2F&rev=13 BUG FIX: The build script did not configure XDATA space ... https://opencores.org/websvn//websvn/revision?repname=light52&path=%2F&rev=12 <div><strong>Rev 12 - ja_rd</strong> (1 file(s) modified)</div><div>BUG FIX: The build script did not configure XDATA space ...</div>~ /light52/trunk/test/cpu_test/build.bat<br /> ja_rd Mon, 28 Jan 2013 10:53:19 +0100 https://opencores.org/websvn//websvn/revision?repname=light52&path=%2F&rev=12 Removed old 'demos' directory. These files are now in the ... https://opencores.org/websvn//websvn/revision?repname=light52&path=%2F&rev=11 <div><strong>Rev 11 - ja_rd</strong> (1 file(s) modified)</div><div>Removed old 'demos' directory. These files are now in the ...</div>- /light52/trunk/vhdl/demos<br /> ja_rd Tue, 27 Nov 2012 12:00:28 +0100 https://opencores.org/websvn//websvn/revision?repname=light52&path=%2F&rev=11 Updated 'quickstart' to reflect new organization of demo directory. https://opencores.org/websvn//websvn/revision?repname=light52&path=%2F&rev=10 <div><strong>Rev 10 - ja_rd</strong> (1 file(s) modified)</div><div>Updated 'quickstart' to reflect new organization of demo directory.</div>~ /light52/trunk/doc/quickstart.txt<br /> ja_rd Tue, 27 Nov 2012 11:59:25 +0100 https://opencores.org/websvn//websvn/revision?repname=light52&path=%2F&rev=10 Fixed quartus-2 project file -- replaced absolute output path with ... https://opencores.org/websvn//websvn/revision?repname=light52&path=%2F&rev=9 <div><strong>Rev 9 - ja_rd</strong> (1 file(s) modified)</div><div>Fixed quartus-2 project file -- replaced absolute output path with ...</div>~ /light52/trunk/boards/terasic_de1/syn/light52_de1.qsf<br /> ja_rd Tue, 27 Nov 2012 10:53:33 +0100 https://opencores.org/websvn//websvn/revision?repname=light52&path=%2F&rev=9 Added support to build demos on another board: Avnet's Spartan-3A ... https://opencores.org/websvn//websvn/revision?repname=light52&path=%2F&rev=8 <div><strong>Rev 8 - ja_rd</strong> (8 file(s) modified)</div><div>Added support to build demos on another board: Avnet's Spartan-3A ...</div>+ /light52/trunk/boards/avnet_s3aeval<br />+ /light52/trunk/boards/avnet_s3aeval/Avnet_Sp3A_Eval.ucf<br />+ /light52/trunk/boards/avnet_s3aeval/readme.txt<br />+ /light52/trunk/boards/avnet_s3aeval/syn<br />+ /light52/trunk/boards/avnet_s3aeval/syn/light52_s3aeval<br />+ /light52/trunk/boards/avnet_s3aeval/syn/light52_s3aeval/light52_s3aeval.xise<br />+ /light52/trunk/boards/avnet_s3aeval/vhdl<br />+ /light52/trunk/boards/avnet_s3aeval/vhdl/s3aeval_soc.vhdl<br /> ja_rd Sat, 24 Nov 2012 19:38:02 +0100 https://opencores.org/websvn//websvn/revision?repname=light52&path=%2F&rev=8 Removed obsolete comment from core include file. https://opencores.org/websvn//websvn/revision?repname=light52&path=%2F&rev=7 <div><strong>Rev 7 - ja_rd</strong> (1 file(s) modified)</div><div>Removed obsolete comment from core include file.</div>~ /light52/trunk/test/include/light52.h<br /> ja_rd Sat, 24 Nov 2012 18:48:50 +0100 https://opencores.org/websvn//websvn/revision?repname=light52&path=%2F&rev=7

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