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pci WebSVN RSS feed - pci https://opencores.org/websvn//websvn/listing?repname=pci&path=%2F& Tue, 01 Sep 2026 22:42:37 +0100 FeedCreator 1.7.2 Added old uploaded documents to new repository. https://opencores.org/websvn//websvn/revision?repname=pci&path=%2F&rev=156 <div><strong>Rev 156 - root</strong> (41 file(s) modified)</div><div>Added old uploaded documents to new repository.</div>+ /pci/web_uploads/charact.shtml<br />+ /pci/web_uploads/contacts.shtml<br />+ /pci/web_uploads/current_stat.shtml<br />+ /pci/web_uploads/documentation.shtml<br />+ /pci/web_uploads/download.shtml<br />+ /pci/web_uploads/index.shtml<br />+ /pci/web_uploads/links.shtml<br />- /pci/web_uploads/oc_checkin.sh<br />- /pci/web_uploads/oc_cvs_checkin.sh<br />+ /pci/web_uploads/PCIsim.shtml<br />+ /pci/web_uploads/pcixwin.jpg<br />+ /pci/web_uploads/PCI_HOST_architecture.jpg<br />+ /pci/web_uploads/pci_parity.html<br />+ /pci/web_uploads/pci_prototype.shtml<br />+ /pci/web_uploads/pci_snapshots.shtml<br />+ /pci/web_uploads/PCI_VGA_conn.jpg<br />+ /pci/web_uploads/PCI_VGA_cristal.jpg<br />+ /pci/web_uploads/PCI_VGA_sch.gif<br />+ /pci/web_uploads/PCI_VGA_sch.jpg<br />+ /pci/web_uploads/PCI_VGA_test_brd.gif<br />+ /pci/web_uploads/Pic00022.jpg<br />+ /pci/web_uploads/Pic00026.jpg<br />+ /pci/web_uploads/Pic00027.jpg<br />+ /pci/web_uploads/Pic00028.jpg<br />+ /pci/web_uploads/Pic00037.jpg<br />+ /pci/web_uploads/references.shtml<br />- /pci/web_uploads/svn_checkin.log<br />- /pci/web_uploads/svn_checkin.sh<br />- /pci/web_uploads/temp.sh<br />+ /pci/web_uploads/testbench.shtml<br />+ /pci/web_uploads/test_app.shtml<br />+ /pci/web_uploads/test_board.shtml<br />+ /pci/web_uploads/test_driver.shtml<br />+ /pci/web_uploads/test_snapshots.shtml<br />+ /pci/web_uploads/thumb_pcixwin.jpg<br />+ /pci/web_uploads/thumb_Pic00022.jpg<br />+ /pci/web_uploads/thumb_Pic00026.jpg<br />+ /pci/web_uploads/thumb_Pic00027.jpg<br />+ /pci/web_uploads/thumb_Pic00028.jpg<br />+ /pci/web_uploads/thumb_Pic00037.jpg<br />+ /pci/web_uploads/todo_list.shtml<br /> root Tue, 10 Mar 2009 14:58:35 +0100 https://opencores.org/websvn//websvn/revision?repname=pci&path=%2F&rev=156 Added old uploaded documents to new repository. https://opencores.org/websvn//websvn/revision?repname=pci&path=%2F&rev=155 <div><strong>Rev 155 - root</strong> (5 file(s) modified)</div><div>Added old uploaded documents to new repository.</div>+ /pci/web_uploads/oc_checkin.sh<br />+ /pci/web_uploads/oc_cvs_checkin.sh<br />+ /pci/web_uploads/svn_checkin.log<br />+ /pci/web_uploads/svn_checkin.sh<br />+ /pci/web_uploads/temp.sh<br /> root Tue, 10 Mar 2009 08:26:17 +0100 https://opencores.org/websvn//websvn/revision?repname=pci&path=%2F&rev=155 New directory structure. https://opencores.org/websvn//websvn/revision?repname=pci&path=%2F&rev=154 <div><strong>Rev 154 - root</strong> (8 file(s) modified)</div><div>New directory structure.</div>- /branches<br />+ /pci<br />+ /pci/branches<br />+ /pci/tags<br />+ /pci/trunk<br />+ /pci/web_uploads<br />- /tags<br />- /trunk<br /> root Tue, 10 Mar 2009 08:24:20 +0100 https://opencores.org/websvn//websvn/revision?repname=pci&path=%2F&rev=154 Write burst performance patch applied. Not tested. Everything should be backwards compatible, ... https://opencores.org/websvn//websvn/revision?repname=pci&path=%2F&rev=153 <div><strong>Rev 153 - mihad</strong> (4 file(s) modified)</div><div>Write burst performance patch applied.<br /> Not tested. Everything should be backwards<br /> compatible, ...</div>~ /trunk/rtl/verilog/pci_wbw_fifo_control.v<br />~ /trunk/rtl/verilog/pci_wbw_wbr_fifos.v<br />~ /trunk/rtl/verilog/pci_wb_slave.v<br />~ /trunk/rtl/verilog/pci_wb_slave_unit.v<br /> mihad Tue, 04 Jul 2006 13:16:19 +0100 https://opencores.org/websvn//websvn/revision?repname=pci&path=%2F&rev=153 Some regression tests were failing during completion expired testing. https://opencores.org/websvn//websvn/revision?repname=pci&path=%2F&rev=152 <div><strong>Rev 152 - mihad</strong> (2 file(s) modified)</div><div>Some regression tests were failing during completion expired testing.</div>~ /trunk/bench/verilog/system.v<br />~ /trunk/sim/rtl_sim/bin/ncsim_waves.rc<br /> mihad Mon, 04 Apr 2005 14:42:33 +0100 https://opencores.org/websvn//websvn/revision?repname=pci&path=%2F&rev=152 Top now sends x's to inputs when output is enabled. https://opencores.org/websvn//websvn/revision?repname=pci&path=%2F&rev=151 <div><strong>Rev 151 - mihad</strong> (2 file(s) modified)</div><div>Top now sends x's to inputs when output is enabled.</div>~ /trunk/bench/verilog/system.v<br />~ /trunk/bench/verilog/top.v<br /> mihad Thu, 23 Sep 2004 14:04:26 +0100 https://opencores.org/websvn//websvn/revision?repname=pci&path=%2F&rev=151 The control inputs from PCI are now muxed with control ... https://opencores.org/websvn//websvn/revision?repname=pci&path=%2F&rev=150 <div><strong>Rev 150 - mihad</strong> (1 file(s) modified)</div><div>The control inputs from PCI are now muxed with control ...</div>~ /trunk/rtl/verilog/pci_bridge32.v<br /> mihad Thu, 23 Sep 2004 13:48:53 +0100 https://opencores.org/websvn//websvn/revision?repname=pci&path=%2F&rev=150 Removed some unused signals. https://opencores.org/websvn//websvn/revision?repname=pci&path=%2F&rev=149 <div><strong>Rev 149 - mihad</strong> (1 file(s) modified)</div><div>Removed some unused signals.</div>~ /trunk/rtl/verilog/pci_conf_space.v<br /> mihad Thu, 19 Aug 2004 16:04:53 +0100 https://opencores.org/websvn//websvn/revision?repname=pci&path=%2F&rev=149 Changed minimum pci image size to 256 bytes because of some ... https://opencores.org/websvn//websvn/revision?repname=pci&path=%2F&rev=148 <div><strong>Rev 148 - mihad</strong> (15 file(s) modified)</div><div>Changed minimum pci image size to 256 bytes because<br /> of some ...</div>~ /trunk/bench/verilog/pci_regression_constants.v<br />~ /trunk/bench/verilog/system.v<br />~ /trunk/bench/verilog/wb_slave_behavioral.v<br />~ /trunk/rtl/verilog/pci_bridge32.v<br />~ /trunk/rtl/verilog/pci_conf_space.v<br />~ /trunk/rtl/verilog/pci_pci_tpram.v<br />~ /trunk/rtl/verilog/pci_target32_interface.v<br />~ /trunk/rtl/verilog/pci_target_unit.v<br />~ /trunk/rtl/verilog/pci_user_constants.v<br />~ /trunk/rtl/verilog/pci_wb_tpram.v<br />~ /trunk/sim/rtl_sim/log/ncsim.log<br />~ /trunk/sim/rtl_sim/log/ncvlog.log<br />~ /trunk/sim/rtl_sim/log/pci_tb.log<br />~ /trunk/sim/rtl_sim/run/ncvlog.args<br />~ /trunk/sim/rtl_sim/run/run_pci_sim_regr.scr<br /> mihad Thu, 19 Aug 2004 15:27:52 +0100 https://opencores.org/websvn//websvn/revision?repname=pci&path=%2F&rev=148 Removed unsinthesizable !== comparation. https://opencores.org/websvn//websvn/revision?repname=pci&path=%2F&rev=147 <div><strong>Rev 147 - mihad</strong> (1 file(s) modified)</div><div>Removed unsinthesizable !== comparation.</div>~ /trunk/rtl/verilog/pci_wbs_wbb3_2_wbb2.v<br /> mihad Mon, 16 Aug 2004 09:12:01 +0100 https://opencores.org/websvn//websvn/revision?repname=pci&path=%2F&rev=147 Update. Overwrite of previous wrong version upload. https://opencores.org/websvn//websvn/revision?repname=pci&path=%2F&rev=146 <div><strong>Rev 146 - mihad</strong> (2 file(s) modified)</div><div>Update. Overwrite of previous wrong version upload.</div>~ /trunk/doc/pci_specification.doc<br />~ /trunk/doc/pci_specification.pdf<br /> mihad Fri, 16 Jul 2004 15:36:31 +0100 https://opencores.org/websvn//websvn/revision?repname=pci&path=%2F&rev=146 PDF regenerated. https://opencores.org/websvn//websvn/revision?repname=pci&path=%2F&rev=145 <div><strong>Rev 145 - mihad</strong> (1 file(s) modified)</div><div>PDF regenerated.</div>~ /trunk/doc/pci_specification.pdf<br /> mihad Fri, 16 Jul 2004 14:45:14 +0100 https://opencores.org/websvn//websvn/revision?repname=pci&path=%2F&rev=145 Added PCI Bridge configuration software provided by Friedrich Ralph. https://opencores.org/websvn//websvn/revision?repname=pci&path=%2F&rev=144 <div><strong>Rev 144 - mihad</strong> (4 file(s) modified)</div><div>Added PCI Bridge configuration software provided by<br /> Friedrich Ralph.</div>+ /trunk/sw<br />+ /trunk/sw/configurator<br />+ /trunk/sw/configurator/PCIBridgeConfig.exe<br />+ /trunk/sw/configurator/qtintf.dll<br /> mihad Fri, 09 Jul 2004 07:41:15 +0100 https://opencores.org/websvn//websvn/revision?repname=pci&path=%2F&rev=144 Added SubsystemVendorID, SubsystemID, MAXLatency, MinGnt defines. ... https://opencores.org/websvn//websvn/revision?repname=pci&path=%2F&rev=143 <div><strong>Rev 143 - mihad</strong> (4 file(s) modified)</div><div>Added SubsystemVendorID, SubsystemID, MAXLatency, MinGnt defines.<br /> Enabled value loading from serial ...</div>~ /trunk/bench/verilog/pci_regression_constants.v<br />~ /trunk/bench/verilog/system.v<br />~ /trunk/rtl/verilog/pci_conf_space.v<br />~ /trunk/rtl/verilog/pci_user_constants.v<br /> mihad Wed, 07 Jul 2004 12:45:02 +0100 https://opencores.org/websvn//websvn/revision?repname=pci&path=%2F&rev=143 Single PCI Master write fix. https://opencores.org/websvn//websvn/revision?repname=pci&path=%2F&rev=142 <div><strong>Rev 142 - mihad</strong> (2 file(s) modified)</div><div>Single PCI Master write fix.</div>~ /trunk/bench/verilog/system.v<br />~ /trunk/rtl/verilog/pci_master32_sm_if.v<br /> mihad Fri, 19 Mar 2004 16:36:55 +0100 https://opencores.org/websvn//websvn/revision?repname=pci&path=%2F&rev=142 This commit was manufactured by cvs2svn to create tag 'wb2hpi'. https://opencores.org/websvn//websvn/revision?repname=pci&path=%2F&rev=141 <div><strong>Rev 141 - </strong> (7 file(s) modified)</div><div>This commit was manufactured by cvs2svn to create tag 'wb2hpi'.</div>+ /tags/wb2hpi<br />- /tags/wb2hpi/apps<br />- /tags/wb2hpi/bench<br />- /tags/wb2hpi/doc<br />- /tags/wb2hpi/lib<br />- /tags/wb2hpi/sim<br />- /tags/wb2hpi/syn<br /> Sat, 24 Jan 2004 11:54:20 +0100 https://opencores.org/websvn//websvn/revision?repname=pci&path=%2F&rev=141 Update! SPOCI Implemented! https://opencores.org/websvn//websvn/revision?repname=pci&path=%2F&rev=140 <div><strong>Rev 140 - mihad</strong> (20 file(s) modified)</div><div>Update! SPOCI Implemented!</div>~ /trunk/apps/sw/driver/pci_bridge32_test<br />~ /trunk/bench/verilog/pci_regression_constants.v<br />~ /trunk/bench/verilog/pci_unsupported_commands_master.v<br />~ /trunk/bench/verilog/system.v<br />~ /trunk/bench/verilog/top.v<br />~ /trunk/doc/pci_specification.doc<br />~ /trunk/doc/pci_specification.pdf<br />~ /trunk/rtl/verilog/pci_bridge32.v<br />~ /trunk/rtl/verilog/pci_conf_space.v<br />+ /trunk/rtl/verilog/pci_spoci_ctrl.v<br />~ /trunk/rtl/verilog/pci_user_constants.v<br />~ /trunk/rtl/verilog/pci_wbs_wbb3_2_wbb2.v<br />~ /trunk/rtl/verilog/pci_wb_master.v<br />~ /trunk/rtl/verilog/pci_wb_slave.v<br />~ /trunk/rtl/verilog/pci_wb_slave_unit.v<br />~ /trunk/sim/rtl_sim/bin/rtl_file_list.lst<br />~ /trunk/sim/rtl_sim/bin/sim_file_list.lst<br />~ /trunk/sim/rtl_sim/run/ncvlog.args<br />~ /trunk/sim/rtl_sim/run/run_pci_sim_regr.scr<br />~ /trunk/sim/rtl_sim/run/top_groups.do<br /> mihad Sat, 24 Jan 2004 11:54:19 +0100 https://opencores.org/websvn//websvn/revision?repname=pci&path=%2F&rev=140 Added for SPOCI testing! https://opencores.org/websvn//websvn/revision?repname=pci&path=%2F&rev=139 <div><strong>Rev 139 - mihad</strong> (1 file(s) modified)</div><div>Added for SPOCI testing!</div>+ /trunk/bench/verilog/i2c_slave_model.v<br /> mihad Sat, 24 Jan 2004 11:51:22 +0100 https://opencores.org/websvn//websvn/revision?repname=pci&path=%2F&rev=139 added test_initial_all_conf_values mbist_ctrl_i replaced by mbist_en_i https://opencores.org/websvn//websvn/revision?repname=pci&path=%2F&rev=138 <div><strong>Rev 138 - fr2201</strong> (1 file(s) modified)</div><div>added test_initial_all_conf_values<br /> mbist_ctrl_i replaced by mbist_en_i</div>~ /trunk/bench/verilog/system.v<br /> fr2201 Wed, 07 Jan 2004 17:41:21 +0100 https://opencores.org/websvn//websvn/revision?repname=pci&path=%2F&rev=138 def_wb_imagex_addr_map defined correctly https://opencores.org/websvn//websvn/revision?repname=pci&path=%2F&rev=137 <div><strong>Rev 137 - fr2201</strong> (3 file(s) modified)</div><div>def_wb_imagex_addr_map defined correctly</div>~ /trunk/bench/verilog/system.v<br />~ /trunk/rtl/verilog/pci_conf_space.v<br />~ /trunk/rtl/verilog/pci_user_constants.v<br /> fr2201 Sun, 28 Dec 2003 09:54:48 +0100 https://opencores.org/websvn//websvn/revision?repname=pci&path=%2F&rev=137

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