OpenCores

URL https://opencores.org/ocsvn/srdydrdy_lib/srdydrdy_lib/trunk

Error creating feed file, please check write permissions.
srdydrdy_lib WebSVN RSS feed - srdydrdy_lib https://opencores.org/websvn//websvn/listing?repname=srdydrdy_lib&path=%2F& Wed, 10 Jun 2026 05:52:14 +0100 FeedCreator 1.7.2 Added bridge2 files https://opencores.org/websvn//websvn/revision?repname=srdydrdy_lib&path=%2F&rev=31 <div><strong>Rev 31 - ghutchis</strong> (10 file(s) modified)</div><div>Added bridge2 files</div>+ /srdydrdy_lib/trunk/examples/bridge/rtl/allocator.v<br />~ /srdydrdy_lib/trunk/examples/bridge/rtl/bridge.vh<br />+ /srdydrdy_lib/trunk/examples/bridge/rtl/bridge_ex2.v<br />+ /srdydrdy_lib/trunk/examples/bridge/rtl/control_pipe.v<br />+ /srdydrdy_lib/trunk/examples/bridge/rtl/deallocator.v<br />~ /srdydrdy_lib/trunk/examples/bridge/rtl/fib_lookup.v<br />~ /srdydrdy_lib/trunk/examples/bridge/rtl/fib_lookup_fsm.v<br />+ /srdydrdy_lib/trunk/examples/bridge/rtl/packet_buffer.v<br />~ /srdydrdy_lib/trunk/examples/bridge/rtl/port_macro.v<br />~ /srdydrdy_lib/trunk/examples/bridge/rtl/sd_rx_gigmac.v<br /> ghutchis Fri, 11 May 2012 16:41:33 +0100 https://opencores.org/websvn//websvn/revision?repname=srdydrdy_lib&path=%2F&rev=31 Added llmanager component https://opencores.org/websvn//websvn/revision?repname=srdydrdy_lib&path=%2F&rev=30 <div><strong>Rev 30 - ghutchis</strong> (9 file(s) modified)</div><div>Added llmanager component</div>~ /srdydrdy_lib/trunk/examples/bridge/env/gmii_driver.v<br />~ /srdydrdy_lib/trunk/examples/bridge/env/run<br />~ /srdydrdy_lib/trunk/rtl/verilog/closure/sd_output.v<br />~ /srdydrdy_lib/trunk/rtl/verilog/forks/sd_ajoin2.v<br />~ /srdydrdy_lib/trunk/rtl/verilog/forks/sd_rrmux.v<br />~ /srdydrdy_lib/trunk/rtl/verilog/memory/behave1p_mem.v<br />+ /srdydrdy_lib/trunk/rtl/verilog/utility/llmanager.v<br />+ /srdydrdy_lib/trunk/rtl/verilog/utility/llmanager_refcount.v<br />~ /srdydrdy_lib/trunk/rtl/verilog/utility/sd_scoreboard.v<br /> ghutchis Fri, 11 May 2012 16:40:44 +0100 https://opencores.org/websvn//websvn/revision?repname=srdydrdy_lib&path=%2F&rev=30 Updated arbitration https://opencores.org/websvn//websvn/revision?repname=srdydrdy_lib&path=%2F&rev=29 <div><strong>Rev 29 - ghutchis</strong> (1 file(s) modified)</div><div>Updated arbitration</div>~ /srdydrdy_lib/trunk/rtl/verilog/forks/sd_rrmux.v<br /> ghutchis Fri, 01 Jul 2011 17:13:47 +0100 https://opencores.org/websvn//websvn/revision?repname=srdydrdy_lib&path=%2F&rev=29 Added ports & fixed signal propagation https://opencores.org/websvn//websvn/revision?repname=srdydrdy_lib&path=%2F&rev=28 <div><strong>Rev 28 - ghutchis</strong> (1 file(s) modified)</div><div>Added ports & fixed signal propagation</div>~ /srdydrdy_lib/trunk/rtl/verilog/utility/sd_bpdrop.v<br /> ghutchis Fri, 18 Mar 2011 17:41:42 +0100 https://opencores.org/websvn//websvn/revision?repname=srdydrdy_lib&path=%2F&rev=28 Added environment to bpdrop https://opencores.org/websvn//websvn/revision?repname=srdydrdy_lib&path=%2F&rev=27 <div><strong>Rev 27 - ghutchis</strong> (3 file(s) modified)</div><div>Added environment to bpdrop</div>+ /srdydrdy_lib/trunk/env/verilog/bpdrop<br />+ /srdydrdy_lib/trunk/env/verilog/bpdrop/bench_bpdrop.v<br />+ /srdydrdy_lib/trunk/env/verilog/bpdrop/runsh<br /> ghutchis Fri, 18 Mar 2011 00:09:07 +0100 https://opencores.org/websvn//websvn/revision?repname=srdydrdy_lib&path=%2F&rev=27 Added backpressure drop module https://opencores.org/websvn//websvn/revision?repname=srdydrdy_lib&path=%2F&rev=26 <div><strong>Rev 26 - ghutchis</strong> (1 file(s) modified)</div><div>Added backpressure drop module</div>+ /srdydrdy_lib/trunk/rtl/verilog/utility/sd_bpdrop.v<br /> ghutchis Fri, 18 Mar 2011 00:08:42 +0100 https://opencores.org/websvn//websvn/revision?repname=srdydrdy_lib&path=%2F&rev=26 Added sd_sync component for cross-clock synchronization https://opencores.org/websvn//websvn/revision?repname=srdydrdy_lib&path=%2F&rev=25 <div><strong>Rev 25 - ghutchis</strong> (4 file(s) modified)</div><div>Added sd_sync component for cross-clock synchronization</div>+ /srdydrdy_lib/trunk/env/verilog/sync<br />+ /srdydrdy_lib/trunk/env/verilog/sync/sync.vf<br />+ /srdydrdy_lib/trunk/env/verilog/sync/sync_bench.v<br />+ /srdydrdy_lib/trunk/rtl/verilog/utility/sd_sync.v<br /> ghutchis Thu, 02 Dec 2010 02:10:34 +0100 https://opencores.org/websvn//websvn/revision?repname=srdydrdy_lib&path=%2F&rev=25 Added CRC32 checker to environment & RTL https://opencores.org/websvn//websvn/revision?repname=srdydrdy_lib&path=%2F&rev=24 <div><strong>Rev 24 - ghutchis</strong> (8 file(s) modified)</div><div>Added CRC32 checker to environment & RTL</div>~ /srdydrdy_lib/trunk/examples/bridge/env/bridge.vf<br />~ /srdydrdy_lib/trunk/examples/bridge/env/gmii_driver.v<br />+ /srdydrdy_lib/trunk/examples/bridge/rtl/mac_crc32.v<br />~ /srdydrdy_lib/trunk/examples/bridge/rtl/sd_rx_gigmac.v<br />~ /srdydrdy_lib/trunk/examples/bridge/rtl/sd_tx_gigmac.v<br />~ /srdydrdy_lib/trunk/rtl/verilog/forks/sd_rrmux.v<br />~ /srdydrdy_lib/trunk/rtl/verilog/utility/sd_scoreboard.v<br />~ /srdydrdy_lib/trunk/rtl/verilog/utility/sd_scoreboard_fsm.v<br /> ghutchis Sat, 07 Aug 2010 01:39:02 +0100 https://opencores.org/websvn//websvn/revision?repname=srdydrdy_lib&path=%2F&rev=24 Imported Ethernet Tri-Mode MAC for use in examples https://opencores.org/websvn//websvn/revision?repname=srdydrdy_lib&path=%2F&rev=23 <div><strong>Rev 23 - ghutchis</strong> (37 file(s) modified)</div><div>Imported Ethernet Tri-Mode MAC for use in examples</div>+ /srdydrdy_lib/trunk/external<br />+ /srdydrdy_lib/trunk/external/ethernet_tri_mode<br />+ /srdydrdy_lib/trunk/external/ethernet_tri_mode/Clk_ctrl.v<br />+ /srdydrdy_lib/trunk/external/ethernet_tri_mode/eth_miim.v<br />+ /srdydrdy_lib/trunk/external/ethernet_tri_mode/header.v<br />+ /srdydrdy_lib/trunk/external/ethernet_tri_mode/MAC_rx<br />+ /srdydrdy_lib/trunk/external/ethernet_tri_mode/MAC_rx.v<br />+ /srdydrdy_lib/trunk/external/ethernet_tri_mode/MAC_rx/Broadcast_filter.v<br />+ /srdydrdy_lib/trunk/external/ethernet_tri_mode/MAC_rx/CRC_chk.v<br />+ /srdydrdy_lib/trunk/external/ethernet_tri_mode/MAC_rx/MAC_rx_add_chk.v<br />+ /srdydrdy_lib/trunk/external/ethernet_tri_mode/MAC_rx/MAC_rx_ctrl.v<br />+ /srdydrdy_lib/trunk/external/ethernet_tri_mode/MAC_rx/MAC_rx_FF.v<br />+ /srdydrdy_lib/trunk/external/ethernet_tri_mode/MAC_top.v<br />+ /srdydrdy_lib/trunk/external/ethernet_tri_mode/MAC_tx<br />+ /srdydrdy_lib/trunk/external/ethernet_tri_mode/MAC_tx.v<br />+ /srdydrdy_lib/trunk/external/ethernet_tri_mode/MAC_tx/CRC_gen.v<br />+ /srdydrdy_lib/trunk/external/ethernet_tri_mode/MAC_tx/flow_ctrl.v<br />+ /srdydrdy_lib/trunk/external/ethernet_tri_mode/MAC_tx/MAC_tx_addr_add.v<br />+ /srdydrdy_lib/trunk/external/ethernet_tri_mode/MAC_tx/MAC_tx_Ctrl.v<br />+ /srdydrdy_lib/trunk/external/ethernet_tri_mode/MAC_tx/MAC_tx_FF.v<br />+ /srdydrdy_lib/trunk/external/ethernet_tri_mode/MAC_tx/Ramdon_gen.v<br />+ /srdydrdy_lib/trunk/external/ethernet_tri_mode/miim<br />+ /srdydrdy_lib/trunk/external/ethernet_tri_mode/miim/eth_clockgen.v<br />+ /srdydrdy_lib/trunk/external/ethernet_tri_mode/miim/eth_outputcontrol.v<br />+ /srdydrdy_lib/trunk/external/ethernet_tri_mode/miim/eth_shiftreg.v<br />+ /srdydrdy_lib/trunk/external/ethernet_tri_mode/miim/timescale.v<br />+ /srdydrdy_lib/trunk/external/ethernet_tri_mode/Phy_int.v<br />+ /srdydrdy_lib/trunk/external/ethernet_tri_mode/reg_int.v<br />+ /srdydrdy_lib/trunk/external/ethernet_tri_mode/RMON<br />+ /srdydrdy_lib/trunk/external/ethernet_tri_mode/RMON.v<br />+ /srdydrdy_lib/trunk/external/ethernet_tri_mode/RMON/RMON_addr_gen.v<br />+ /srdydrdy_lib/trunk/external/ethernet_tri_mode/RMON/RMON_ctrl.v<br />+ /srdydrdy_lib/trunk/external/ethernet_tri_mode/RMON/RMON_dpram.v<br />+ /srdydrdy_lib/trunk/external/ethernet_tri_mode/TECH<br />+ /srdydrdy_lib/trunk/external/ethernet_tri_mode/TECH/CLK_DIV2.v<br />+ /srdydrdy_lib/trunk/external/ethernet_tri_mode/TECH/CLK_SWITCH.v<br />+ /srdydrdy_lib/trunk/external/ethernet_tri_mode/TECH/duram.v<br /> ghutchis Thu, 18 Feb 2010 02:45:29 +0100 https://opencores.org/websvn//websvn/revision?repname=srdydrdy_lib&path=%2F&rev=23 Created separate module-level environments for fifo_b and scoreboard. Added some ... https://opencores.org/websvn//websvn/revision?repname=srdydrdy_lib&path=%2F&rev=22 <div><strong>Rev 22 - ghutchis</strong> (15 file(s) modified)</div><div>Created separate module-level environments for fifo_b<br /> and scoreboard. Added some ...</div>- /srdydrdy_lib/trunk/env/verilog/bench_fifo_b.v<br />- /srdydrdy_lib/trunk/env/verilog/bench_fifo_b.vf<br />+ /srdydrdy_lib/trunk/env/verilog/common<br />+ /srdydrdy_lib/trunk/env/verilog/common/sd_seq_check.v<br />+ /srdydrdy_lib/trunk/env/verilog/common/sd_seq_gen.v<br />+ /srdydrdy_lib/trunk/env/verilog/fifo_b<br />+ /srdydrdy_lib/trunk/env/verilog/fifo_b/bench_fifo_b.v<br />+ /srdydrdy_lib/trunk/env/verilog/fifo_b/bench_fifo_b.vf<br />- /srdydrdy_lib/trunk/env/verilog/sd_seq_check.v<br />- /srdydrdy_lib/trunk/env/verilog/sd_seq_gen.v<br />+ /srdydrdy_lib/trunk/examples/bridge/doc<br />+ /srdydrdy_lib/trunk/examples/bridge/doc/bridge_example.txt<br />+ /srdydrdy_lib/trunk/examples/bridge/doc/intro_ethernet.pdf<br />~ /srdydrdy_lib/trunk/examples/bridge/env/run<br />~ /srdydrdy_lib/trunk/rtl/verilog/buffers/sd_fifo_tail_b.v<br /> ghutchis Fri, 22 Jan 2010 22:39:04 +0100 https://opencores.org/websvn//websvn/revision?repname=srdydrdy_lib&path=%2F&rev=22 Changed rrslow to rrmux, updated descriptions, changed bridge mux to fast ... https://opencores.org/websvn//websvn/revision?repname=srdydrdy_lib&path=%2F&rev=21 <div><strong>Rev 21 - ghutchis</strong> (7 file(s) modified)</div><div>Changed rrslow to rrmux, updated descriptions, changed<br /> bridge mux to fast ...</div>~ /srdydrdy_lib/trunk/doc/component_descriptions.txt<br />~ /srdydrdy_lib/trunk/examples/bridge/env/tests/overflow1.v<br />~ /srdydrdy_lib/trunk/examples/bridge/env/tests/sample_test.v<br />~ /srdydrdy_lib/trunk/examples/bridge/rtl/bridge_ex1.v<br />~ /srdydrdy_lib/trunk/examples/bridge/rtl/ring_arb.v<br />+ /srdydrdy_lib/trunk/rtl/verilog/forks/sd_rrmux.v<br />- /srdydrdy_lib/trunk/rtl/verilog/forks/sd_rrslow.v<br /> ghutchis Thu, 21 Jan 2010 20:06:16 +0100 https://opencores.org/websvn//websvn/revision?repname=srdydrdy_lib&path=%2F&rev=21 Added fast arb mode https://opencores.org/websvn//websvn/revision?repname=srdydrdy_lib&path=%2F&rev=20 <div><strong>Rev 20 - ghutchis</strong> (1 file(s) modified)</div><div>Added fast arb mode</div>~ /srdydrdy_lib/trunk/rtl/verilog/forks/sd_rrslow.v<br /> ghutchis Thu, 21 Jan 2010 18:30:10 +0100 https://opencores.org/websvn//websvn/revision?repname=srdydrdy_lib&path=%2F&rev=20 Fixed several minor bugs in scoreboard, adjusted usage width in ... https://opencores.org/websvn//websvn/revision?repname=srdydrdy_lib&path=%2F&rev=19 <div><strong>Rev 19 - ghutchis</strong> (8 file(s) modified)</div><div>Fixed several minor bugs in scoreboard, adjusted usage width in ...</div>~ /srdydrdy_lib/trunk/doc/component_descriptions.txt<br />~ /srdydrdy_lib/trunk/env/verilog/scoreboard/sb_bench.v<br />~ /srdydrdy_lib/trunk/env/verilog/scoreboard/sb_monitor.v<br />~ /srdydrdy_lib/trunk/examples/bridge/env/run<br />~ /srdydrdy_lib/trunk/rtl/verilog/buffers/sd_fifo_b.v<br />~ /srdydrdy_lib/trunk/rtl/verilog/buffers/sd_fifo_tail_b.v<br />~ /srdydrdy_lib/trunk/rtl/verilog/memory/behave1p_mem.v<br />~ /srdydrdy_lib/trunk/rtl/verilog/utility/sd_scoreboard_fsm.v<br /> ghutchis Thu, 21 Jan 2010 06:33:30 +0100 https://opencores.org/websvn//websvn/revision?repname=srdydrdy_lib&path=%2F&rev=19 Added scoreboard and scoreboard testbench https://opencores.org/websvn//websvn/revision?repname=srdydrdy_lib&path=%2F&rev=18 <div><strong>Rev 18 - ghutchis</strong> (12 file(s) modified)</div><div>Added scoreboard and scoreboard testbench</div>+ /srdydrdy_lib/trunk/env/verilog/scoreboard<br />+ /srdydrdy_lib/trunk/env/verilog/scoreboard/run<br />+ /srdydrdy_lib/trunk/env/verilog/scoreboard/sb_bench.v<br />+ /srdydrdy_lib/trunk/env/verilog/scoreboard/sb_driver.v<br />+ /srdydrdy_lib/trunk/env/verilog/scoreboard/sb_monitor.v<br />+ /srdydrdy_lib/trunk/env/verilog/scoreboard/scoreboard.vf<br />+ /srdydrdy_lib/trunk/rtl/verilog/forks/sd_ajoin2.v<br />~ /srdydrdy_lib/trunk/rtl/verilog/forks/sd_rrslow.v<br />+ /srdydrdy_lib/trunk/rtl/verilog/utility<br />+ /srdydrdy_lib/trunk/rtl/verilog/utility/sd_ring_node.v<br />+ /srdydrdy_lib/trunk/rtl/verilog/utility/sd_scoreboard.v<br />+ /srdydrdy_lib/trunk/rtl/verilog/utility/sd_scoreboard_fsm.v<br /> ghutchis Thu, 21 Jan 2010 02:32:32 +0100 https://opencores.org/websvn//websvn/revision?repname=srdydrdy_lib&path=%2F&rev=18 Added component descriptions https://opencores.org/websvn//websvn/revision?repname=srdydrdy_lib&path=%2F&rev=17 <div><strong>Rev 17 - ghutchis</strong> (2 file(s) modified)</div><div>Added component descriptions</div>+ /srdydrdy_lib/trunk/doc<br />+ /srdydrdy_lib/trunk/doc/component_descriptions.txt<br /> ghutchis Wed, 20 Jan 2010 17:26:50 +0100 https://opencores.org/websvn//websvn/revision?repname=srdydrdy_lib&path=%2F&rev=17 Changed fifo head/tail to have separate usage counters for producer ... https://opencores.org/websvn//websvn/revision?repname=srdydrdy_lib&path=%2F&rev=16 <div><strong>Rev 16 - ghutchis</strong> (7 file(s) modified)</div><div>Changed fifo head/tail to have separate usage counters for producer ...</div>~ /srdydrdy_lib/trunk/examples/bridge/env/env_top.v<br />~ /srdydrdy_lib/trunk/examples/bridge/env/run<br />~ /srdydrdy_lib/trunk/examples/bridge/rtl/port_macro.v<br />~ /srdydrdy_lib/trunk/examples/bridge/rtl/port_ring_tap_fsm.v<br />~ /srdydrdy_lib/trunk/rtl/verilog/buffers/sd_fifo_b.v<br />~ /srdydrdy_lib/trunk/rtl/verilog/buffers/sd_fifo_head_b.v<br />~ /srdydrdy_lib/trunk/rtl/verilog/buffers/sd_fifo_tail_b.v<br /> ghutchis Wed, 20 Jan 2010 05:32:13 +0100 https://opencores.org/websvn//websvn/revision?repname=srdydrdy_lib&path=%2F&rev=16 Fixed FIB lookup multicast -- multicast packets were being repeatedly sent ... https://opencores.org/websvn//websvn/revision?repname=srdydrdy_lib&path=%2F&rev=15 <div><strong>Rev 15 - ghutchis</strong> (1 file(s) modified)</div><div>Fixed FIB lookup multicast -- multicast packets were being<br /> repeatedly sent ...</div>~ /srdydrdy_lib/trunk/examples/bridge/rtl/fib_lookup_fsm.v<br /> ghutchis Wed, 20 Jan 2010 01:24:42 +0100 https://opencores.org/websvn//websvn/revision?repname=srdydrdy_lib&path=%2F&rev=15 - Modified large FIFO to remove "full" signal and store ... https://opencores.org/websvn//websvn/revision?repname=srdydrdy_lib&path=%2F&rev=14 <div><strong>Rev 14 - ghutchis</strong> (9 file(s) modified)</div><div>- Modified large FIFO to remove "full" signal and store ...</div>~ /srdydrdy_lib/trunk/env/verilog/bench_fifo_b.v<br />~ /srdydrdy_lib/trunk/env/verilog/bench_fifo_s.v<br />~ /srdydrdy_lib/trunk/env/verilog/bench_fifo_s.vf<br />~ /srdydrdy_lib/trunk/env/verilog/sd_seq_gen.v<br />~ /srdydrdy_lib/trunk/examples/bridge/env/run<br />~ /srdydrdy_lib/trunk/rtl/verilog/buffers/sd_fifo_head_b.v<br />~ /srdydrdy_lib/trunk/rtl/verilog/buffers/sd_fifo_s.v<br />~ /srdydrdy_lib/trunk/rtl/verilog/buffers/sd_fifo_tail_b.v<br />~ /srdydrdy_lib/trunk/rtl/verilog/forks/sd_mirror.v<br /> ghutchis Mon, 18 Jan 2010 07:28:13 +0100 https://opencores.org/websvn//websvn/revision?repname=srdydrdy_lib&path=%2F&rev=14 Fixed FIFO Full condition for large fifo, added separate tests to ... https://opencores.org/websvn//websvn/revision?repname=srdydrdy_lib&path=%2F&rev=13 <div><strong>Rev 13 - ghutchis</strong> (13 file(s) modified)</div><div>Fixed FIFO Full condition for large fifo, added separate<br /> tests to ...</div>~ /srdydrdy_lib/trunk/examples/bridge/env/env_top.v<br />~ /srdydrdy_lib/trunk/examples/bridge/env/run<br />+ /srdydrdy_lib/trunk/examples/bridge/env/tests<br />+ /srdydrdy_lib/trunk/examples/bridge/env/tests/overflow1.v<br />+ /srdydrdy_lib/trunk/examples/bridge/env/tests/sample_test.v<br />+ /srdydrdy_lib/trunk/examples/bridge/env/test_tasks.v<br />~ /srdydrdy_lib/trunk/examples/bridge/rtl/bridge.vh<br />~ /srdydrdy_lib/trunk/examples/bridge/rtl/egr_oflow.v<br />~ /srdydrdy_lib/trunk/examples/bridge/rtl/fib_lookup_fsm.v<br />~ /srdydrdy_lib/trunk/examples/bridge/rtl/port_ring_tap_fsm.v<br />~ /srdydrdy_lib/trunk/rtl/verilog/buffers/sd_fifo_b.v<br />~ /srdydrdy_lib/trunk/rtl/verilog/buffers/sd_fifo_head_b.v<br />~ /srdydrdy_lib/trunk/rtl/verilog/buffers/sd_fifo_tail_b.v<br /> ghutchis Thu, 14 Jan 2010 20:58:48 +0100 https://opencores.org/websvn//websvn/revision?repname=srdydrdy_lib&path=%2F&rev=13 Added absolute priority arbitration to ring to avoid having two ring ... https://opencores.org/websvn//websvn/revision?repname=srdydrdy_lib&path=%2F&rev=12 <div><strong>Rev 12 - ghutchis</strong> (7 file(s) modified)</div><div>Added absolute priority arbitration to ring to avoid<br /> having two ring ...</div>~ /srdydrdy_lib/trunk/examples/bridge/env/bridge.vf<br />~ /srdydrdy_lib/trunk/examples/bridge/env/env_top.v<br />~ /srdydrdy_lib/trunk/examples/bridge/rtl/bridge_ex1.v<br />~ /srdydrdy_lib/trunk/examples/bridge/rtl/port_macro.v<br />~ /srdydrdy_lib/trunk/examples/bridge/rtl/port_ring_tap.v<br />~ /srdydrdy_lib/trunk/examples/bridge/rtl/port_ring_tap_fsm.v<br />+ /srdydrdy_lib/trunk/examples/bridge/rtl/ring_arb.v<br /> ghutchis Wed, 13 Jan 2010 21:26:23 +0100 https://opencores.org/websvn//websvn/revision?repname=srdydrdy_lib&path=%2F&rev=12

Browse

Tools