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vga_lcd WebSVN RSS feed - vga_lcd https://opencores.org/websvn//websvn/listing?repname=vga_lcd&path=%2F& Mon, 15 Jun 2026 15:27:31 +0100 FeedCreator 1.7.2 Added old uploaded documents to new repository. https://opencores.org/websvn//websvn/revision?repname=vga_lcd&path=%2F&rev=64 <div><strong>Rev 64 - root</strong> (9 file(s) modified)</div><div>Added old uploaded documents to new repository.</div>+ /vga_lcd/web_uploads/block_diagram.gif<br />+ /vga_lcd/web_uploads/block_diagram.jpg<br />+ /vga_lcd/web_uploads/index.shtml<br />- /vga_lcd/web_uploads/oc_checkin.sh<br />- /vga_lcd/web_uploads/oc_cvs_checkin.sh<br />- /vga_lcd/web_uploads/svn_checkin.log<br />- /vga_lcd/web_uploads/svn_checkin.sh<br />- /vga_lcd/web_uploads/temp.sh<br />+ /vga_lcd/web_uploads/vga_core.pdf<br /> root Tue, 10 Mar 2009 15:59:25 +0100 https://opencores.org/websvn//websvn/revision?repname=vga_lcd&path=%2F&rev=64 Added old uploaded documents to new repository. https://opencores.org/websvn//websvn/revision?repname=vga_lcd&path=%2F&rev=63 <div><strong>Rev 63 - root</strong> (5 file(s) modified)</div><div>Added old uploaded documents to new repository.</div>+ /vga_lcd/web_uploads/oc_checkin.sh<br />+ /vga_lcd/web_uploads/oc_cvs_checkin.sh<br />+ /vga_lcd/web_uploads/svn_checkin.log<br />+ /vga_lcd/web_uploads/svn_checkin.sh<br />+ /vga_lcd/web_uploads/temp.sh<br /> root Tue, 10 Mar 2009 10:22:18 +0100 https://opencores.org/websvn//websvn/revision?repname=vga_lcd&path=%2F&rev=63 New directory structure. https://opencores.org/websvn//websvn/revision?repname=vga_lcd&path=%2F&rev=62 <div><strong>Rev 62 - root</strong> (8 file(s) modified)</div><div>New directory structure.</div>- /branches<br />- /tags<br />- /trunk<br />+ /vga_lcd<br />+ /vga_lcd/branches<br />+ /vga_lcd/tags<br />+ /vga_lcd/trunk<br />+ /vga_lcd/web_uploads<br /> root Tue, 10 Mar 2009 10:21:49 +0100 https://opencores.org/websvn//websvn/revision?repname=vga_lcd&path=%2F&rev=62 This commit was manufactured by cvs2svn to create tag 'rel_19'. https://opencores.org/websvn//websvn/revision?repname=vga_lcd&path=%2F&rev=61 <div><strong>Rev 61 - </strong> (2 file(s) modified)</div><div>This commit was manufactured by cvs2svn to create tag 'rel_19'.</div>+ /tags/rel_19<br />- /tags/rel_19/rtl<br /> Tue, 23 Sep 2003 13:09:27 +0100 https://opencores.org/websvn//websvn/revision?repname=vga_lcd&path=%2F&rev=61 all WB outputs are registered, but just when we dont ... https://opencores.org/websvn//websvn/revision?repname=vga_lcd&path=%2F&rev=60 <div><strong>Rev 60 - markom</strong> (5 file(s) modified)</div><div>all WB outputs are registered, but just when we dont ...</div>~ /trunk/bench/verilog/sync_check.v<br />~ /trunk/bench/verilog/tests.v<br />~ /trunk/bench/verilog/test_bench_top.v<br />~ /trunk/bench/verilog/wb_mast_model.v<br />~ /trunk/sim/rtl_sim/bin/Makefile<br /> markom Tue, 23 Sep 2003 13:09:26 +0100 https://opencores.org/websvn//websvn/revision?repname=vga_lcd&path=%2F&rev=60 Removed ctrl register's clut and vide bank switch from the ... https://opencores.org/websvn//websvn/revision?repname=vga_lcd&path=%2F&rev=59 <div><strong>Rev 59 - rherveille</strong> (1 file(s) modified)</div><div>Removed ctrl register's clut and vide bank switch from the ...</div>~ /trunk/bench/verilog/tests.v<br /> rherveille Fri, 22 Aug 2003 07:17:21 +0100 https://opencores.org/websvn//websvn/revision?repname=vga_lcd&path=%2F&rev=59 Enabled Fifo Underrun test https://opencores.org/websvn//websvn/revision?repname=vga_lcd&path=%2F&rev=58 <div><strong>Rev 58 - rherveille</strong> (1 file(s) modified)</div><div>Enabled Fifo Underrun test</div>~ /trunk/bench/verilog/test_bench_top.v<br /> rherveille Fri, 22 Aug 2003 07:12:31 +0100 https://opencores.org/websvn//websvn/revision?repname=vga_lcd&path=%2F&rev=58 1) Rewrote vga_fifo_dc. It now uses gray codes and a ... https://opencores.org/websvn//websvn/revision?repname=vga_lcd&path=%2F&rev=57 <div><strong>Rev 57 - rherveille</strong> (6 file(s) modified)</div><div>1) Rewrote vga_fifo_dc. It now uses gray codes and a ...</div>~ /trunk/rtl/verilog/vga_defines.v<br />~ /trunk/rtl/verilog/vga_enh_top.v<br />~ /trunk/rtl/verilog/vga_fifo.v<br />~ /trunk/rtl/verilog/vga_fifo_dc.v<br />~ /trunk/rtl/verilog/vga_pgen.v<br />~ /trunk/rtl/verilog/vga_wb_master.v<br /> rherveille Fri, 01 Aug 2003 11:46:38 +0100 https://opencores.org/websvn//websvn/revision?repname=vga_lcd&path=%2F&rev=57 Removed 'or negedge arst' from sluint/luint sensitivity list https://opencores.org/websvn//websvn/revision?repname=vga_lcd&path=%2F&rev=56 <div><strong>Rev 56 - rherveille</strong> (1 file(s) modified)</div><div>Removed 'or negedge arst' from sluint/luint sensitivity list</div>~ /trunk/rtl/verilog/vga_enh_top.v<br /> rherveille Thu, 03 Jul 2003 15:09:06 +0100 https://opencores.org/websvn//websvn/revision?repname=vga_lcd&path=%2F&rev=56 Initial release. https://opencores.org/websvn//websvn/revision?repname=vga_lcd&path=%2F&rev=55 <div><strong>Rev 55 - rherveille</strong> (1 file(s) modified)</div><div>Initial release.</div>+ /trunk/rtl/verilog/vga_clkgen.v<br /> rherveille Wed, 07 May 2003 14:43:01 +0100 https://opencores.org/websvn//websvn/revision?repname=vga_lcd&path=%2F&rev=55 Added DVI tests https://opencores.org/websvn//websvn/revision?repname=vga_lcd&path=%2F&rev=54 <div><strong>Rev 54 - rherveille</strong> (2 file(s) modified)</div><div>Added DVI tests</div>~ /trunk/bench/verilog/tests.v<br />~ /trunk/bench/verilog/test_bench_top.v<br /> rherveille Wed, 07 May 2003 14:39:19 +0100 https://opencores.org/websvn//websvn/revision?repname=vga_lcd&path=%2F&rev=54 Fixed some Wishbone RevB.3 related bugs. Changed layout of the core. ... https://opencores.org/websvn//websvn/revision?repname=vga_lcd&path=%2F&rev=53 <div><strong>Rev 53 - rherveille</strong> (13 file(s) modified)</div><div>Fixed some Wishbone RevB.3 related bugs.<br /> Changed layout of the core. ...</div>~ /trunk/rtl/verilog/vga_colproc.v<br />~ /trunk/rtl/verilog/vga_csm_pb.v<br />~ /trunk/rtl/verilog/vga_curproc.v<br />~ /trunk/rtl/verilog/vga_cur_cregs.v<br />~ /trunk/rtl/verilog/vga_defines.v<br />~ /trunk/rtl/verilog/vga_enh_top.v<br />~ /trunk/rtl/verilog/vga_fifo.v<br />~ /trunk/rtl/verilog/vga_fifo_dc.v<br />~ /trunk/rtl/verilog/vga_pgen.v<br />~ /trunk/rtl/verilog/vga_tgen.v<br />~ /trunk/rtl/verilog/vga_vtim.v<br />~ /trunk/rtl/verilog/vga_wb_master.v<br />~ /trunk/rtl/verilog/vga_wb_slave.v<br /> rherveille Wed, 07 May 2003 09:48:54 +0100 https://opencores.org/websvn//websvn/revision?repname=vga_lcd&path=%2F&rev=53 Numerous updates and added checks https://opencores.org/websvn//websvn/revision?repname=vga_lcd&path=%2F&rev=52 <div><strong>Rev 52 - rherveille</strong> (5 file(s) modified)</div><div>Numerous updates and added checks</div>~ /trunk/bench/verilog/sync_check.v<br />~ /trunk/bench/verilog/tests.v<br />~ /trunk/bench/verilog/test_bench_top.v<br />~ /trunk/bench/verilog/wb_b3_check.v<br />~ /trunk/bench/verilog/wb_slv_model.v<br /> rherveille Wed, 07 May 2003 09:45:28 +0100 https://opencores.org/websvn//websvn/revision?repname=vga_lcd&path=%2F&rev=52 Forgot to change document revision number https://opencores.org/websvn//websvn/revision?repname=vga_lcd&path=%2F&rev=51 <div><strong>Rev 51 - rherveille</strong> (1 file(s) modified)</div><div>Forgot to change document revision number</div>~ /trunk/doc/src/vga_core_enh.doc<br /> rherveille Thu, 20 Mar 2003 15:09:51 +0100 https://opencores.org/websvn//websvn/revision?repname=vga_lcd&path=%2F&rev=51 Forgot to change document revision https://opencores.org/websvn//websvn/revision?repname=vga_lcd&path=%2F&rev=50 <div><strong>Rev 50 - rherveille</strong> (1 file(s) modified)</div><div>Forgot to change document revision</div>~ /trunk/doc/vga_core.pdf<br /> rherveille Thu, 20 Mar 2003 15:07:05 +0100 https://opencores.org/websvn//websvn/revision?repname=vga_lcd&path=%2F&rev=50 Added WISHBONE revB.3 signals https://opencores.org/websvn//websvn/revision?repname=vga_lcd&path=%2F&rev=49 <div><strong>Rev 49 - rherveille</strong> (1 file(s) modified)</div><div>Added WISHBONE revB.3 signals</div>~ /trunk/doc/src/vga_core_enh.doc<br /> rherveille Thu, 20 Mar 2003 14:09:40 +0100 https://opencores.org/websvn//websvn/revision?repname=vga_lcd&path=%2F&rev=49 WISHBONE revB.3 signals added https://opencores.org/websvn//websvn/revision?repname=vga_lcd&path=%2F&rev=48 <div><strong>Rev 48 - rherveille</strong> (1 file(s) modified)</div><div>WISHBONE revB.3 signals added</div>~ /trunk/doc/vga_core.pdf<br /> rherveille Thu, 20 Mar 2003 14:04:21 +0100 https://opencores.org/websvn//websvn/revision?repname=vga_lcd&path=%2F&rev=48 Added wb_b3_check Removed ud_cnt, ro_cnt https://opencores.org/websvn//websvn/revision?repname=vga_lcd&path=%2F&rev=47 <div><strong>Rev 47 - rherveille</strong> (1 file(s) modified)</div><div>Added wb_b3_check<br /> Removed ud_cnt, ro_cnt</div>~ /trunk/sim/rtl_sim/bin/Makefile<br /> rherveille Wed, 19 Mar 2003 17:27:37 +0100 https://opencores.org/websvn//websvn/revision?repname=vga_lcd&path=%2F&rev=47 Added WISHBONE revB.3 sanity checks https://opencores.org/websvn//websvn/revision?repname=vga_lcd&path=%2F&rev=46 <div><strong>Rev 46 - rherveille</strong> (2 file(s) modified)</div><div>Added WISHBONE revB.3 sanity checks</div>~ /trunk/bench/verilog/test_bench_top.v<br />+ /trunk/bench/verilog/wb_b3_check.v<br /> rherveille Wed, 19 Mar 2003 17:22:19 +0100 https://opencores.org/websvn//websvn/revision?repname=vga_lcd&path=%2F&rev=46 Changed timing generator; made it smaller and easier. https://opencores.org/websvn//websvn/revision?repname=vga_lcd&path=%2F&rev=45 <div><strong>Rev 45 - rherveille</strong> (4 file(s) modified)</div><div>Changed timing generator; made it smaller and easier.</div>- /trunk/rtl/verilog/ro_cnt.v<br />- /trunk/rtl/verilog/ud_cnt.v<br />~ /trunk/rtl/verilog/vga_vtim.v<br />~ /trunk/rtl/verilog/vga_wb_master.v<br /> rherveille Wed, 19 Mar 2003 12:50:45 +0100 https://opencores.org/websvn//websvn/revision?repname=vga_lcd&path=%2F&rev=45

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