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xmatchpro WebSVN RSS feed - xmatchpro https://opencores.org/websvn//websvn/listing?repname=xmatchpro&path=%2F& Mon, 11 May 2026 23:58:11 +0100 FeedCreator 1.7.2 full project for VC707 Virtex-7 board https://opencores.org/websvn//websvn/revision?repname=xmatchpro&path=%2F&rev=9 <div>Rev 9 - eejlny (1435 file(s) modified)</div><div>full project for VC707 Virtex-7 board</div>+ /xmatchpro/trunk/xmw4-comdec/xmatch_sim7 + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/Behavioral.wcfg + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/coregen.cgc + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/coregen.cgp + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_256 + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_256.asy + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_256.gise + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_256.ngc + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_256.vhd + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_256.vho + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_256.xco + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_256.xise + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_256/blk_mem_gen_v7_3_readme.txt + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_256/doc + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_256/doc/blk_mem_gen_v7_3_vinfo.html + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_256/doc/pg058-blk-mem-gen.pdf + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_256/example_design + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_256/example_design/DP_RAM_XILINX_256_exdes.ucf + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_256/example_design/DP_RAM_XILINX_256_exdes.vhd + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_256/example_design/DP_RAM_XILINX_256_exdes.xdc + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_256/example_design/DP_RAM_XILINX_256_prod.vhd + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_256/implement + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_256/implement/implement.bat + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_256/implement/implement.sh + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_256/implement/planAhead_ise.bat + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_256/implement/planAhead_ise.sh + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_256/implement/planAhead_ise.tcl + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_256/implement/xst.prj + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_256/implement/xst.scr + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_256/simulation + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_256/simulation/addr_gen.vhd + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_256/simulation/bmg_stim_gen.vhd + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_256/simulation/bmg_tb_pkg.vhd + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_256/simulation/checker.vhd + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_256/simulation/data_gen.vhd + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_256/simulation/DP_RAM_XILINX_256_synth.vhd + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_256/simulation/DP_RAM_XILINX_256_tb.vhd + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_256/simulation/functional + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_256/simulation/functional/simcmds.tcl + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_256/simulation/functional/simulate_isim.bat + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_256/simulation/functional/simulate_mti.bat + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_256/simulation/functional/simulate_mti.do + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_256/simulation/functional/simulate_mti.sh + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_256/simulation/functional/simulate_ncsim.sh + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_256/simulation/functional/simulate_vcs.sh + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_256/simulation/functional/ucli_commands.key + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_256/simulation/functional/vcs_session.tcl + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_256/simulation/functional/wave_mti.do + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_256/simulation/functional/wave_ncsim.sv + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_256/simulation/random.vhd + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_256/simulation/timing + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_256/simulation/timing/simcmds.tcl + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_256/simulation/timing/simulate_isim.bat + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_256/simulation/timing/simulate_mti.bat + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_256/simulation/timing/simulate_mti.do + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_256/simulation/timing/simulate_mti.sh + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_256/simulation/timing/simulate_ncsim.sh + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_256/simulation/timing/simulate_vcs.sh + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_256/simulation/timing/ucli_commands.key + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_256/simulation/timing/vcs_session.tcl + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_256/simulation/timing/wave_mti.do + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_256/simulation/timing/wave_ncsim.sv + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_256_flist.txt + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_256_xmdf.tcl + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_512 + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_512.asy + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_512.gise + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_512.ngc + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_512.vhd + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_512.vho + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_512.xco + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_512.xise + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_512/blk_mem_gen_v7_3_readme.txt + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_512/doc + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_512/doc/blk_mem_gen_v7_3_vinfo.html + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_512/doc/pg058-blk-mem-gen.pdf + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_512/example_design + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_512/example_design/DP_RAM_XILINX_512_exdes.ucf + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_512/example_design/DP_RAM_XILINX_512_exdes.vhd + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_512/example_design/DP_RAM_XILINX_512_exdes.xdc + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_512/example_design/DP_RAM_XILINX_512_prod.vhd + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_512/implement + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_512/implement/implement.bat + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_512/implement/implement.sh + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_512/implement/planAhead_ise.bat + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_512/implement/planAhead_ise.sh + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_512/implement/planAhead_ise.tcl + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_512/implement/xst.prj + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_512/implement/xst.scr + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_512/simulation + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_512/simulation/addr_gen.vhd + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_512/simulation/bmg_stim_gen.vhd + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_512/simulation/bmg_tb_pkg.vhd + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_512/simulation/checker.vhd + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_512/simulation/data_gen.vhd + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_512/simulation/DP_RAM_XILINX_512_synth.vhd + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_512/simulation/DP_RAM_XILINX_512_tb.vhd + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_512/simulation/functional + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_512/simulation/functional/simcmds.tcl + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_512/simulation/functional/simulate_isim.bat + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_512/simulation/functional/simulate_mti.bat + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_512/simulation/functional/simulate_mti.do + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_512/simulation/functional/simulate_mti.sh + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_512/simulation/functional/simulate_ncsim.sh + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_512/simulation/functional/simulate_vcs.sh + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_512/simulation/functional/ucli_commands.key + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_512/simulation/functional/vcs_session.tcl + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_512/simulation/functional/wave_mti.do + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_512/simulation/functional/wave_ncsim.sv + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_512/simulation/random.vhd + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_512/simulation/timing + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_512/simulation/timing/simcmds.tcl + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_512/simulation/timing/simulate_isim.bat + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_512/simulation/timing/simulate_mti.bat + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_512/simulation/timing/simulate_mti.do + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_512/simulation/timing/simulate_mti.sh + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_512/simulation/timing/simulate_ncsim.sh + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_512/simulation/timing/simulate_vcs.sh + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_512/simulation/timing/ucli_commands.key + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_512/simulation/timing/vcs_session.tcl + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_512/simulation/timing/wave_mti.do + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_512/simulation/timing/wave_ncsim.sv + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_512_flist.txt + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_512_xmdf.tcl + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_MASK + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_MASK.asy + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_MASK.gise + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_MASK.ngc + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_MASK.vhd + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_MASK.vho + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_MASK.xco + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_MASK.xise + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_MASK/blk_mem_gen_v7_3_readme.txt + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_MASK/doc + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_MASK/doc/blk_mem_gen_v7_3_vinfo.html + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_MASK/doc/pg058-blk-mem-gen.pdf + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_MASK/example_design + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_MASK/example_design/DP_RAM_XILINX_MASK_exdes.ucf + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_MASK/example_design/DP_RAM_XILINX_MASK_exdes.vhd + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_MASK/example_design/DP_RAM_XILINX_MASK_exdes.xdc + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_MASK/example_design/DP_RAM_XILINX_MASK_prod.vhd + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_MASK/implement + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_MASK/implement/implement.bat + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_MASK/implement/implement.sh + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_MASK/implement/planAhead_ise.bat + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_MASK/implement/planAhead_ise.sh + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_MASK/implement/planAhead_ise.tcl + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_MASK/implement/xst.prj + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/coregen/DP_RAM_XILINX_MASK/implement/xst.scr + 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/xmatchpro/trunk/xmw4-comdec/xmatch_sim7/test_file/CONFIRM_DATA_2048.txt + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/test_file/CONFIRM_OUTPUT_COMPRESSED_1KB_BLOCKSIZE.txt + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/test_file/CONFIRM_output_compressed_X.txt + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/test_file/CONFIRM_output_decompressed_X.txt + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/test_file/Cvectors_alic_1024.txt + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/test_file/Cvectors_fiel_1024.txt + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/test_file/Cvectors_kenn_3422.txt + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/test_file/Cvectors_plra_2712.txt + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/test_file/C_1F.txt + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/test_file/C_1KB_F_ORIGINAL.txt + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/test_file/C_4KB_TEST.txt + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/test_file/C_4KB_TEST_NEW_BLOCKSIZE.txt + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/test_file/C_4KB_TEST_ORIGINAL.txt + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/test_file/C_32KB_A.txt + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/test_file/C_32KB_S.txt + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/test_file/C_64KB_A.txt + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/test_file/C_723936_S.txt + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/test_file/C_alice_8192_NEW_BLOCKSIZE.txt + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/test_file/C_alice_32768_NEW_BLOCKSIZE.txt + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/test_file/C_alice_167520_NEW_BLOCKSIZE.txt + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/test_file/D_1F.txt + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/test_file/D_4KB_TEST.txt + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/test_file/D_4KB_TEST_NEW_BLOCKSIZE.txt + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/test_file/D_alice_8192_NEW_BLOCKSIZE.txt + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/test_file/D_alice_32768_NEW_BLOCKSIZE.txt + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/test_file/D_alice_167520_NEW_BLOCKSIZE.txt + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/test_file/file_compressed_256_ori_xmatch.txt + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/test_file/out.pro + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/test_file/output_compressed_AX.txt + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/test_file/output_compressed_AX2.txt + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/test_file/output_compressed_AXFULL.txt + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/test_file/output_compressed_X.txt + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/test_file/output_compressed_XALICE.txt + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/test_file/output_compressed_X_ALICE1KB_CONFIRM.txt + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/test_file/output_decompressed_X.txt + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/test_file/output_decompressed_X.txt.bak + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/test_file/outx.txt + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/test_file/sample_data_original_xmatch_256.txt + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/test_file/sample_data_original_xmatch_256_decompressed.txt + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/test_file/sp_ibm723936.bin + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/test_file/test_2kB.txt + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/test_file/test_out.txt + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/test_file/tvin_c.txt + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/test_file/tvout_c.txt + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/test_file/tvout_c_OK.txt + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/test_file/tvout_d.txt + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/test_file/tvout_d_OK.txt + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/test_file/U_1KB_F.txt + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/test_file/U_4KB_TEST.txt + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/test_file/U_32KB_A.txt + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/test_file/U_32KB_S.txt + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/test_file/U_64KB_A.txt + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/test_file/U_308_M.txt + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/test_file/U_723936_S.txt + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/test_file/U_alice_2048.txt + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/test_file/U_alice_8192.txt + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/test_file/U_alice_32768.txt + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/test_file/U_alice_32768.txt.bak + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/test_file/U_alice_167520.txt + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/test_file/U_alice_167520.txt.bak + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/test_file/v2bfile.bin + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/test_file/xmatch_256_compressed_original.txt + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/test_file/xmw4.exe + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/xilinxsim.ini + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/xmatchpro_summary.html + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/xmatch_controller.vhd + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/xmatch_controller_summary.html + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/_xmsgs + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/_xmsgs/netgen.xmsgs + /xmatchpro/trunk/xmw4-comdec/xmatch_sim7/_xmsgs/pn_parser.xmsgs eejlny Wed, 06 Jan 2016 15:19:37 +0100 https://opencores.org/websvn//websvn/revision?repname=xmatchpro&path=%2F&rev=9 bug fixes and update to latest sources https://opencores.org/websvn//websvn/revision?repname=xmatchpro&path=%2F&rev=8 <div>Rev 8 - eejlny (1822 file(s) modified)</div><div>bug fixes and update to latest sources</div>+ /xmatchpro/trunk/xmw4-comdec + /xmatchpro/trunk/xmw4-comdec/bin + /xmatchpro/trunk/xmw4-comdec/bin/xmw51.exe + /xmatchpro/trunk/xmw4-comdec/doc + /xmatchpro/trunk/xmw4-comdec/doc/CR_comp.pdf + /xmatchpro/trunk/xmw4-comdec/doc/datefinal.pdf + /xmatchpro/trunk/xmw4-comdec/doc/HK_paper.PDF + /xmatchpro/trunk/xmw4-comdec/doc/IEEE_GBIT.pdf + /xmatchpro/trunk/xmw4-comdec/doc/registers.vsdx + /xmatchpro/trunk/xmw4-comdec/doc/X-MatchPROv7_datasheet.doc + /xmatchpro/trunk/xmw4-comdec/doc/xmat_fpl.pdf + /xmatchpro/trunk/xmw4-comdec/doc/xmlite.pdf + /xmatchpro/trunk/xmw4-comdec/doc/xmw.pdf + /xmatchpro/trunk/xmw4-comdec/lgpl.txt + /xmatchpro/trunk/xmw4-comdec/lib + /xmatchpro/trunk/xmw4-comdec/lib/dzx + /xmatchpro/trunk/xmw4-comdec/lib/dzx/attributes_pkg.vhd + /xmatchpro/trunk/xmw4-comdec/lib/dzx/bit_arith_pkg.vhd + /xmatchpro/trunk/xmw4-comdec/lib/dzx/bit_arith_pkg_body.vhd + /xmatchpro/trunk/xmw4-comdec/lib/dzx/bit_utils_pkg.vhd + /xmatchpro/trunk/xmw4-comdec/lib/dzx/bit_utils_pkg_body.vhd + /xmatchpro/trunk/xmw4-comdec/lib/dzx/transcript + /xmatchpro/trunk/xmw4-comdec/lib/lpm + /xmatchpro/trunk/xmw4-comdec/lib/lpm/220model.vhd + /xmatchpro/trunk/xmw4-comdec/lib/lpm/220PACK.VHD + /xmatchpro/trunk/xmw4-comdec/lib/xil_lib + /xmatchpro/trunk/xmw4-comdec/lib/xil_lib/DP_RAM_XILINX_256.ngc + /xmatchpro/trunk/xmw4-comdec/lib/xil_lib/DP_RAM_XILINX_256.vhd + /xmatchpro/trunk/xmw4-comdec/lib/xil_lib/DP_RAM_XILINX_512.ngc + /xmatchpro/trunk/xmw4-comdec/lib/xil_lib/DP_RAM_XILINX_512.vhd + /xmatchpro/trunk/xmw4-comdec/lib/xil_lib/DP_RAM_XILINX_MASK.ngc + /xmatchpro/trunk/xmw4-comdec/lib/xil_lib/DP_RAM_XILINX_MASK.vhd + /xmatchpro/trunk/xmw4-comdec/lib/xil_lib/xil_comp.vhd + /xmatchpro/trunk/xmw4-comdec/prj + /xmatchpro/trunk/xmw4-comdec/prj/ISE + /xmatchpro/trunk/xmw4-comdec/prj/ISE/DP_RAM_XILINX_256.ngc + /xmatchpro/trunk/xmw4-comdec/prj/ISE/DP_RAM_XILINX_512.ngc + /xmatchpro/trunk/xmw4-comdec/prj/ISE/DP_RAM_XILINX_MASK.ngc + /xmatchpro/trunk/xmw4-comdec/prj/ISE/xmw2_comdec.npl + /xmatchpro/trunk/xmw4-comdec/prj/Modelsim + /xmatchpro/trunk/xmw4-comdec/prj/Modelsim/dzx + /xmatchpro/trunk/xmw4-comdec/prj/Modelsim/dzx/attributes + /xmatchpro/trunk/xmw4-comdec/prj/Modelsim/dzx/attributes/_primary.dat + /xmatchpro/trunk/xmw4-comdec/prj/Modelsim/dzx/attributes/_primary.dbs + /xmatchpro/trunk/xmw4-comdec/prj/Modelsim/dzx/bit_arith + /xmatchpro/trunk/xmw4-comdec/prj/Modelsim/dzx/bit_arith/body.dat + /xmatchpro/trunk/xmw4-comdec/prj/Modelsim/dzx/bit_arith/body.dbs + /xmatchpro/trunk/xmw4-comdec/prj/Modelsim/dzx/bit_arith/_primary.dat + /xmatchpro/trunk/xmw4-comdec/prj/Modelsim/dzx/bit_arith/_primary.dbs + /xmatchpro/trunk/xmw4-comdec/prj/Modelsim/dzx/bit_utils + /xmatchpro/trunk/xmw4-comdec/prj/Modelsim/dzx/bit_utils/body.dat + /xmatchpro/trunk/xmw4-comdec/prj/Modelsim/dzx/bit_utils/body.dbs + /xmatchpro/trunk/xmw4-comdec/prj/Modelsim/dzx/bit_utils/_primary.dat + /xmatchpro/trunk/xmw4-comdec/prj/Modelsim/dzx/bit_utils/_primary.dbs + /xmatchpro/trunk/xmw4-comdec/prj/Modelsim/dzx/_info + /xmatchpro/trunk/xmw4-comdec/prj/Modelsim/dzx/_temp + /xmatchpro/trunk/xmw4-comdec/prj/Modelsim/dzx/_vmake + /xmatchpro/trunk/xmw4-comdec/prj/Modelsim/vsim.wlf + /xmatchpro/trunk/xmw4-comdec/prj/Modelsim/vw.do + /xmatchpro/trunk/xmw4-comdec/prj/Modelsim/work + /xmatchpro/trunk/xmw4-comdec/prj/Modelsim/work/@_opt + /xmatchpro/trunk/xmw4-comdec/prj/Modelsim/work/@_opt/vopt0ac2ex + /xmatchpro/trunk/xmw4-comdec/prj/Modelsim/work/@_opt/vopt0b8n36 + /xmatchpro/trunk/xmw4-comdec/prj/Modelsim/work/@_opt/vopt0c1ser + /xmatchpro/trunk/xmw4-comdec/prj/Modelsim/work/@_opt/vopt0dxc41 + /xmatchpro/trunk/xmw4-comdec/prj/Modelsim/work/@_opt/vopt0es0t9 + /xmatchpro/trunk/xmw4-comdec/prj/Modelsim/work/@_opt/vopt0fi35w + /xmatchpro/trunk/xmw4-comdec/prj/Modelsim/work/@_opt/vopt0geqt4 + /xmatchpro/trunk/xmw4-comdec/prj/Modelsim/work/@_opt/vopt0habgd + /xmatchpro/trunk/xmw4-comdec/prj/Modelsim/work/@_opt/vopt0i3evz + /xmatchpro/trunk/xmw4-comdec/prj/Modelsim/work/@_opt/vopt0jz1h8 + /xmatchpro/trunk/xmw4-comdec/prj/Modelsim/work/@_opt/vopt0kvm6h + /xmatchpro/trunk/xmw4-comdec/prj/Modelsim/work/@_opt/vopt0mkrh3 + /xmatchpro/trunk/xmw4-comdec/prj/Modelsim/work/@_opt/vopt0ngc7c + /xmatchpro/trunk/xmw4-comdec/prj/Modelsim/work/@_opt/vopt0qc0xk + /xmatchpro/trunk/xmw4-comdec/prj/Modelsim/work/@_opt/vopt0r5387 + /xmatchpro/trunk/xmw4-comdec/prj/Modelsim/work/@_opt/vopt0s1qxf + /xmatchpro/trunk/xmw4-comdec/prj/Modelsim/work/@_opt/vopt0txajr + /xmatchpro/trunk/xmw4-comdec/prj/Modelsim/work/@_opt/vopt0vndya + /xmatchpro/trunk/xmw4-comdec/prj/Modelsim/work/@_opt/vopt0wi1kj + /xmatchpro/trunk/xmw4-comdec/prj/Modelsim/work/@_opt/vopt0xem9w + /xmatchpro/trunk/xmw4-comdec/prj/Modelsim/work/@_opt/vopt0y7rke + /xmatchpro/trunk/xmw4-comdec/prj/Modelsim/work/@_opt/vopt0z3caq + /xmatchpro/trunk/xmw4-comdec/prj/Modelsim/work/@_opt/vopt01s2bi + /xmatchpro/trunk/xmw4-comdec/prj/Modelsim/work/@_opt/vopt02mn0v + /xmatchpro/trunk/xmw4-comdec/prj/Modelsim/work/@_opt/vopt04ad1n + /xmatchpro/trunk/xmw4-comdec/prj/Modelsim/work/@_opt/vopt0561qy + /xmatchpro/trunk/xmw4-comdec/prj/Modelsim/work/@_opt/vopt07vqqs + /xmatchpro/trunk/xmw4-comdec/prj/Modelsim/work/@_opt/vopt08qbd2 + /xmatchpro/trunk/xmw4-comdec/prj/Modelsim/work/@_opt/vopt09gerk + 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/xmatchpro/trunk/xmw4-comdec/prj/Modelsim/xil_lib/dp_ram_xilinx_256/_primary.dbs + /xmatchpro/trunk/xmw4-comdec/prj/Modelsim/xil_lib/dp_ram_xilinx_512 + /xmatchpro/trunk/xmw4-comdec/prj/Modelsim/xil_lib/dp_ram_xilinx_512/dp_ram_xilinx_512_a.dat + /xmatchpro/trunk/xmw4-comdec/prj/Modelsim/xil_lib/dp_ram_xilinx_512/dp_ram_xilinx_512_a.dbs + /xmatchpro/trunk/xmw4-comdec/prj/Modelsim/xil_lib/dp_ram_xilinx_512/_primary.dat + /xmatchpro/trunk/xmw4-comdec/prj/Modelsim/xil_lib/dp_ram_xilinx_512/_primary.dbs + /xmatchpro/trunk/xmw4-comdec/prj/Modelsim/xil_lib/dp_ram_xilinx_mask + /xmatchpro/trunk/xmw4-comdec/prj/Modelsim/xil_lib/dp_ram_xilinx_mask/dp_ram_xilinx_mask_a.dat + /xmatchpro/trunk/xmw4-comdec/prj/Modelsim/xil_lib/dp_ram_xilinx_mask/dp_ram_xilinx_mask_a.dbs + /xmatchpro/trunk/xmw4-comdec/prj/Modelsim/xil_lib/dp_ram_xilinx_mask/_primary.dat + /xmatchpro/trunk/xmw4-comdec/prj/Modelsim/xil_lib/dp_ram_xilinx_mask/_primary.dbs + /xmatchpro/trunk/xmw4-comdec/prj/Modelsim/xil_lib/xil_comp + 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/xmatchpro/trunk/xmw4-comdec/src/decode_mt.vhd + /xmatchpro/trunk/xmw4-comdec/src/decode_mt_2.vhd + /xmatchpro/trunk/xmw4-comdec/src/DECODING_BUFFER_32_64_2.vhd + /xmatchpro/trunk/xmw4-comdec/src/DECODING_BUFFER_CU_2.vhd + /xmatchpro/trunk/xmw4-comdec/src/decomp_assem_9.vhd + /xmatchpro/trunk/xmw4-comdec/src/decomp_decode_4.vhd + /xmatchpro/trunk/xmw4-comdec/src/encode16_4.vhd + /xmatchpro/trunk/xmw4-comdec/src/ff_finish_decoding.vhd + /xmatchpro/trunk/xmw4-comdec/src/ff_v3_delay.vhd + /xmatchpro/trunk/xmw4-comdec/src/full_match_d.vhd + /xmatchpro/trunk/xmw4-comdec/src/input_buffer_32_32.vhd + /xmatchpro/trunk/xmw4-comdec/src/input_buffer_cu.vhd + /xmatchpro/trunk/xmw4-comdec/src/input_counter.vhd + /xmatchpro/trunk/xmw4-comdec/src/input_counter_9bits.vhd + /xmatchpro/trunk/xmw4-comdec/src/latch6.vhd + /xmatchpro/trunk/xmw4-comdec/src/latch7.vhd + /xmatchpro/trunk/xmw4-comdec/src/latch96.vhd + /xmatchpro/trunk/xmw4-comdec/src/latch98.vhd + /xmatchpro/trunk/xmw4-comdec/src/latch129.vhd + /xmatchpro/trunk/xmw4-comdec/src/latch133.vhd + /xmatchpro/trunk/xmw4-comdec/src/lc_assembler.vhd + /xmatchpro/trunk/xmw4-comdec/src/length_selection_2.vhd + /xmatchpro/trunk/xmw4-comdec/src/level1r.vhd + /xmatchpro/trunk/xmw4-comdec/src/level1rc.vhd + /xmatchpro/trunk/xmw4-comdec/src/level1rd.vhd + /xmatchpro/trunk/xmw4-comdec/src/level2_4ca.vhd + /xmatchpro/trunk/xmw4-comdec/src/level2_4d_pbc.vhd + /xmatchpro/trunk/xmw4-comdec/src/location_equal.vhd + /xmatchpro/trunk/xmw4-comdec/src/lpm_ram_dp_mask.vhd + /xmatchpro/trunk/xmw4-comdec/src/mask_bit.vhd + /xmatchpro/trunk/xmw4-comdec/src/mask_word.vhd + /xmatchpro/trunk/xmw4-comdec/src/max_pbc_length_2.vhd + /xmatchpro/trunk/xmw4-comdec/src/mc_mux_3c.vhd + /xmatchpro/trunk/xmw4-comdec/src/mc_mux_3d.vhd + /xmatchpro/trunk/xmw4-comdec/src/mg_logic_2.vhd + /xmatchpro/trunk/xmw4-comdec/src/miss_type_coder.vhd + /xmatchpro/trunk/xmw4-comdec/src/mld_decode.vhd + /xmatchpro/trunk/xmw4-comdec/src/mld_dprop.vhd + /xmatchpro/trunk/xmw4-comdec/src/mld_dprop_5.vhd + /xmatchpro/trunk/xmw4-comdec/src/mld_logic_3_1_2.vhd + /xmatchpro/trunk/xmw4-comdec/src/mld_logic_3_2_2.vhd + /xmatchpro/trunk/xmw4-comdec/src/mt_coder.vhd + /xmatchpro/trunk/xmw4-comdec/src/mux_ram.vhd + /xmatchpro/trunk/xmw4-comdec/src/my_mask_memory.vhd + /xmatchpro/trunk/xmw4-comdec/src/my_memory.vhd + /xmatchpro/trunk/xmw4-comdec/src/nfl_counters2.vhd + /xmatchpro/trunk/xmw4-comdec/src/ob_assem.vhd + /xmatchpro/trunk/xmw4-comdec/src/ob_assembler.vhd + /xmatchpro/trunk/xmw4-comdec/src/oda_cell_2.vhd + /xmatchpro/trunk/xmw4-comdec/src/oda_cell_2_d.vhd + /xmatchpro/trunk/xmw4-comdec/src/oda_cell_2_d_1.vhd + /xmatchpro/trunk/xmw4-comdec/src/oda_register.vhd + /xmatchpro/trunk/xmw4-comdec/src/oda_register_d.vhd + /xmatchpro/trunk/xmw4-comdec/src/output_buffer_32_32.vhd + /xmatchpro/trunk/xmw4-comdec/src/output_buffer_cu.vhd + /xmatchpro/trunk/xmw4-comdec/src/out_register.vhd + /xmatchpro/trunk/xmw4-comdec/src/ov_latch.vhd + /xmatchpro/trunk/xmw4-comdec/src/parser.vhd + /xmatchpro/trunk/xmw4-comdec/src/parser_concatenator.vhd + /xmatchpro/trunk/xmw4-comdec/src/parser_register.vhd + /xmatchpro/trunk/xmw4-comdec/src/parsing_unit.vhd + /xmatchpro/trunk/xmw4-comdec/src/pc_generate.vhd + /xmatchpro/trunk/xmw4-comdec/src/PIPELINE_R0.vhd + /xmatchpro/trunk/xmw4-comdec/src/PIPELINE_R1.vhd + /xmatchpro/trunk/xmw4-comdec/src/PIPELINE_R1_D.vhd + /xmatchpro/trunk/xmw4-comdec/src/PIPELINE_R2_D.vhd + /xmatchpro/trunk/xmw4-comdec/src/PIPELINE_R4.vhd + /xmatchpro/trunk/xmw4-comdec/src/pointer_1.vhd + /xmatchpro/trunk/xmw4-comdec/src/pointer_2.vhd + /xmatchpro/trunk/xmw4-comdec/src/pointer_3.vhd + /xmatchpro/trunk/xmw4-comdec/src/pointer_4.vhd + /xmatchpro/trunk/xmw4-comdec/src/pointer_5.vhd + /xmatchpro/trunk/xmw4-comdec/src/pointer_6.vhd + /xmatchpro/trunk/xmw4-comdec/src/pointer_7.vhd + /xmatchpro/trunk/xmw4-comdec/src/pointer_8.vhd + /xmatchpro/trunk/xmw4-comdec/src/pointer_9.vhd + /xmatchpro/trunk/xmw4-comdec/src/pointer_10.vhd + /xmatchpro/trunk/xmw4-comdec/src/pointer_11.vhd + /xmatchpro/trunk/xmw4-comdec/src/pointer_12.vhd + /xmatchpro/trunk/xmw4-comdec/src/pointer_13.vhd + /xmatchpro/trunk/xmw4-comdec/src/pointer_14.vhd + /xmatchpro/trunk/xmw4-comdec/src/pointer_15.vhd + /xmatchpro/trunk/xmw4-comdec/src/pointer_array.vhd + /xmatchpro/trunk/xmw4-comdec/src/pointer_first.vhd + /xmatchpro/trunk/xmw4-comdec/src/register_bank.vhd + /xmatchpro/trunk/xmw4-comdec/src/reg_file_c.vhd + /xmatchpro/trunk/xmw4-comdec/src/reg_file_d.vhd + /xmatchpro/trunk/xmw4-comdec/src/reg_temp.vhd + /xmatchpro/trunk/xmw4-comdec/src/RLI_CCU.vhd + /xmatchpro/trunk/xmw4-comdec/src/RLI_coding_logic.vhd + /xmatchpro/trunk/xmw4-comdec/src/rli_counter_c.vhd + /xmatchpro/trunk/xmw4-comdec/src/rli_counter_d.vhd + /xmatchpro/trunk/xmw4-comdec/src/RLI_CR.vhd + /xmatchpro/trunk/xmw4-comdec/src/RLI_DCU.vhd + /xmatchpro/trunk/xmw4-comdec/src/RLI_DR.vhd + /xmatchpro/trunk/xmw4-comdec/src/shift_byte.vhd + /xmatchpro/trunk/xmw4-comdec/src/shift_literal.vhd + /xmatchpro/trunk/xmw4-comdec/src/sreg.vhd + /xmatchpro/trunk/xmw4-comdec/src/sync_ram_register.vhd + /xmatchpro/trunk/xmw4-comdec/src/tb_level1cr.vhd + /xmatchpro/trunk/xmw4-comdec/src/tb_level1cr.vhd.bak + /xmatchpro/trunk/xmw4-comdec/src/tech_package.vhd + /xmatchpro/trunk/xmw4-comdec/src/transcript + /xmatchpro/trunk/xmw4-comdec/test + /xmatchpro/trunk/xmw4-comdec/test/Cvectors_alic_1024.txt + /xmatchpro/trunk/xmw4-comdec/test/Cvectors_fiel_1024.txt + /xmatchpro/trunk/xmw4-comdec/test/Cvectors_kenn_3422.txt + /xmatchpro/trunk/xmw4-comdec/test/Cvectors_plra_2712.txt - /xmatchpro/web_uploads eejlny Wed, 06 Jan 2016 14:22:02 +0100 https://opencores.org/websvn//websvn/revision?repname=xmatchpro&path=%2F&rev=8 update to Xilinx V4/V5 https://opencores.org/websvn//websvn/revision?repname=xmatchpro&path=%2F&rev=7 <div>Rev 7 - eejlny (2 file(s) modified)</div><div>update to Xilinx V4/V5</div>- /xmatchpro/web_uploads/open_xmw2.zip + /xmatchpro/web_uploads/xmw3-comdec.zip eejlny Sat, 19 Sep 2009 14:07:00 +0100 https://opencores.org/websvn//websvn/revision?repname=xmatchpro&path=%2F&rev=7 Added old uploaded documents to new repository. https://opencores.org/websvn//websvn/revision?repname=xmatchpro&path=%2F&rev=6 <div>Rev 6 - root (6 file(s) modified)</div><div>Added old uploaded documents to new repository.</div>- /xmatchpro/web_uploads/oc_checkin.sh - /xmatchpro/web_uploads/oc_cvs_checkin.sh + /xmatchpro/web_uploads/open_xmw2.zip - /xmatchpro/web_uploads/svn_checkin.log - /xmatchpro/web_uploads/svn_checkin.sh - /xmatchpro/web_uploads/temp.sh root Tue, 10 Mar 2009 16:12:34 +0100 https://opencores.org/websvn//websvn/revision?repname=xmatchpro&path=%2F&rev=6 Added old uploaded documents to new repository. https://opencores.org/websvn//websvn/revision?repname=xmatchpro&path=%2F&rev=5 <div>Rev 5 - root (5 file(s) modified)</div><div>Added old uploaded documents to new repository.</div>+ /xmatchpro/web_uploads/oc_checkin.sh + /xmatchpro/web_uploads/oc_cvs_checkin.sh + /xmatchpro/web_uploads/svn_checkin.log + /xmatchpro/web_uploads/svn_checkin.sh + /xmatchpro/web_uploads/temp.sh root Tue, 10 Mar 2009 10:50:13 +0100 https://opencores.org/websvn//websvn/revision?repname=xmatchpro&path=%2F&rev=5 New directory structure. https://opencores.org/websvn//websvn/revision?repname=xmatchpro&path=%2F&rev=4 <div>Rev 4 - root (8 file(s) modified)</div><div>New directory structure.</div>- /branches - /tags - /trunk + /xmatchpro + /xmatchpro/branches + /xmatchpro/tags + /xmatchpro/trunk + /xmatchpro/web_uploads root Tue, 10 Mar 2009 10:49:44 +0100 https://opencores.org/websvn//websvn/revision?repname=xmatchpro&path=%2F&rev=4 project created https://opencores.org/websvn//websvn/revision?repname=xmatchpro&path=%2F&rev=3 <div>Rev 3 - marcus (1 file(s) modified)</div><div>project created</div>+ /branches marcus Mon, 09 Mar 2009 16:05:13 +0100 https://opencores.org/websvn//websvn/revision?repname=xmatchpro&path=%2F&rev=3 project created https://opencores.org/websvn//websvn/revision?repname=xmatchpro&path=%2F&rev=2 <div>Rev 2 - marcus (1 file(s) modified)</div><div>project created</div>+ /trunk marcus Mon, 09 Mar 2009 16:05:13 +0100 https://opencores.org/websvn//websvn/revision?repname=xmatchpro&path=%2F&rev=2 project created https://opencores.org/websvn//websvn/revision?repname=xmatchpro&path=%2F&rev=1 <div>Rev 1 - marcus (1 file(s) modified)</div><div>project created</div>+ /tags marcus Mon, 09 Mar 2009 16:05:13 +0100 https://opencores.org/websvn//websvn/revision?repname=xmatchpro&path=%2F&rev=1

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