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https://opencores.org/ocsvn/yifive/yifive/trunk
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yifive
WebSVN RSS feed - yifive
https://opencores.org/websvn//websvn/listing?repname=yifive&path=%2F&
Mon, 24 Aug 2026 20:17:44 +0100
FeedCreator 1.7.2
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sdram added
https://opencores.org/websvn//websvn/revision?repname=yifive&path=%2F&rev=23
<div><strong>Rev 23 - dinesha</strong> (5 file(s) modified)</div><div>sdram added</div>~ /yifive/trunk/caravel_yifive/Makefile<br />+ /yifive/trunk/caravel_yifive/openlane/sdram<br />+ /yifive/trunk/caravel_yifive/openlane/sdram/config.tcl<br />+ /yifive/trunk/caravel_yifive/openlane/sdram/pin_order.cfg<br />+ /yifive/trunk/caravel_yifive/read.me<br />
dinesha
Sun, 13 Jun 2021 06:41:45 +0100
https://opencores.org/websvn//websvn/revision?repname=yifive&path=%2F&rev=23
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test bench update
https://opencores.org/websvn//websvn/revision?repname=yifive&path=%2F&rev=22
<div><strong>Rev 22 - dinesha</strong> (44 file(s) modified)</div><div>test bench update</div>~ /yifive/trunk/caravel_yifive/verilog/dv/io_ports/io_ports_tb.v<br />~ /yifive/trunk/caravel_yifive/verilog/dv/io_ports/Makefile<br />+ /yifive/trunk/caravel_yifive/verilog/dv/io_ports/mgmt_core.sv<br />~ /yifive/trunk/caravel_yifive/verilog/dv/la_test1/Makefile<br />~ /yifive/trunk/caravel_yifive/verilog/dv/la_test2/Makefile<br />~ /yifive/trunk/caravel_yifive/verilog/dv/Makefile<br />+ /yifive/trunk/caravel_yifive/verilog/dv/model<br />+ /yifive/trunk/caravel_yifive/verilog/dv/model/mt48lc8m8a2.v<br />+ /yifive/trunk/caravel_yifive/verilog/dv/risc_boot<br />+ /yifive/trunk/caravel_yifive/verilog/dv/risc_boot/Makefile<br />+ /yifive/trunk/caravel_yifive/verilog/dv/risc_boot/risc_boot.c<br />+ /yifive/trunk/caravel_yifive/verilog/dv/risc_boot/risc_boot_tb.v<br />+ /yifive/trunk/caravel_yifive/verilog/dv/risc_boot/run_iverilog<br />+ /yifive/trunk/caravel_yifive/verilog/dv/risc_boot/user_risc_boot.hex<br />+ /yifive/trunk/caravel_yifive/verilog/dv/user_risc_boot<br />+ /yifive/trunk/caravel_yifive/verilog/dv/user_risc_boot/Makefile<br />+ /yifive/trunk/caravel_yifive/verilog/dv/user_risc_boot/run_iverilog<br />+ /yifive/trunk/caravel_yifive/verilog/dv/user_risc_boot/uprj_netlists.v<br />+ /yifive/trunk/caravel_yifive/verilog/dv/user_risc_boot/user_risc_boot.c<br />+ /yifive/trunk/caravel_yifive/verilog/dv/user_risc_boot/user_risc_boot.hex<br />+ /yifive/trunk/caravel_yifive/verilog/dv/user_risc_boot/user_risc_boot_tb.v<br />~ /yifive/trunk/caravel_yifive/verilog/dv/wb_port/Makefile<br />~ /yifive/trunk/caravel_yifive/verilog/dv/wb_port/wb_port.c<br />~ /yifive/trunk/caravel_yifive/verilog/dv/wb_port/wb_port_tb.v<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/digital_core/src/glbl_cfg.sv<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/lib/clk_ctl.v<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/lib/registers.v<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/sim<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/sim/tests<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/sim/tests/common<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/sim/tests/common/common.mk<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/sim/tests/common/crt.S<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/sim/tests/common/crt_tcm.S<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/sim/tests/common/csr.h<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/sim/tests/common/LICENSE<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/sim/tests/common/link.ld<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/sim/tests/common/link_tcm.ld<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/sim/tests/common/reloc.h<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/sim/tests/common/riscv_csr_encoding.h<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/sim/tests/common/riscv_macros.h<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/sim/tests/common/scr1_specific.h<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/sim/tests/common/sc_print.c<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/sim/tests/common/sc_print.h<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/sim/tests/common/sc_test.h<br />
dinesha
Sun, 13 Jun 2021 06:39:28 +0100
https://opencores.org/websvn//websvn/revision?repname=yifive&path=%2F&rev=22
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Simulation clean up and wishbone interconnect added
https://opencores.org/websvn//websvn/revision?repname=yifive&path=%2F&rev=21
<div><strong>Rev 21 - dinesha</strong> (44 file(s) modified)</div><div>Simulation clean up and wishbone interconnect added</div>~ /yifive/trunk/caravel_yifive/verilog/rtl/digital_core/filelist_rtl.f<br />~ /yifive/trunk/caravel_yifive/verilog/rtl/digital_core/src/digital_core.sv<br />~ /yifive/trunk/caravel_yifive/verilog/rtl/lib/wb_crossbar.v<br />~ /yifive/trunk/caravel_yifive/verilog/rtl/sdram_ctrl/src/core/sdrc_core.v<br />~ /yifive/trunk/caravel_yifive/verilog/rtl/sdram_ctrl/src/core/sdrc_req_gen.v<br />~ /yifive/trunk/caravel_yifive/verilog/rtl/sdram_ctrl/src/core/sdrc_xfr_ctl.v<br />~ /yifive/trunk/caravel_yifive/verilog/rtl/spi_master/src/spim_clkgen.sv<br />~ /yifive/trunk/caravel_yifive/verilog/rtl/spi_master/src/spim_ctrl.sv<br />~ /yifive/trunk/caravel_yifive/verilog/rtl/spi_master/src/spim_regs.sv<br />~ /yifive/trunk/caravel_yifive/verilog/rtl/spi_master/src/spim_rx.sv<br />~ /yifive/trunk/caravel_yifive/verilog/rtl/spi_master/src/spim_top.sv<br />~ /yifive/trunk/caravel_yifive/verilog/rtl/spi_master/src/spim_tx.sv<br />~ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_exu.sv<br />~ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_ialu.sv<br />~ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_idu.sv<br />~ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_ifu.sv<br />~ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_lsu.sv<br />~ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_mprf.sv<br />~ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_top.sv<br />~ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_tracelog.sv<br />~ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/core/scr1_core_top.sv<br />~ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/core/scr1_dm.sv<br />~ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/includes/scr1_arch_types.svh<br />~ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/includes/scr1_memif.svh<br />~ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/includes/scr1_riscv_isa_decoding.svh<br />~ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/includes/scr1_scu.svh<br />~ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/top/scr1_dmem_ahb.sv<br />~ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/top/scr1_dmem_router.sv<br />~ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/top/scr1_dmem_wb.sv<br />~ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/top/scr1_imem_ahb.sv<br />~ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/top/scr1_imem_router.sv<br />~ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/top/scr1_imem_wb.sv<br />~ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/top/scr1_mem_axi.sv<br />~ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/top/scr1_tcm.sv<br />~ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/top/scr1_timer.sv<br />~ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/top/scr1_top_ahb.sv<br />~ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/top/scr1_top_axi.sv<br />~ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/top/scr1_top_wb.sv<br />~ /yifive/trunk/caravel_yifive/verilog/rtl/uprj_netlists.v<br />~ /yifive/trunk/caravel_yifive/verilog/rtl/user_project_wrapper.v<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/wb_interconnect<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/wb_interconnect/src<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/wb_interconnect/src/wb_arb.sv<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/wb_interconnect/src/wb_interconnect.sv<br />
dinesha
Sun, 13 Jun 2021 06:33:52 +0100
https://opencores.org/websvn//websvn/revision?repname=yifive&path=%2F&rev=21
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digital core added into svn
https://opencores.org/websvn//websvn/revision?repname=yifive&path=%2F&rev=20
<div><strong>Rev 20 - dinesha</strong> (12 file(s) modified)</div><div>digital core added into svn</div>+ /yifive/trunk/caravel_yifive/verilog/rtl/digital_core<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/digital_core/filelist_rtl.f<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/digital_core/run_modelsim<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/digital_core/src<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/digital_core/src/digital_core.sv<br />~ /yifive/trunk/caravel_yifive/verilog/rtl/lib/sync_fifo.sv<br />~ /yifive/trunk/caravel_yifive/verilog/rtl/lib/wb_crossbar.v<br />~ /yifive/trunk/caravel_yifive/verilog/rtl/sdram_ctrl/src/core/sdrc_core.v<br />~ /yifive/trunk/caravel_yifive/verilog/rtl/sdram_ctrl/src/top/sdrc_top.v<br />~ /yifive/trunk/caravel_yifive/verilog/rtl/sdram_ctrl/src/wb2sdrc/wb2sdrc.v<br />~ /yifive/trunk/caravel_yifive/verilog/rtl/spi_master/src/spim_top.sv<br />~ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/top/scr1_dmem_wb.sv<br />
dinesha
Tue, 08 Jun 2021 15:19:39 +0100
https://opencores.org/websvn//websvn/revision?repname=yifive&path=%2F&rev=20
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sdram control added
https://opencores.org/websvn//websvn/revision?repname=yifive&path=%2F&rev=19
<div><strong>Rev 19 - dinesha</strong> (22 file(s) modified)</div><div>sdram control added</div>+ /yifive/trunk/caravel_yifive/verilog/rtl/lib/async_fifo.sv<br />~ /yifive/trunk/caravel_yifive/verilog/rtl/lib/sync_fifo.sv<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/sdram_ctrl<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/sdram_ctrl/src<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/sdram_ctrl/src/core<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/sdram_ctrl/src/core/sdrc_bank_ctl.v<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/sdram_ctrl/src/core/sdrc_bank_fsm.v<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/sdram_ctrl/src/core/sdrc_bs_convert.v<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/sdram_ctrl/src/core/sdrc_core.v<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/sdram_ctrl/src/core/sdrc_req_gen.v<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/sdram_ctrl/src/core/sdrc_xfr_ctl.v<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/sdram_ctrl/src/defs<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/sdram_ctrl/src/defs/sdrc_define.v<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/sdram_ctrl/src/filelist_rtl.f<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/sdram_ctrl/src/run_modelsim<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/sdram_ctrl/src/top<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/sdram_ctrl/src/top/sdrc_top.v<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/sdram_ctrl/src/wb2sdrc<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/sdram_ctrl/src/wb2sdrc/wb2sdrc.v<br />~ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/top/scr1_dmem_wb.sv<br />~ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/top/scr1_imem_wb.sv<br />~ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/wb_top.files<br />
dinesha
Tue, 08 Jun 2021 11:20:32 +0100
https://opencores.org/websvn//websvn/revision?repname=yifive&path=%2F&rev=19
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spi master added
https://opencores.org/websvn//websvn/revision?repname=yifive&path=%2F&rev=18
<div><strong>Rev 18 - dinesha</strong> (15 file(s) modified)</div><div>spi master added</div>+ /yifive/trunk/caravel_yifive/openlane/spi_master<br />+ /yifive/trunk/caravel_yifive/openlane/spi_master/config.tcl<br />+ /yifive/trunk/caravel_yifive/openlane/spi_master/pin_order.cfg<br />~ /yifive/trunk/caravel_yifive/openlane/syntacore/config.tcl<br />~ /yifive/trunk/caravel_yifive/verilog/rtl/lib/sync_fifo.sv<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/spi_master<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/spi_master/src<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/spi_master/src/filelist.f<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/spi_master/src/spim_clkgen.sv<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/spi_master/src/spim_ctrl.sv<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/spi_master/src/spim_fifo.sv<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/spi_master/src/spim_regs.sv<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/spi_master/src/spim_rx.sv<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/spi_master/src/spim_top.sv<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/spi_master/src/spim_tx.sv<br />
dinesha
Tue, 08 Jun 2021 10:58:01 +0100
https://opencores.org/websvn//websvn/revision?repname=yifive&path=%2F&rev=18
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syntacore_scr1 directory removal
https://opencores.org/websvn//websvn/revision?repname=yifive&path=%2F&rev=17
<div><strong>Rev 17 - dinesha</strong> (1 file(s) modified)</div><div>syntacore_scr1 directory removal</div>- /yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1<br />
dinesha
Mon, 07 Jun 2021 16:03:00 +0100
https://opencores.org/websvn//websvn/revision?repname=yifive&path=%2F&rev=17
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syntacore_scr1 directory removal
https://opencores.org/websvn//websvn/revision?repname=yifive&path=%2F&rev=16
<div><strong>Rev 16 - dinesha</strong> (5 file(s) modified)</div><div>syntacore_scr1 directory removal</div>- /yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/src/ahb_top.files<br />- /yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/src/axi_top.files<br />- /yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/src/core.files<br />- /yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/src/run_modemsim<br />- /yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/src/wb_top.files<br />
dinesha
Mon, 07 Jun 2021 16:02:40 +0100
https://opencores.org/websvn//websvn/revision?repname=yifive&path=%2F&rev=16
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syntacore_scr1 directory removal
https://opencores.org/websvn//websvn/revision?repname=yifive&path=%2F&rev=15
<div><strong>Rev 15 - dinesha</strong> (3 file(s) modified)</div><div>syntacore_scr1 directory removal</div>- /yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/src/core<br />- /yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/src/includes<br />- /yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/src/top<br />
dinesha
Mon, 07 Jun 2021 16:02:13 +0100
https://opencores.org/websvn//websvn/revision?repname=yifive&path=%2F&rev=15
-
syntacore_scr1 directory removal
https://opencores.org/websvn//websvn/revision?repname=yifive&path=%2F&rev=14
<div><strong>Rev 14 - dinesha</strong> (1 file(s) modified)</div><div>syntacore_scr1 directory removal</div>- /yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/synth<br />
dinesha
Mon, 07 Jun 2021 16:01:45 +0100
https://opencores.org/websvn//websvn/revision?repname=yifive&path=%2F&rev=14
-
syntacore_scr1 directory removal
https://opencores.org/websvn//websvn/revision?repname=yifive&path=%2F&rev=13
<div><strong>Rev 13 - dinesha</strong> (3 file(s) modified)</div><div>syntacore_scr1 directory removal</div>- /yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/synth/Makefile<br />- /yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/synth/run_synth<br />- /yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/synth/synth.tcl<br />
dinesha
Mon, 07 Jun 2021 16:01:05 +0100
https://opencores.org/websvn//websvn/revision?repname=yifive&path=%2F&rev=13
-
syntacore_scr1 directory removal
https://opencores.org/websvn//websvn/revision?repname=yifive&path=%2F&rev=12
<div><strong>Rev 12 - dinesha</strong> (4 file(s) modified)</div><div>syntacore_scr1 directory removal</div>- /yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/docs<br />- /yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/LICENSE<br />- /yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/Makefile<br />- /yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/README.md<br />
dinesha
Mon, 07 Jun 2021 16:00:46 +0100
https://opencores.org/websvn//websvn/revision?repname=yifive&path=%2F&rev=12
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syntacore directory update
https://opencores.org/websvn//websvn/revision?repname=yifive&path=%2F&rev=11
<div><strong>Rev 11 - dinesha</strong> (76 file(s) modified)</div><div>syntacore directory update</div>+ /yifive/trunk/caravel_yifive/verilog/rtl/lib/sync_fifo.sv<br />~ /yifive/trunk/caravel_yifive/verilog/rtl/lib/wb_interface.v<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/docs<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/docs/img<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/docs/img/scr1_cluster.svg<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/docs/scr1_eas.pdf<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/docs/scr1_um.pdf<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/LICENSE<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/Makefile<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/README.md<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/ahb_top.files<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/axi_top.files<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/core<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/core.files<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/core/pipeline<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_ipic.sv<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_csr.sv<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_exu.sv<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_hdu.sv<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_ialu.sv<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_idu.sv<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_ifu.sv<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_lsu.sv<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_mprf.sv<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_tdu.sv<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_pipe_top.sv<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/core/pipeline/scr1_tracelog.sv<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/core/primitives<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/core/primitives/scr1_cg.sv<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/core/primitives/scr1_reset_cells.sv<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/core/scr1_clk_ctrl.sv<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/core/scr1_core_top.sv<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/core/scr1_dm.sv<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/core/scr1_dmi.sv<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/core/scr1_scu.sv<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/core/scr1_tapc.sv<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/core/scr1_tapc_shift_reg.sv<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/core/scr1_tapc_synchronizer.sv<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/includes<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/includes/scr1_ahb.svh<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/includes/scr1_arch_description.svh<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/includes/scr1_arch_types.svh<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/includes/scr1_csr.svh<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/includes/scr1_dm.svh<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/includes/scr1_hdu.svh<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/includes/scr1_ipic.svh<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/includes/scr1_memif.svh<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/includes/scr1_riscv_isa_decoding.svh<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/includes/scr1_scu.svh<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/includes/scr1_search_ms1.svh<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/includes/scr1_tapc.svh<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/includes/scr1_tdu.svh<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/includes/scr1_wb.svh<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/run_modemsim<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/top<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/top/scr1_dmem_ahb.sv<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/top/scr1_dmem_router.sv<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/top/scr1_dmem_wb.sv<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/top/scr1_dp_memory.sv<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/top/scr1_imem_ahb.sv<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/top/scr1_imem_router.sv<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/top/scr1_imem_wb.sv<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/top/scr1_mem_axi.sv<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/top/scr1_tcm.sv<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/top/scr1_timer.sv<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/top/scr1_top_ahb.sv<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/top/scr1_top_axi.sv<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/top/scr1_top_wb.sv<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/src/wb_top.files<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/synth<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/synth/Makefile<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/synth/run_synth<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore/scr1/synth/synth.tcl<br />
dinesha
Mon, 07 Jun 2021 15:59:05 +0100
https://opencores.org/websvn//websvn/revision?repname=yifive&path=%2F&rev=11
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syntacore interface change to wishbone
https://opencores.org/websvn//websvn/revision?repname=yifive&path=%2F&rev=10
<div><strong>Rev 10 - dinesha</strong> (10 file(s) modified)</div><div>syntacore interface change to wishbone</div>~ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_ipic.sv<br />~ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_csr.sv<br />~ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_exu.sv<br />~ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_idu.sv<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/src/includes/scr1_wb.svh<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/src/run_modemsim<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/src/top/scr1_dmem_wb.sv<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/src/top/scr1_imem_wb.sv<br />~ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/src/top/scr1_top_wb.sv<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/src/wb_top.files<br />
dinesha
Mon, 07 Jun 2021 15:44:20 +0100
https://opencores.org/websvn//websvn/revision?repname=yifive&path=%2F&rev=10
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syntacore added
https://opencores.org/websvn//websvn/revision?repname=yifive&path=%2F&rev=9
<div><strong>Rev 9 - dinesha</strong> (4 file(s) modified)</div><div>syntacore added</div>~ /yifive/trunk/caravel_yifive/openlane/Makefile<br />+ /yifive/trunk/caravel_yifive/openlane/syntacore<br />+ /yifive/trunk/caravel_yifive/openlane/syntacore/config.tcl<br />+ /yifive/trunk/caravel_yifive/openlane/syntacore/pin_order.cfg<br />
dinesha
Sun, 06 Jun 2021 15:40:02 +0100
https://opencores.org/websvn//websvn/revision?repname=yifive&path=%2F&rev=9
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synthesis script update
https://opencores.org/websvn//websvn/revision?repname=yifive&path=%2F&rev=8
<div><strong>Rev 8 - dinesha</strong> (1 file(s) modified)</div><div>synthesis script update</div>~ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/synth/synth.tcl<br />
dinesha
Sun, 06 Jun 2021 14:55:15 +0100
https://opencores.org/websvn//websvn/revision?repname=yifive&path=%2F&rev=8
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synth script clean up
https://opencores.org/websvn//websvn/revision?repname=yifive&path=%2F&rev=7
<div><strong>Rev 7 - dinesha</strong> (2 file(s) modified)</div><div>synth script clean up</div>~ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/synth/Makefile<br />~ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/synth/synth.tcl<br />
dinesha
Sun, 06 Jun 2021 14:48:25 +0100
https://opencores.org/websvn//websvn/revision?repname=yifive&path=%2F&rev=7
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first yosys synthesisizable rtl
https://opencores.org/websvn//websvn/revision?repname=yifive&path=%2F&rev=6
<div><strong>Rev 6 - dinesha</strong> (18 file(s) modified)</div><div>first yosys synthesisizable rtl</div>- /yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/src/axi_tb.files<br />~ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_ipic.sv<br />~ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_csr.sv<br />~ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_ialu.sv<br />~ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_idu.sv<br />~ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_ifu.sv<br />~ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/src/core/pipeline/scr1_pipe_tdu.sv<br />~ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/src/core/scr1_dm.sv<br />~ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/src/core/scr1_scu.sv<br />~ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/src/includes/scr1_arch_description.svh<br />~ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/src/includes/scr1_hdu.svh<br />~ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/src/includes/scr1_search_ms1.svh<br />~ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/src/top/scr1_dmem_ahb.sv<br />~ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/src/top/scr1_mem_axi.sv<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/synth<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/synth/Makefile<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/synth/run_synth<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/synth/synth.tcl<br />
dinesha
Sun, 06 Jun 2021 14:45:00 +0100
https://opencores.org/websvn//websvn/revision?repname=yifive&path=%2F&rev=6
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Webstone interface update
https://opencores.org/websvn//websvn/revision?repname=yifive&path=%2F&rev=5
<div><strong>Rev 5 - dinesha</strong> (3 file(s) modified)</div><div>Webstone interface update</div>~ /yifive/trunk/caravel_yifive/verilog/rtl/lib/wb_crossbar.v<br />~ /yifive/trunk/caravel_yifive/verilog/rtl/lib/wb_interface.v<br />+ /yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/src/top/scr1_top_wb.sv<br />
dinesha
Sun, 06 Jun 2021 09:59:50 +0100
https://opencores.org/websvn//websvn/revision?repname=yifive&path=%2F&rev=5
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Removed Git igonore command file
https://opencores.org/websvn//websvn/revision?repname=yifive&path=%2F&rev=4
<div><strong>Rev 4 - dinesha</strong> (2 file(s) modified)</div><div>Removed Git igonore command file</div>- /yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/.gitignore<br />- /yifive/trunk/caravel_yifive/verilog/rtl/syntacore_scr1/.gitmodules<br />
dinesha
Sun, 06 Jun 2021 09:29:17 +0100
https://opencores.org/websvn//websvn/revision?repname=yifive&path=%2F&rev=4
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