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https://opencores.org/ocsvn/c16/c16/trunk
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c16
WebSVN RSS feed - c16
https://opencores.org/websvn//websvn/listing?repname=c16&path=%2Fc16%2Ftrunk%2Fvhdl%2F&
Mon, 28 Sep 2026 03:44:42 +0100
FeedCreator 1.7.2
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New directory structure.
https://opencores.org/websvn//websvn/revision?repname=c16&path=%2Fc16%2Ftrunk%2Fvhdl%2F&rev=26
<div><strong>Rev 26 - root</strong> (8 file(s) modified)</div><div>New directory structure.</div>- /branches<br />+ /c16<br />+ /c16/branches<br />+ /c16/tags<br />+ /c16/trunk<br />+ /c16/web_uploads<br />- /tags<br />- /trunk<br />
root
Mon, 09 Mar 2009 19:33:21 +0100
https://opencores.org/websvn//websvn/revision?repname=c16&path=%2Fc16%2Ftrunk%2Fvhdl%2F&rev=26
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XOR bug fixed
https://opencores.org/websvn//websvn/revision?repname=c16&path=%2Ftrunk%2Fvhdl%2F&rev=25
<div><strong>Rev 25 - jsauermann</strong> (1 file(s) modified)</div><div>XOR bug fixed</div>~ /trunk/vhdl/alu8.vhd<br />
jsauermann
Sun, 16 Apr 2006 12:45:15 +0100
https://opencores.org/websvn//websvn/revision?repname=c16&path=%2Ftrunk%2Fvhdl%2F&rev=25
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Fixed problem with wishbone wait-states
https://opencores.org/websvn//websvn/revision?repname=c16&path=%2Ftrunk%2Fvhdl%2F&rev=23
<div><strong>Rev 23 - jsauermann</strong> (1 file(s) modified)</div><div>Fixed problem with wishbone wait-states</div>~ /trunk/vhdl/cpu_engine.vhd<br />
jsauermann
Sun, 19 Jun 2005 15:27:44 +0100
https://opencores.org/websvn//websvn/revision?repname=c16&path=%2Ftrunk%2Fvhdl%2F&rev=23
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Changes for Xilinx Proj. Nav. 7.1.02i
https://opencores.org/websvn//websvn/revision?repname=c16&path=%2Ftrunk%2Fvhdl%2F&rev=21
<div><strong>Rev 21 - jsauermann</strong> (6 file(s) modified)</div><div>Changes for Xilinx Proj. Nav. 7.1.02i</div>~ /trunk/vhdl/board_cpu.bit<br />+ /trunk/vhdl/cpu16.ise<br />~ /trunk/vhdl/cpu_engine.vhd<br />~ /trunk/vhdl/memory.vhd<br />~ /trunk/vhdl/opcode_decoder.vhd<br />~ /trunk/vhdl/opcode_fetch.vhd<br />
jsauermann
Sun, 19 Jun 2005 10:07:47 +0100
https://opencores.org/websvn//websvn/revision?repname=c16&path=%2Ftrunk%2Fvhdl%2F&rev=21
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FPGA Pin desription added.
https://opencores.org/websvn//websvn/revision?repname=c16&path=%2Ftrunk%2Fvhdl%2F&rev=19
<div><strong>Rev 19 - jsauermann</strong> (1 file(s) modified)</div><div>FPGA Pin desription added.</div>~ /trunk/vhdl/board_cpu.ucf<br />
jsauermann
Sun, 05 Dec 2004 13:26:35 +0100
https://opencores.org/websvn//websvn/revision?repname=c16&path=%2Ftrunk%2Fvhdl%2F&rev=19
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Assert ENABLE_INT and DISABLE_INT only in M1.
Thanks to Riccardo Cerulli-Irelly.
Requires ...
https://opencores.org/websvn//websvn/revision?repname=c16&path=%2Ftrunk%2Fvhdl%2F&rev=18
<div><strong>Rev 18 - jsauermann</strong> (1 file(s) modified)</div><div>Assert ENABLE_INT and DISABLE_INT only in M1.<br />
Thanks to Riccardo Cerulli-Irelly.<br />
Requires ...</div>~ /trunk/vhdl/board_cpu.bit<br />
jsauermann
Sun, 08 Feb 2004 14:21:00 +0100
https://opencores.org/websvn//websvn/revision?repname=c16&path=%2Ftrunk%2Fvhdl%2F&rev=18
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Assert ENABLE_INT and DISABLE_INT only in M1.
Thanks to Riccardo Cerulli-Irelly.
Requires ...
https://opencores.org/websvn//websvn/revision?repname=c16&path=%2Ftrunk%2Fvhdl%2F&rev=17
<div><strong>Rev 17 - jsauermann</strong> (1 file(s) modified)</div><div>Assert ENABLE_INT and DISABLE_INT only in M1.<br />
Thanks to Riccardo Cerulli-Irelly.<br />
Requires ...</div>~ /trunk/vhdl/opcode_decoder.vhd<br />
jsauermann
Sun, 08 Feb 2004 14:13:29 +0100
https://opencores.org/websvn//websvn/revision?repname=c16&path=%2Ftrunk%2Fvhdl%2F&rev=17
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sample ucf file
https://opencores.org/websvn//websvn/revision?repname=c16&path=%2Ftrunk%2Fvhdl%2F&rev=15
<div><strong>Rev 15 - jsauermann</strong> (1 file(s) modified)</div><div>sample ucf file</div>+ /trunk/vhdl/board_cpu.ucf<br />
jsauermann
Wed, 31 Dec 2003 11:03:31 +0100
https://opencores.org/websvn//websvn/revision?repname=c16&path=%2Ftrunk%2Fvhdl%2F&rev=15
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Made cpu_engine WISHBONE compliant.
(Somebody please validate it).
https://opencores.org/websvn//websvn/revision?repname=c16&path=%2Ftrunk%2Fvhdl%2F&rev=9
<div><strong>Rev 9 - jsauermann</strong> (22 file(s) modified)</div><div>Made cpu_engine WISHBONE compliant.<br />
(Somebody please validate it).</div>~ /trunk/vhdl/BaudGen.vhd<br />~ /trunk/vhdl/bin_to_7segment.vhd<br />~ /trunk/vhdl/board_cpu.bit<br />~ /trunk/vhdl/Board_cpu.vhd<br />~ /trunk/vhdl/cpu.vhd<br />~ /trunk/vhdl/cpu16.npl<br />~ /trunk/vhdl/cpu_engine.vhd<br />~ /trunk/vhdl/cpu_pack.vhd<br />~ /trunk/vhdl/cpu_test.vhd<br />~ /trunk/vhdl/data_core.vhd<br />~ /trunk/vhdl/ds1722.vhd<br />~ /trunk/vhdl/input_output.vhd<br />~ /trunk/vhdl/mem_content.vhd<br />~ /trunk/vhdl/opcode_decoder.vhd<br />~ /trunk/vhdl/opcode_fetch.vhd<br />~ /trunk/vhdl/select_yy.vhd<br />~ /trunk/vhdl/temperature.vhd<br />~ /trunk/vhdl/test.vhd<br />~ /trunk/vhdl/uart.vhd<br />~ /trunk/vhdl/uart._baudgen.vhd<br />~ /trunk/vhdl/uart_rx.vhd<br />~ /trunk/vhdl/uart_tx.vhd<br />
jsauermann
Sun, 12 Oct 2003 16:50:29 +0100
https://opencores.org/websvn//websvn/revision?repname=c16&path=%2Ftrunk%2Fvhdl%2F&rev=9
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Handle auto variable declarations in compound statements properly
https://opencores.org/websvn//websvn/revision?repname=c16&path=%2Ftrunk%2Fvhdl%2F&rev=7
<div><strong>Rev 7 - jsauermann</strong> (33 file(s) modified)</div><div>Handle auto variable declarations in compound statements properly</div>~ /trunk/asm/assembler.exe<br />~ /trunk/asm/Makefile<br />~ /trunk/compiler/Backend.cc<br />~ /trunk/compiler/Backend.hh<br />~ /trunk/compiler/cc80.exe<br />~ /trunk/compiler/Makefile<br />~ /trunk/compiler/Name.cc<br />~ /trunk/compiler/Name.hh<br />~ /trunk/compiler/Node.cc<br />~ /trunk/compiler/Statement.cc<br />~ /trunk/loader.asm<br />~ /trunk/loader.bin<br />~ /trunk/loader.ihx<br />~ /trunk/loader.lst<br />~ /trunk/loader.sym<br />~ /trunk/Makefile<br />~ /trunk/memory/Makefile<br />~ /trunk/rtos.asm<br />~ /trunk/rtos.bin<br />~ /trunk/rtos.ihx<br />~ /trunk/rtos.lst<br />~ /trunk/rtos.sym<br />~ /trunk/sim/Makefile<br />~ /trunk/sim/simulate.cc<br />~ /trunk/sim/simulate.exe<br />~ /trunk/test.asm<br />~ /trunk/test.bin<br />~ /trunk/test.ihx<br />~ /trunk/test.lst<br />~ /trunk/test.sym<br />~ /trunk/vhdl/board_cpu.bit<br />~ /trunk/vhdl/cpu16.npl<br />~ /trunk/vhdl/mem_content.vhd<br />
jsauermann
Sat, 04 Oct 2003 14:40:53 +0100
https://opencores.org/websvn//websvn/revision?repname=c16&path=%2Ftrunk%2Fvhdl%2F&rev=7
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no message
https://opencores.org/websvn//websvn/revision?repname=c16&path=%2Ftrunk%2Fvhdl%2F&rev=2
<div><strong>Rev 2 - jsauermann</strong> (83 file(s) modified)</div><div>no message</div>+ /trunk/asm<br />+ /trunk/asm/assembler.bison<br />+ /trunk/asm/assembler.cc<br />+ /trunk/asm/assembler.exe<br />+ /trunk/asm/assembler.flex<br />+ /trunk/asm/Makefile<br />+ /trunk/bin2array.cc<br />+ /trunk/bin2array.exe<br />+ /trunk/compiler<br />+ /trunk/compiler/ansic.bison<br />+ /trunk/compiler/ansic.flex<br />+ /trunk/compiler/Backend.cc<br />+ /trunk/compiler/Backend.hh<br />+ /trunk/compiler/cc80.cc<br />+ /trunk/compiler/cc80.exe<br />+ /trunk/compiler/Expression.cc<br />+ /trunk/compiler/List.hh<br />+ /trunk/compiler/Makefile<br />+ /trunk/compiler/Makefile~<br />+ /trunk/compiler/Name.cc<br />+ /trunk/compiler/Name.hh<br />+ /trunk/compiler/Node.cc<br />+ /trunk/compiler/Node.hh<br />+ /trunk/compiler/Statement.cc<br />+ /trunk/doc<br />+ /trunk/doc/c16.pdf<br />+ /trunk/doc/cpu.mif<br />+ /trunk/loader.asm<br />+ /trunk/loader.bin<br />+ /trunk/loader.c<br />+ /trunk/loader.ihx<br />+ /trunk/loader.lst<br />+ /trunk/loader.sym<br />+ /trunk/Makefile<br />+ /trunk/memory<br />+ /trunk/memory/Makefile<br />+ /trunk/memory/makemem.cc<br />+ /trunk/memory/makemem.exe<br />+ /trunk/rtos.asm<br />+ /trunk/rtos.bin<br />+ /trunk/rtos.c<br />+ /trunk/rtos.ihx<br />+ /trunk/rtos.lst<br />+ /trunk/rtos.sym<br />+ /trunk/sim<br />+ /trunk/sim/Makefile<br />+ /trunk/sim/simulate.cc<br />+ /trunk/sim/simulate.exe<br />+ /trunk/test.asm<br />+ /trunk/test.bin<br />+ /trunk/test.c<br />+ /trunk/test.ihx<br />+ /trunk/test.lst<br />+ /trunk/test.sym<br />+ /trunk/test.txt<br />+ /trunk/tty.cc<br />+ /trunk/tty.exe<br />+ /trunk/vhdl<br />+ /trunk/vhdl/alu8.vhd<br />+ /trunk/vhdl/BaudGen.vhd<br />+ /trunk/vhdl/bin_to_7segment.vhd<br />+ /trunk/vhdl/board_cpu.bit<br />+ /trunk/vhdl/Board_cpu.vhd<br />+ /trunk/vhdl/cpu.vhd<br />+ /trunk/vhdl/cpu16.npl<br />+ /trunk/vhdl/cpu_engine.vhd<br />+ /trunk/vhdl/cpu_pack.vhd<br />+ /trunk/vhdl/cpu_test.vhd<br />+ /trunk/vhdl/data_core.vhd<br />+ /trunk/vhdl/ds1722.vhd<br />+ /trunk/vhdl/input_output.vhd<br />+ /trunk/vhdl/memory.vhd<br />+ /trunk/vhdl/mem_content.vhd<br />+ /trunk/vhdl/opcode_decoder.vhd<br />+ /trunk/vhdl/opcode_fetch.vhd<br />+ /trunk/vhdl/select_yy.vhd<br />+ /trunk/vhdl/temperature.vhd<br />+ /trunk/vhdl/test.tbw<br />+ /trunk/vhdl/test.vhd<br />+ /trunk/vhdl/uart.vhd<br />+ /trunk/vhdl/uart._baudgen.vhd<br />+ /trunk/vhdl/uart_rx.vhd<br />+ /trunk/vhdl/uart_tx.vhd<br />
jsauermann
Tue, 30 Sep 2003 17:58:06 +0100
https://opencores.org/websvn//websvn/revision?repname=c16&path=%2Ftrunk%2Fvhdl%2F&rev=2
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