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embedded_risc WebSVN RSS feed - embedded_risc https://opencores.org/websvn//websvn/listing?repname=embedded_risc&path=%2Fembedded_risc%2Ftrunk%2F& Tue, 14 Apr 2026 13:59:07 +0100 FeedCreator 1.7.2 New directory structure. https://opencores.org/websvn//websvn/revision?repname=embedded_risc&path=%2Fembedded_risc%2Ftrunk%2F&rev=27 <div><strong>Rev 27 - root</strong> (8 file(s) modified)</div><div>New directory structure.</div>- /branches<br />+ /embedded_risc<br />+ /embedded_risc/branches<br />+ /embedded_risc/tags<br />+ /embedded_risc/trunk<br />+ /embedded_risc/web_uploads<br />- /tags<br />- /trunk<br /> root Mon, 09 Mar 2009 21:03:15 +0100 https://opencores.org/websvn//websvn/revision?repname=embedded_risc&path=%2Fembedded_risc%2Ftrunk%2F&rev=27 no message https://opencores.org/websvn//websvn/revision?repname=embedded_risc&path=%2Ftrunk%2F&rev=26 <div><strong>Rev 26 - hosseinamidi</strong> (52 file(s) modified)</div><div>no message</div>+ /trunk/Machine_Language<br />+ /trunk/Machine_Language/program.txt<br />+ /trunk/Test_Bench_Verilog<br />+ /trunk/Test_Bench_Verilog/Top_level_tb.tf<br />+ /trunk/Verilog<br />+ /trunk/Verilog/ACC.V<br />+ /trunk/Verilog/ALU.V<br />+ /trunk/Verilog/bus_arbiter.v<br />+ /trunk/Verilog/cmd_ack.v<br />+ /trunk/Verilog/cmd_decoder.v<br />+ /trunk/Verilog/cmd_detector.v<br />+ /trunk/Verilog/cmd_generator.v<br />+ /trunk/Verilog/cmd_internal_reg.v<br />+ /trunk/Verilog/command_if.v<br />+ /trunk/Verilog/CONTROL.V<br />+ /trunk/Verilog/data_cache_way0.v<br />+ /trunk/Verilog/data_cache_way1.v<br />+ /trunk/Verilog/data_cache_way2.v<br />+ /trunk/Verilog/data_cache_way3.v<br />+ /trunk/Verilog/data_in_reg.v<br />+ /trunk/Verilog/data_port.v<br />+ /trunk/Verilog/dma_cntrl.v<br />+ /trunk/Verilog/dma_fifo.v<br />+ /trunk/Verilog/dma_internal_reg.v<br />+ /trunk/Verilog/flash_ctrl.v<br />+ /trunk/Verilog/fsm.v<br />+ /trunk/Verilog/instruction_cache_way0.v<br />+ /trunk/Verilog/instruction_cache_way1.v<br />+ /trunk/Verilog/instruction_cache_way2.v<br />+ /trunk/Verilog/instruction_cache_way3.v<br />+ /trunk/Verilog/IR.V<br />+ /trunk/Verilog/k9f1g08u0m.v<br />+ /trunk/Verilog/lru_data_cache.v<br />+ /trunk/Verilog/lru_instruction_cache.v<br />+ /trunk/Verilog/MEM.V<br />+ /trunk/Verilog/MUX12.V<br />+ /trunk/Verilog/MUX16.V<br />+ /trunk/Verilog/oe_generator.v<br />+ /trunk/Verilog/parameter.v<br />+ /trunk/Verilog/PC.V<br />+ /trunk/Verilog/ras_cas_delay.v<br />+ /trunk/Verilog/ref_ack.v<br />+ /trunk/Verilog/ref_timer.v<br />+ /trunk/Verilog/risc.v<br />+ /trunk/Verilog/sdram.v<br />+ /trunk/Verilog/sdramctrl_rtl.v<br />+ /trunk/Verilog/sdram_cntrl.v<br />+ /trunk/Verilog/sdram_mux.v<br />+ /trunk/Verilog/sdram_port.v<br />+ /trunk/Verilog/soc.v<br />+ /trunk/Verilog/timer.v<br />+ /trunk/Verilog/uart.v<br /> hosseinamidi Wed, 05 Jun 2002 22:38:44 +0100 https://opencores.org/websvn//websvn/revision?repname=embedded_risc&path=%2Ftrunk%2F&rev=26 no message https://opencores.org/websvn//websvn/revision?repname=embedded_risc&path=%2Ftrunk%2F&rev=25 <div><strong>Rev 25 - hosseinamidi</strong> (1 file(s) modified)</div><div>no message</div>+ /trunk/SOC_Design.pdf<br /> hosseinamidi Wed, 05 Jun 2002 22:16:34 +0100 https://opencores.org/websvn//websvn/revision?repname=embedded_risc&path=%2Ftrunk%2F&rev=25 no message https://opencores.org/websvn//websvn/revision?repname=embedded_risc&path=%2Ftrunk%2F&rev=24 <div><strong>Rev 24 - hosseinamidi</strong> (2 file(s) modified)</div><div>no message</div>- /trunk/cvs.pdf<br />- /trunk/SOC_Block_diagram.pdf<br /> hosseinamidi Wed, 05 Jun 2002 21:40:13 +0100 https://opencores.org/websvn//websvn/revision?repname=embedded_risc&path=%2Ftrunk%2F&rev=24 no message https://opencores.org/websvn//websvn/revision?repname=embedded_risc&path=%2Ftrunk%2F&rev=23 <div><strong>Rev 23 - hosseinamidi</strong> (2 file(s) modified)</div><div>no message</div>- /trunk/sdram_controller.pdf<br />~ /trunk/SOC_Block_diagram.pdf<br /> hosseinamidi Wed, 05 Jun 2002 21:30:05 +0100 https://opencores.org/websvn//websvn/revision?repname=embedded_risc&path=%2Ftrunk%2F&rev=23 no message https://opencores.org/websvn//websvn/revision?repname=embedded_risc&path=%2Ftrunk%2F&rev=22 <div><strong>Rev 22 - hosseinamidi</strong> (1 file(s) modified)</div><div>no message</div>- /trunk/empty_file.txt<br /> hosseinamidi Mon, 06 May 2002 17:21:26 +0100 https://opencores.org/websvn//websvn/revision?repname=embedded_risc&path=%2Ftrunk%2F&rev=22 This commit was generated by cvs2svn to compensate for changes ... https://opencores.org/websvn//websvn/revision?repname=embedded_risc&path=%2Ftrunk%2F&rev=20 <div><strong>Rev 20 - hosseinamidi</strong> (1 file(s) modified)</div><div>This commit was generated by cvs2svn to compensate for changes ...</div>+ /trunk/empty_file.txt<br /> hosseinamidi Mon, 06 May 2002 17:16:55 +0100 https://opencores.org/websvn//websvn/revision?repname=embedded_risc&path=%2Ftrunk%2F&rev=20 no message https://opencores.org/websvn//websvn/revision?repname=embedded_risc&path=%2Ftrunk%2F&rev=18 <div><strong>Rev 18 - hosseinamidi</strong> (3 file(s) modified)</div><div>no message</div>+ /trunk/cvs.pdf<br />+ /trunk/sdram_controller.pdf<br />+ /trunk/SOC_Block_diagram.pdf<br /> hosseinamidi Sun, 05 May 2002 07:24:28 +0100 https://opencores.org/websvn//websvn/revision?repname=embedded_risc&path=%2Ftrunk%2F&rev=18 no message https://opencores.org/websvn//websvn/revision?repname=embedded_risc&path=%2Ftrunk%2F&rev=17 <div><strong>Rev 17 - hosseinamidi</strong> (1 file(s) modified)</div><div>no message</div>- /trunk/embedded_risc<br /> hosseinamidi Sun, 05 May 2002 07:15:27 +0100 https://opencores.org/websvn//websvn/revision?repname=embedded_risc&path=%2Ftrunk%2F&rev=17 no message https://opencores.org/websvn//websvn/revision?repname=embedded_risc&path=%2Ftrunk%2F&rev=15 <div><strong>Rev 15 - hosseinamidi</strong> (9 file(s) modified)</div><div>no message</div>- /trunk/cvs.pdf<br />- /trunk/Entries<br />- /trunk/Repository<br />- /trunk/RISC_uProcessor.vsd<br />- /trunk/Root<br />- /trunk/sdram_controller.pdf<br />- /trunk/sdram_controller.vsd<br />- /trunk/SOC_Block_diagram.pdf<br />- /trunk/SOC_Block_diagram.vsd<br /> hosseinamidi Sun, 05 May 2002 06:42:47 +0100 https://opencores.org/websvn//websvn/revision?repname=embedded_risc&path=%2Ftrunk%2F&rev=15 This commit was generated by cvs2svn to compensate for changes ... https://opencores.org/websvn//websvn/revision?repname=embedded_risc&path=%2Ftrunk%2F&rev=14 <div><strong>Rev 14 - hosseinamidi</strong> (3 file(s) modified)</div><div>This commit was generated by cvs2svn to compensate for changes ...</div>+ /trunk/RISC_uProcessor.vsd<br />+ /trunk/sdram_controller.vsd<br />+ /trunk/SOC_Block_diagram.vsd<br /> hosseinamidi Sun, 05 May 2002 06:27:17 +0100 https://opencores.org/websvn//websvn/revision?repname=embedded_risc&path=%2Ftrunk%2F&rev=14 This commit was generated by cvs2svn to compensate for changes ... https://opencores.org/websvn//websvn/revision?repname=embedded_risc&path=%2Ftrunk%2F&rev=12 <div><strong>Rev 12 - hosseinamidi</strong> (7 file(s) modified)</div><div>This commit was generated by cvs2svn to compensate for changes ...</div>+ /trunk/embedded_risc<br />+ /trunk/embedded_risc/cvs.pdf<br />+ /trunk/embedded_risc/Entries<br />+ /trunk/embedded_risc/Repository<br />+ /trunk/embedded_risc/Root<br />+ /trunk/embedded_risc/sdram_controller.pdf<br />+ /trunk/embedded_risc/SOC_Block_diagram.pdf<br /> hosseinamidi Sun, 05 May 2002 06:14:46 +0100 https://opencores.org/websvn//websvn/revision?repname=embedded_risc&path=%2Ftrunk%2F&rev=12 This commit was generated by cvs2svn to compensate for changes ... https://opencores.org/websvn//websvn/revision?repname=embedded_risc&path=%2Ftrunk%2F&rev=9 <div><strong>Rev 9 - hosseinamidi</strong> (3 file(s) modified)</div><div>This commit was generated by cvs2svn to compensate for changes ...</div>+ /trunk/Entries<br />+ /trunk/Repository<br />+ /trunk/Root<br /> hosseinamidi Sun, 05 May 2002 05:27:04 +0100 https://opencores.org/websvn//websvn/revision?repname=embedded_risc&path=%2Ftrunk%2F&rev=9 no message https://opencores.org/websvn//websvn/revision?repname=embedded_risc&path=%2Ftrunk%2F&rev=6 <div><strong>Rev 6 - hosseinamidi</strong> (1 file(s) modified)</div><div>no message</div>+ /trunk/sdram_controller.pdf<br /> hosseinamidi Wed, 24 Apr 2002 06:12:00 +0100 https://opencores.org/websvn//websvn/revision?repname=embedded_risc&path=%2Ftrunk%2F&rev=6 This commit was generated by cvs2svn to compensate for changes ... https://opencores.org/websvn//websvn/revision?repname=embedded_risc&path=%2Ftrunk%2F&rev=5 <div><strong>Rev 5 - hosseinamidi</strong> (1 file(s) modified)</div><div>This commit was generated by cvs2svn to compensate for changes ...</div>+ /trunk/SOC_Block_diagram.pdf<br /> hosseinamidi Mon, 22 Apr 2002 07:48:19 +0100 https://opencores.org/websvn//websvn/revision?repname=embedded_risc&path=%2Ftrunk%2F&rev=5 This commit was generated by cvs2svn to compensate for changes ... https://opencores.org/websvn//websvn/revision?repname=embedded_risc&path=%2Ftrunk%2F&rev=3 <div><strong>Rev 3 - hosseinamidi</strong> (1 file(s) modified)</div><div>This commit was generated by cvs2svn to compensate for changes ...</div>+ /trunk/cvs.pdf<br /> hosseinamidi Mon, 22 Apr 2002 06:24:43 +0100 https://opencores.org/websvn//websvn/revision?repname=embedded_risc&path=%2Ftrunk%2F&rev=3 Standard project directories initialized by cvs2svn. https://opencores.org/websvn//websvn/revision?repname=embedded_risc&path=%2Ftrunk%2F&rev=1 <div><strong>Rev 1 - </strong> (3 file(s) modified)</div><div>Standard project directories initialized by cvs2svn.</div>+ /branches<br />+ /tags<br />+ /trunk<br /> Mon, 22 Apr 2002 06:24:43 +0100 https://opencores.org/websvn//websvn/revision?repname=embedded_risc&path=%2Ftrunk%2F&rev=1

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