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ion WebSVN RSS feed - ion https://opencores.org/websvn//websvn/listing?repname=ion&path=%2Fion%2Ftrunk%2Fvhdl%2Ftb%2F& Fri, 19 Jun 2026 03:44:09 +0100 FeedCreator 1.7.2 Extracted COP0 logic to separate module within CPU. Preliminary step for ... https://opencores.org/websvn//websvn/revision?repname=ion&path=%2Fion%2Ftrunk%2Fvhdl%2Ftb%2F&rev=251 <div><strong>Rev 251 - ja_rd</strong> (4 file(s) modified)</div><div>Extracted COP0 logic to separate module within CPU.<br /> Preliminary step for ...</div>~ /ion/trunk/sim/mips_tb.do<br />~ /ion/trunk/vhdl/mips_cpu.vhdl<br />~ /ion/trunk/vhdl/mips_pkg.vhdl<br />~ /ion/trunk/vhdl/tb/mips_tb_pkg.vhdl<br /> ja_rd Tue, 14 Jan 2014 18:32:53 +0100 https://opencores.org/websvn//websvn/revision?repname=ion&path=%2Fion%2Ftrunk%2Fvhdl%2Ftb%2F&rev=251 Updated simulation and synthesis object code packages with latest build ... https://opencores.org/websvn//websvn/revision?repname=ion&path=%2Fion%2Ftrunk%2Fvhdl%2Ftb%2F&rev=241 <div><strong>Rev 241 - ja_rd</strong> (2 file(s) modified)</div><div>Updated simulation and synthesis object code packages with latest build ...</div>~ /ion/trunk/vhdl/SoC/bootstrap_code_pkg.vhdl<br />~ /ion/trunk/vhdl/tb/sim_params_pkg.vhdl<br /> ja_rd Thu, 15 Nov 2012 12:17:11 +0100 https://opencores.org/websvn//websvn/revision?repname=ion&path=%2Fion%2Ftrunk%2Fvhdl%2Ftb%2F&rev=241 Fixed test bench to work with latest modifications of SoC https://opencores.org/websvn//websvn/revision?repname=ion&path=%2Fion%2Ftrunk%2Fvhdl%2Ftb%2F&rev=237 <div><strong>Rev 237 - ja_rd</strong> (1 file(s) modified)</div><div>Fixed test bench to work with latest modifications of SoC</div>~ /ion/trunk/vhdl/tb/mips_tb.vhdl<br /> ja_rd Thu, 15 Nov 2012 08:09:12 +0100 https://opencores.org/websvn//websvn/revision?repname=ion&path=%2Fion%2Ftrunk%2Fvhdl%2Ftb%2F&rev=237 Updated demo and test bench to use new SoC entity. https://opencores.org/websvn//websvn/revision?repname=ion&path=%2Fion%2Ftrunk%2Fvhdl%2Ftb%2F&rev=226 <div><strong>Rev 226 - ja_rd</strong> (6 file(s) modified)</div><div>Updated demo and test bench to use new SoC entity.</div>~ /ion/trunk/vhdl/demo/c2sb_demo.vhdl<br />- /ion/trunk/vhdl/demo/mips_mpu.vhdl<br />+ /ion/trunk/vhdl/SoC/bootstrap_code_pkg.vhdl<br />~ /ion/trunk/vhdl/tb/mips_tb.vhdl<br />~ /ion/trunk/vhdl/tb/mips_tb_pkg.vhdl<br />~ /ion/trunk/vhdl/tb/sim_params_pkg.vhdl<br /> ja_rd Wed, 20 Jun 2012 06:41:09 +0100 https://opencores.org/websvn//websvn/revision?repname=ion&path=%2Fion%2Ftrunk%2Fvhdl%2Ftb%2F&rev=226 Included a simulated block of I/O regs in the test ... https://opencores.org/websvn//websvn/revision?repname=ion&path=%2Fion%2Ftrunk%2Fvhdl%2Ftb%2F&rev=211 <div><strong>Rev 211 - ja_rd</strong> (1 file(s) modified)</div><div>Included a simulated block of I/O regs in the test ...</div>~ /ion/trunk/vhdl/tb/mips_tb.vhdl<br /> ja_rd Sat, 09 Jun 2012 07:49:43 +0100 https://opencores.org/websvn//websvn/revision?repname=ion&path=%2Fion%2Ftrunk%2Fvhdl%2Ftb%2F&rev=211 Simulation memories now modelled with shared variables and not signals. This ... https://opencores.org/websvn//websvn/revision?repname=ion&path=%2Fion%2Ftrunk%2Fvhdl%2Ftb%2F&rev=207 <div><strong>Rev 207 - ja_rd</strong> (1 file(s) modified)</div><div>Simulation memories now modelled with shared variables and not signals.<br /> This ...</div>~ /ion/trunk/vhdl/tb/mips_tb.vhdl<br /> ja_rd Sun, 04 Sep 2011 12:04:59 +0100 https://opencores.org/websvn//websvn/revision?repname=ion&path=%2Fion%2Ftrunk%2Fvhdl%2Ftb%2F&rev=207 Fixed SygnalSpy function calls for compatibility with older versions of ... https://opencores.org/websvn//websvn/revision?repname=ion&path=%2Fion%2Ftrunk%2Fvhdl%2Ftb%2F&rev=206 <div><strong>Rev 206 - ja_rd</strong> (1 file(s) modified)</div><div>Fixed SygnalSpy function calls for compatibility with older versions of ...</div>~ /ion/trunk/vhdl/tb/mips_tb_pkg.vhdl<br /> ja_rd Sun, 04 Sep 2011 12:03:04 +0100 https://opencores.org/websvn//websvn/revision?repname=ion&path=%2Fion%2Ftrunk%2Fvhdl%2Ftb%2F&rev=206 Fixed bug in test bench interface to CPU https://opencores.org/websvn//websvn/revision?repname=ion&path=%2Fion%2Ftrunk%2Fvhdl%2Ftb%2F&rev=205 <div><strong>Rev 205 - ja_rd</strong> (1 file(s) modified)</div><div>Fixed bug in test bench interface to CPU</div>~ /ion/trunk/vhdl/tb/mips_tb.vhdl<br /> ja_rd Sun, 14 Aug 2011 13:24:39 +0100 https://opencores.org/websvn//websvn/revision?repname=ion&path=%2Fion%2Ftrunk%2Fvhdl%2Ftb%2F&rev=205 CPU interrupt input changed to 8-bit vector Other modules changed accordingly Interrupts ... https://opencores.org/websvn//websvn/revision?repname=ion&path=%2Fion%2Ftrunk%2Fvhdl%2Ftb%2F&rev=200 <div><strong>Rev 200 - ja_rd</strong> (4 file(s) modified)</div><div>CPU interrupt input changed to 8-bit vector<br /> Other modules changed accordingly<br /> Interrupts ...</div>~ /ion/trunk/vhdl/demo/c2sb_demo.vhdl<br />~ /ion/trunk/vhdl/demo/mips_mpu.vhdl<br />~ /ion/trunk/vhdl/mips_cpu.vhdl<br />~ /ion/trunk/vhdl/tb/mips_tb.vhdl<br /> ja_rd Sun, 31 Jul 2011 13:22:58 +0100 https://opencores.org/websvn//websvn/revision?repname=ion&path=%2Fion%2Ftrunk%2Fvhdl%2Ftb%2F&rev=200 Removed deprecated files from old TB version https://opencores.org/websvn//websvn/revision?repname=ion&path=%2Fion%2Ftrunk%2Fvhdl%2Ftb%2F&rev=194 <div><strong>Rev 194 - ja_rd</strong> (3 file(s) modified)</div><div>Removed deprecated files from old TB version</div>- /ion/trunk/sim/mips_tb2.do<br />- /ion/trunk/sim/mips_tb2_wave.do<br />- /ion/trunk/vhdl/tb/mips_tb2.vhdl<br /> ja_rd Fri, 29 Jul 2011 21:36:26 +0100 https://opencores.org/websvn//websvn/revision?repname=ion&path=%2Fion%2Ftrunk%2Fvhdl%2Ftb%2F&rev=194 Major test bench reorganization: 1.- TB now uses same object code ... https://opencores.org/websvn//websvn/revision?repname=ion&path=%2Fion%2Ftrunk%2Fvhdl%2Ftb%2F&rev=193 <div><strong>Rev 193 - ja_rd</strong> (11 file(s) modified)</div><div>Major test bench reorganization:<br /> 1.- TB now uses same object code ...</div>+ /ion/trunk/sim/mips_tb.do<br />+ /ion/trunk/sim/mips_tb_wave.do<br />~ /ion/trunk/src/adventure/makefile<br />~ /ion/trunk/src/hello/makefile<br />~ /ion/trunk/src/memtest/makefile<br />~ /ion/trunk/src/opcodes/makefile<br />~ /ion/trunk/vhdl/demo/code_rom_pkg.vhdl<br />~ /ion/trunk/vhdl/demo/mips_mpu.vhdl<br />+ /ion/trunk/vhdl/tb/mips_tb.vhdl<br />~ /ion/trunk/vhdl/tb/mips_tb_pkg.vhdl<br />+ /ion/trunk/vhdl/tb/sim_params_pkg.vhdl<br /> ja_rd Fri, 29 Jul 2011 21:35:39 +0100 https://opencores.org/websvn//websvn/revision?repname=ion&path=%2Fion%2Ftrunk%2Fvhdl%2Ftb%2F&rev=193 removed file from TB directory which was committed by mistake https://opencores.org/websvn//websvn/revision?repname=ion&path=%2Fion%2Ftrunk%2Fvhdl%2Ftb%2F&rev=158 <div><strong>Rev 158 - ja_rd</strong> (1 file(s) modified)</div><div>removed file from TB directory which was committed by mistake</div>- /ion/trunk/vhdl/tb/mips_mpu.vhdl<br /> ja_rd Wed, 08 Jun 2011 06:06:44 +0100 https://opencores.org/websvn//websvn/revision?repname=ion&path=%2Fion%2Ftrunk%2Fvhdl%2Ftb%2F&rev=158 Bug fix in the missing coprocesor exception. The CPU was ... https://opencores.org/websvn//websvn/revision?repname=ion&path=%2Fion%2Ftrunk%2Fvhdl%2Ftb%2F&rev=157 <div><strong>Rev 157 - ja_rd</strong> (2 file(s) modified)</div><div>Bug fix in the missing coprocesor exception. <br /> The CPU was ...</div>~ /ion/trunk/vhdl/mips_cpu.vhdl<br />~ /ion/trunk/vhdl/tb/mips_tb_pkg.vhdl<br /> ja_rd Mon, 06 Jun 2011 20:20:07 +0100 https://opencores.org/websvn//websvn/revision?repname=ion&path=%2Fion%2Ftrunk%2Fvhdl%2Ftb%2F&rev=157 Added R3000 compatible support for kernel/user state: - Implemented KU/IE plus ... https://opencores.org/websvn//websvn/revision?repname=ion&path=%2Fion%2Ftrunk%2Fvhdl%2Ftb%2F&rev=152 <div><strong>Rev 152 - ja_rd</strong> (6 file(s) modified)</div><div>Added R3000 compatible support for kernel/user state:<br /> - Implemented KU/IE plus ...</div>~ /ion/trunk/src/adventure/bootstrap.s<br />~ /ion/trunk/src/common/startup.s<br />~ /ion/trunk/src/memtest/memtest.s<br />~ /ion/trunk/src/opcodes/opcodes.s<br />~ /ion/trunk/tools/slite/src/slite.c<br />~ /ion/trunk/vhdl/tb/mips_tb_pkg.vhdl<br /> ja_rd Mon, 06 Jun 2011 10:59:29 +0100 https://opencores.org/websvn//websvn/revision?repname=ion&path=%2Fion%2Ftrunk%2Fvhdl%2Ftb%2F&rev=152 updated simulation &amp; synthesis pre-generated entities ('hello' code sample) https://opencores.org/websvn//websvn/revision?repname=ion&path=%2Fion%2Ftrunk%2Fvhdl%2Ftb%2F&rev=139 <div><strong>Rev 139 - ja_rd</strong> (1 file(s) modified)</div><div>updated simulation &amp; synthesis pre-generated entities<br /> ('hello' code sample)</div>+ /ion/trunk/vhdl/tb/mips_mpu.vhdl<br /> ja_rd Wed, 01 Jun 2011 13:11:20 +0100 https://opencores.org/websvn//websvn/revision?repname=ion&path=%2Fion%2Ftrunk%2Fvhdl%2Ftb%2F&rev=139 updated simulation &amp; synthesis pre-generated entities ('hello' code sample) https://opencores.org/websvn//websvn/revision?repname=ion&path=%2Fion%2Ftrunk%2Fvhdl%2Ftb%2F&rev=138 <div><strong>Rev 138 - ja_rd</strong> (2 file(s) modified)</div><div>updated simulation &amp; synthesis pre-generated entities<br /> ('hello' code sample)</div>~ /ion/trunk/vhdl/demo/mips_mpu.vhdl<br />~ /ion/trunk/vhdl/tb/mips_tb2.vhdl<br /> ja_rd Wed, 01 Jun 2011 13:10:52 +0100 https://opencores.org/websvn//websvn/revision?repname=ion&path=%2Fion%2Ftrunk%2Fvhdl%2Ftb%2F&rev=138 updated precompiled simulation testbench https://opencores.org/websvn//websvn/revision?repname=ion&path=%2Fion%2Ftrunk%2Fvhdl%2Ftb%2F&rev=128 <div><strong>Rev 128 - ja_rd</strong> (1 file(s) modified)</div><div>updated precompiled simulation testbench</div>~ /ion/trunk/vhdl/tb/mips_tb2.vhdl<br /> ja_rd Sun, 29 May 2011 15:10:55 +0100 https://opencores.org/websvn//websvn/revision?repname=ion&path=%2Fion%2Ftrunk%2Fvhdl%2Ftb%2F&rev=128 added SDRAM verilog simulation model https://opencores.org/websvn//websvn/revision?repname=ion&path=%2Fion%2Ftrunk%2Fvhdl%2Ftb%2F&rev=126 <div><strong>Rev 126 - ja_rd</strong> (2 file(s) modified)</div><div>added SDRAM verilog simulation model</div>+ /ion/trunk/vhdl/tb/models<br />+ /ion/trunk/vhdl/tb/models/mt48lc4m16a2.v<br /> ja_rd Sun, 29 May 2011 15:07:08 +0100 https://opencores.org/websvn//websvn/revision?repname=ion&path=%2Fion%2Ftrunk%2Fvhdl%2Ftb%2F&rev=126 Updated pre-generated simulation and synthesis demos https://opencores.org/websvn//websvn/revision?repname=ion&path=%2Fion%2Ftrunk%2Fvhdl%2Ftb%2F&rev=119 <div><strong>Rev 119 - ja_rd</strong> (2 file(s) modified)</div><div>Updated pre-generated simulation and synthesis demos</div>~ /ion/trunk/vhdl/demo/mips_mpu.vhdl<br />~ /ion/trunk/vhdl/tb/mips_tb2.vhdl<br /> ja_rd Mon, 04 Apr 2011 12:33:48 +0100 https://opencores.org/websvn//websvn/revision?repname=ion&path=%2Fion%2Ftrunk%2Fvhdl%2Ftb%2F&rev=119 Updated simulation package for compatibility to new cache https://opencores.org/websvn//websvn/revision?repname=ion&path=%2Fion%2Ftrunk%2Fvhdl%2Ftb%2F&rev=112 <div><strong>Rev 112 - ja_rd</strong> (1 file(s) modified)</div><div>Updated simulation package for compatibility to new cache</div>~ /ion/trunk/vhdl/tb/mips_tb_pkg.vhdl<br /> ja_rd Mon, 04 Apr 2011 07:49:56 +0100 https://opencores.org/websvn//websvn/revision?repname=ion&path=%2Fion%2Ftrunk%2Fvhdl%2Ftb%2F&rev=112
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