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https://opencores.org/ocsvn/mem_ctrl/mem_ctrl/trunk
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mem_ctrl
WebSVN RSS feed - mem_ctrl
https://opencores.org/websvn//websvn/listing?repname=mem_ctrl&path=%2Fmem_ctrl%2Ftrunk%2Frtl%2F&
Tue, 21 Apr 2026 05:32:57 +0100
FeedCreator 1.7.2
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New directory structure.
https://opencores.org/websvn//websvn/revision?repname=mem_ctrl&path=%2Fmem_ctrl%2Ftrunk%2Frtl%2F&rev=28
<div><strong>Rev 28 - root</strong> (8 file(s) modified)</div><div>New directory structure.</div>- /branches<br />+ /mem_ctrl<br />+ /mem_ctrl/branches<br />+ /mem_ctrl/tags<br />+ /mem_ctrl/trunk<br />+ /mem_ctrl/web_uploads<br />- /tags<br />- /trunk<br />
root
Tue, 10 Mar 2009 01:08:35 +0100
https://opencores.org/websvn//websvn/revision?repname=mem_ctrl&path=%2Fmem_ctrl%2Ftrunk%2Frtl%2F&rev=28
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Fixed several minor bugs, cleaned up the code further ...
https://opencores.org/websvn//websvn/revision?repname=mem_ctrl&path=%2Ftrunk%2Frtl%2F&rev=22
<div><strong>Rev 22 - rudi</strong> (14 file(s) modified)</div><div>Fixed several minor bugs, cleaned up the code further ...</div>~ /trunk/rtl/verilog/mc_adr_sel.v<br />~ /trunk/rtl/verilog/mc_cs_rf.v<br />~ /trunk/rtl/verilog/mc_defines.v<br />~ /trunk/rtl/verilog/mc_dp.v<br />~ /trunk/rtl/verilog/mc_incn_r.v<br />~ /trunk/rtl/verilog/mc_mem_if.v<br />~ /trunk/rtl/verilog/mc_obct.v<br />~ /trunk/rtl/verilog/mc_obct_top.v<br />~ /trunk/rtl/verilog/mc_rd_fifo.v<br />~ /trunk/rtl/verilog/mc_refresh.v<br />~ /trunk/rtl/verilog/mc_rf.v<br />~ /trunk/rtl/verilog/mc_timing.v<br />~ /trunk/rtl/verilog/mc_top.v<br />~ /trunk/rtl/verilog/mc_wb_if.v<br />
rudi
Mon, 21 Jan 2002 13:08:52 +0100
https://opencores.org/websvn//websvn/revision?repname=mem_ctrl&path=%2Ftrunk%2Frtl%2F&rev=22
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- Fixed combinatorial loops in synthesis
- Fixed byte select bug
https://opencores.org/websvn//websvn/revision?repname=mem_ctrl&path=%2Ftrunk%2Frtl%2F&rev=20
<div><strong>Rev 20 - rudi</strong> (5 file(s) modified)</div><div>- Fixed combinatorial loops in synthesis<br />
- Fixed byte select bug</div>~ /trunk/rtl/verilog/mc_mem_if.v<br />~ /trunk/rtl/verilog/mc_obct_top.v<br />~ /trunk/rtl/verilog/mc_rf.v<br />~ /trunk/rtl/verilog/mc_timing.v<br />~ /trunk/rtl/verilog/mc_top.v<br />
rudi
Fri, 21 Dec 2001 05:09:30 +0100
https://opencores.org/websvn//websvn/revision?repname=mem_ctrl&path=%2Ftrunk%2Frtl%2F&rev=20
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*** empty log message ***
https://opencores.org/websvn//websvn/revision?repname=mem_ctrl&path=%2Ftrunk%2Frtl%2F&rev=19
<div><strong>Rev 19 - rudi</strong> (1 file(s) modified)</div><div>*** empty log message ***</div>~ /trunk/rtl/verilog/mc_defines.v<br />
rudi
Wed, 12 Dec 2001 06:35:15 +0100
https://opencores.org/websvn//websvn/revision?repname=mem_ctrl&path=%2Ftrunk%2Frtl%2F&rev=19
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- Made some changes not to expect clock during reset ...
https://opencores.org/websvn//websvn/revision?repname=mem_ctrl&path=%2Ftrunk%2Frtl%2F&rev=18
<div><strong>Rev 18 - rudi</strong> (8 file(s) modified)</div><div>- Made some changes not to expect clock during reset ...</div>~ /trunk/rtl/verilog/mc_cs_rf.v<br />~ /trunk/rtl/verilog/mc_defines.v<br />~ /trunk/rtl/verilog/mc_dp.v<br />~ /trunk/rtl/verilog/mc_rd_fifo.v<br />~ /trunk/rtl/verilog/mc_refresh.v<br />~ /trunk/rtl/verilog/mc_rf.v<br />~ /trunk/rtl/verilog/mc_timing.v<br />~ /trunk/rtl/verilog/mc_wb_if.v<br />
rudi
Tue, 11 Dec 2001 02:47:19 +0100
https://opencores.org/websvn//websvn/revision?repname=mem_ctrl&path=%2Ftrunk%2Frtl%2F&rev=18
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- More Synthesis cleanup, mostly for speed
- Several bug fixes
- ...
https://opencores.org/websvn//websvn/revision?repname=mem_ctrl&path=%2Ftrunk%2Frtl%2F&rev=16
<div><strong>Rev 16 - rudi</strong> (16 file(s) modified)</div><div>- More Synthesis cleanup, mostly for speed<br />
- Several bug fixes<br />
- ...</div>~ /trunk/bench/verilog/160b3ver/adv_bb.v<br />~ /trunk/bench/verilog/sdram_models/16Mx16/mt48lc16m16a2.v<br />~ /trunk/bench/verilog/tests.v<br />~ /trunk/bench/verilog/test_bench_top.v<br />~ /trunk/bench/verilog/wb_mast_model.v<br />~ /trunk/rtl/verilog/mc_adr_sel.v<br />~ /trunk/rtl/verilog/mc_cs_rf.v<br />~ /trunk/rtl/verilog/mc_defines.v<br />~ /trunk/rtl/verilog/mc_dp.v<br />~ /trunk/rtl/verilog/mc_mem_if.v<br />~ /trunk/rtl/verilog/mc_obct.v<br />~ /trunk/rtl/verilog/mc_rd_fifo.v<br />~ /trunk/rtl/verilog/mc_rf.v<br />~ /trunk/rtl/verilog/mc_timing.v<br />~ /trunk/rtl/verilog/mc_top.v<br />~ /trunk/rtl/verilog/mc_wb_if.v<br />
rudi
Thu, 29 Nov 2001 02:17:37 +0100
https://opencores.org/websvn//websvn/revision?repname=mem_ctrl&path=%2Ftrunk%2Frtl%2F&rev=16
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Fixed Register reads
Tightened up timing for register rd/wr
https://opencores.org/websvn//websvn/revision?repname=mem_ctrl&path=%2Ftrunk%2Frtl%2F&rev=13
<div><strong>Rev 13 - rudi</strong> (1 file(s) modified)</div><div>Fixed Register reads<br />
Tightened up timing for register rd/wr</div>~ /trunk/rtl/verilog/mc_rf.v<br />
rudi
Thu, 04 Oct 2001 03:19:37 +0100
https://opencores.org/websvn//websvn/revision?repname=mem_ctrl&path=%2Ftrunk%2Frtl%2F&rev=13
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Changed Reset to be active high and async.
https://opencores.org/websvn//websvn/revision?repname=mem_ctrl&path=%2Ftrunk%2Frtl%2F&rev=12
<div><strong>Rev 12 - rudi</strong> (8 file(s) modified)</div><div>Changed Reset to be active high and async.</div>~ /trunk/rtl/verilog/mc_cs_rf.v<br />~ /trunk/rtl/verilog/mc_dp.v<br />~ /trunk/rtl/verilog/mc_mem_if.v<br />~ /trunk/rtl/verilog/mc_obct.v<br />~ /trunk/rtl/verilog/mc_refresh.v<br />~ /trunk/rtl/verilog/mc_rf.v<br />~ /trunk/rtl/verilog/mc_timing.v<br />~ /trunk/rtl/verilog/mc_wb_if.v<br />
rudi
Mon, 24 Sep 2001 00:38:21 +0100
https://opencores.org/websvn//websvn/revision?repname=mem_ctrl&path=%2Ftrunk%2Frtl%2F&rev=12
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*** empty log message ***
https://opencores.org/websvn//websvn/revision?repname=mem_ctrl&path=%2Ftrunk%2Frtl%2F&rev=11
<div><strong>Rev 11 - rudi</strong> (2 file(s) modified)</div><div>*** empty log message ***</div>~ /trunk/rtl/verilog/mc_defines.v<br />~ /trunk/rtl/verilog/mc_top.v<br />
rudi
Mon, 10 Sep 2001 13:44:17 +0100
https://opencores.org/websvn//websvn/revision?repname=mem_ctrl&path=%2Ftrunk%2Frtl%2F&rev=11
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Many fixes for minor bugs that showed up in gate ...
https://opencores.org/websvn//websvn/revision?repname=mem_ctrl&path=%2Ftrunk%2Frtl%2F&rev=9
<div><strong>Rev 9 - rudi</strong> (3 file(s) modified)</div><div>Many fixes for minor bugs that showed up in gate ...</div>~ /trunk/rtl/verilog/mc_mem_if.v<br />~ /trunk/rtl/verilog/mc_timing.v<br />~ /trunk/rtl/verilog/mc_top.v<br />
rudi
Sun, 02 Sep 2001 02:28:28 +0100
https://opencores.org/websvn//websvn/revision?repname=mem_ctrl&path=%2Ftrunk%2Frtl%2F&rev=9
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- Changed IO names to be more clear.
- Uniquifyed define ...
https://opencores.org/websvn//websvn/revision?repname=mem_ctrl&path=%2Ftrunk%2Frtl%2F&rev=8
<div><strong>Rev 8 - rudi</strong> (13 file(s) modified)</div><div>- Changed IO names to be more clear.<br />
- Uniquifyed define ...</div>~ /trunk/bench/verilog/tests.v<br />~ /trunk/bench/verilog/test_bench_top.v<br />~ /trunk/doc/mc_doc.pdf<br />~ /trunk/rtl/verilog/mc_adr_sel.v<br />~ /trunk/rtl/verilog/mc_cs_rf.v<br />~ /trunk/rtl/verilog/mc_defines.v<br />~ /trunk/rtl/verilog/mc_dp.v<br />~ /trunk/rtl/verilog/mc_obct_top.v<br />~ /trunk/rtl/verilog/mc_rf.v<br />~ /trunk/rtl/verilog/mc_timing.v<br />~ /trunk/rtl/verilog/mc_top.v<br />~ /trunk/rtl/verilog/mc_wb_if.v<br />~ /trunk/sim/rtl_sim/bin/Makefile<br />
rudi
Fri, 10 Aug 2001 08:16:21 +0100
https://opencores.org/websvn//websvn/revision?repname=mem_ctrl&path=%2Ftrunk%2Frtl%2F&rev=8
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1) Changed Directory Structure
2) Fixed several minor bugs
https://opencores.org/websvn//websvn/revision?repname=mem_ctrl&path=%2Ftrunk%2Frtl%2F&rev=4
<div><strong>Rev 4 - rudi</strong> (96 file(s) modified)</div><div>1) Changed Directory Structure<br />
2) Fixed several minor bugs</div>+ /trunk/bench<br />+ /trunk/bench/verilog<br />+ /trunk/bench/verilog/160b3ver<br />+ /trunk/bench/verilog/160b3ver/adv_bb.v<br />+ /trunk/bench/verilog/160b3ver/dp160b3b.v<br />+ /trunk/bench/verilog/160b3ver/DP160B3B_RU.V<br />+ /trunk/bench/verilog/160b3ver/dp160b3t.v<br />+ /trunk/bench/verilog/160b3ver/f160b3b.bkb<br />+ /trunk/bench/verilog/160b3ver/f160b3b.bke<br />+ /trunk/bench/verilog/160b3ver/f160b3b.bkt<br />+ /trunk/bench/verilog/160b3ver/f160b3t.bkb<br />+ /trunk/bench/verilog/160b3ver/f160b3t.bke<br />+ /trunk/bench/verilog/160b3ver/f160b3t.bkt<br />+ /trunk/bench/verilog/160b3ver/read.me<br />+ /trunk/bench/verilog/160b3ver/t160b3b.v<br />+ /trunk/bench/verilog/160b3ver/t160b3t.v<br />+ /trunk/bench/verilog/sdram_models<br />+ /trunk/bench/verilog/sdram_models/2Mx32<br />+ /trunk/bench/verilog/sdram_models/2Mx32/bank0.txt<br />+ /trunk/bench/verilog/sdram_models/2Mx32/bank1.txt<br />+ /trunk/bench/verilog/sdram_models/2Mx32/bank2.txt<br />+ /trunk/bench/verilog/sdram_models/2Mx32/bank3.txt<br />+ /trunk/bench/verilog/sdram_models/2Mx32/mt48lc2m32b2.v<br />+ /trunk/bench/verilog/sdram_models/4Mx16<br />+ /trunk/bench/verilog/sdram_models/4Mx16/bank0.txt<br />+ /trunk/bench/verilog/sdram_models/4Mx16/bank1.txt<br />+ /trunk/bench/verilog/sdram_models/4Mx16/bank2.txt<br />+ /trunk/bench/verilog/sdram_models/4Mx16/bank3.txt<br />+ /trunk/bench/verilog/sdram_models/4Mx16/mt48lc4m16a2.v<br />+ /trunk/bench/verilog/sdram_models/4Mx32<br />+ /trunk/bench/verilog/sdram_models/4Mx32/mt48lc4m32b2.v<br />+ /trunk/bench/verilog/sdram_models/8Mx8<br />+ /trunk/bench/verilog/sdram_models/8Mx8/bank0.txt<br />+ /trunk/bench/verilog/sdram_models/8Mx8/bank1.txt<br />+ /trunk/bench/verilog/sdram_models/8Mx8/bank2.txt<br />+ /trunk/bench/verilog/sdram_models/8Mx8/bank3.txt<br />+ /trunk/bench/verilog/sdram_models/8Mx8/mt48lc8m8a2.v<br />+ /trunk/bench/verilog/sdram_models/8Mx16<br />+ /trunk/bench/verilog/sdram_models/8Mx16/mt48lc8m16a2.v<br />+ /trunk/bench/verilog/sdram_models/16Mx8<br />+ /trunk/bench/verilog/sdram_models/16Mx8/mt48lc16m8a2.v<br />+ /trunk/bench/verilog/sdram_models/16Mx16<br />+ /trunk/bench/verilog/sdram_models/16Mx16/mt48lc16m16a2.v<br />+ /trunk/bench/verilog/sdram_models/32Mx8<br />+ /trunk/bench/verilog/sdram_models/32Mx8/mt48lc32m8a2.v<br />+ /trunk/bench/verilog/sram_models<br />+ /trunk/bench/verilog/sram_models/IDT71T67802<br />+ /trunk/bench/verilog/sram_models/IDT71T67802/idt71t67802s133.v<br />+ /trunk/bench/verilog/sram_models/IDT71T67802/idt71t67802s150.v<br />+ /trunk/bench/verilog/sram_models/IDT71T67802/idt71t67802s166.v<br />+ /trunk/bench/verilog/sram_models/IDT71T67802/idt_512Kx18_PBSRAM_test.v<br />+ /trunk/bench/verilog/sram_models/IDT71T67802/readme_71T67802<br />+ /trunk/bench/verilog/sram_models/MicronSRAM<br />+ /trunk/bench/verilog/sram_models/MicronSRAM/mt58l1my18d.v<br />+ /trunk/bench/verilog/sync_cs_dev.v<br />+ /trunk/bench/verilog/tests.v<br />+ /trunk/bench/verilog/test_bench_top.v<br />+ /trunk/bench/verilog/test_lib.v<br />+ /trunk/bench/verilog/wb_mast_model.v<br />+ /trunk/bench/verilog/wb_model_defines.v<br />+ /trunk/bench/vhdl<br />+ /trunk/bench/vhdl/8Kx8_vhdl.vhd<br />+ /trunk/bench/vhdl/mt48lc2m32b2.v<br />+ /trunk/bench/vhdl/mt58l64l32p.v<br />+ /trunk/bench/vhdl/tst_bench.vhd<br />~ /trunk/doc/README.txt<br />~ /trunk/doc/STATUS.txt<br />+ /trunk/rtl<br />+ /trunk/rtl/verilog<br />+ /trunk/rtl/verilog/mc_adr_sel.v<br />+ /trunk/rtl/verilog/mc_cs_rf.v<br />+ /trunk/rtl/verilog/mc_defines.v<br />+ /trunk/rtl/verilog/mc_dp.v<br />+ /trunk/rtl/verilog/mc_incn_r.v<br />+ /trunk/rtl/verilog/mc_mem_if.v<br />+ /trunk/rtl/verilog/mc_obct.v<br />+ /trunk/rtl/verilog/mc_obct_top.v<br />+ /trunk/rtl/verilog/mc_rd_fifo.v<br />+ /trunk/rtl/verilog/mc_refresh.v<br />+ /trunk/rtl/verilog/mc_rf.v<br />+ /trunk/rtl/verilog/mc_timing.v<br />+ /trunk/rtl/verilog/mc_top.v<br />+ /trunk/rtl/verilog/mc_wb_if.v<br />+ /trunk/sim<br />+ /trunk/sim/rtl_sim<br />+ /trunk/sim/rtl_sim/bin<br />+ /trunk/sim/rtl_sim/bin/Makefile<br />+ /trunk/sim/vhdl_rtl_sim<br />+ /trunk/sim/vhdl_rtl_sim/bin<br />+ /trunk/sim/vhdl_rtl_sim/bin/Makefile<br />+ /trunk/syn<br />+ /trunk/syn/bin<br />+ /trunk/syn/bin/comp.dc<br />+ /trunk/syn/bin/design_spec.dc<br />+ /trunk/syn/bin/lib_spec.dc<br />+ /trunk/syn/bin/read.dc<br />
rudi
Sun, 29 Jul 2001 07:34:41 +0100
https://opencores.org/websvn//websvn/revision?repname=mem_ctrl&path=%2Ftrunk%2Frtl%2F&rev=4
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