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minsoc WebSVN RSS feed - minsoc https://opencores.org/websvn//websvn/listing?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Fprj%2Fsrc%2F& Thu, 25 Jun 2026 05:31:10 +0100 FeedCreator 1.7.2 Creating a verilator branche. https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Fprj%2Fsrc%2F&rev=139 <div><strong>Rev 139 - rfajardo</strong> (1 file(s) modified)</div><div>Creating a verilator branche.</div>+ /minsoc/branches/verilator<br /> rfajardo Tue, 22 Nov 2011 10:09:55 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Fprj%2Fsrc%2F&rev=139 Roll back minsoc_bench.v to timed simulation. Merge minsoc_bench_core and minsoc_bench_clock ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Fprj%2Fsrc%2F&rev=133 <div><strong>Rev 133 - rfajardo</strong> (7 file(s) modified)</div><div>Roll back minsoc_bench.v to timed simulation. Merge minsoc_bench_core and minsoc_bench_clock ...</div>+ /minsoc/branches/rc-1.0/bench/verilog/minsoc_bench.v<br />~ /minsoc/branches/rc-1.0/bench/verilog/minsoc_bench_core.v<br />~ /minsoc/branches/rc-1.0/prj/src/minsoc_bench.prj<br />~ /minsoc/branches/rc-1.0/sim/modelsim/run_sim.bat<br />~ /minsoc/branches/rc-1.0/sim/modelsim/run_sim.sh<br />~ /minsoc/branches/rc-1.0/sim/run/run_bench<br />~ /minsoc/branches/rc-1.0/sw/utils/bin2hex.c<br /> rfajardo Mon, 07 Nov 2011 09:48:11 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Fprj%2Fsrc%2F&rev=133 Renaming testbench modules. Adding to ifdefs without which the testbench ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Fprj%2Fsrc%2F&rev=131 <div><strong>Rev 131 - rfajardo</strong> (4 file(s) modified)</div><div>Renaming testbench modules. Adding to ifdefs without which the testbench ...</div>- /minsoc/branches/rc-1.0/bench/verilog/minsoc_bench.v<br />~ /minsoc/branches/rc-1.0/bench/verilog/minsoc_bench_clock.v<br />+ /minsoc/branches/rc-1.0/bench/verilog/minsoc_bench_core.v<br />~ /minsoc/branches/rc-1.0/prj/src/minsoc_bench.prj<br /> rfajardo Thu, 03 Nov 2011 13:58:53 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Fprj%2Fsrc%2F&rev=131 Outsourcing clocks and reset generations from minsoc_bench.v to minsoc_bench_clock.v. https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Fprj%2Fsrc%2F&rev=128 <div><strong>Rev 128 - rfajardo</strong> (3 file(s) modified)</div><div>Outsourcing clocks and reset generations from minsoc_bench.v to minsoc_bench_clock.v.</div>~ /minsoc/branches/rc-1.0/bench/verilog/minsoc_bench.v<br />+ /minsoc/branches/rc-1.0/bench/verilog/minsoc_bench_clock.v<br />~ /minsoc/branches/rc-1.0/prj/src/minsoc_bench.prj<br /> rfajardo Wed, 02 Nov 2011 23:46:04 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Fprj%2Fsrc%2F&rev=128 ethmac.prj: a file was missing https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Fprj%2Fsrc%2F&rev=120 <div><strong>Rev 120 - rfajardo</strong> (1 file(s) modified)</div><div>ethmac.prj: a file was missing</div>~ /minsoc/branches/rc-1.0/prj/src/ethmac.prj<br /> rfajardo Thu, 27 Oct 2011 16:49:07 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Fprj%2Fsrc%2F&rev=120 minsoc-install.sh & minsoc-configure.sh: -aware of location ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Fprj%2Fsrc%2F&rev=113 <div><strong>Rev 113 - rfajardo</strong> (7 file(s) modified)</div><div>minsoc-install.sh & minsoc-configure.sh: <br /> -aware of location ...</div>~ /minsoc/branches/rc-1.0/backend/spartan3e_starter_kit/or1200_defines.v<br />~ /minsoc/branches/rc-1.0/backend/spartan3e_starter_kit_eth/or1200_defines.v<br />~ /minsoc/branches/rc-1.0/prj/Makefile<br />~ /minsoc/branches/rc-1.0/prj/src/blackboxes/or1200_top.v<br />~ /minsoc/branches/rc-1.0/utils/setup/configure.sh<br />~ /minsoc/branches/rc-1.0/utils/setup/minsoc-configure.sh<br />~ /minsoc/branches/rc-1.0/utils/setup/minsoc-install.sh<br /> rfajardo Thu, 27 Oct 2011 13:49:07 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Fprj%2Fsrc%2F&rev=113 Fixing several minor issues with the system: ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Fprj%2Fsrc%2F&rev=110 <div><strong>Rev 110 - rfajardo</strong> (13 file(s) modified)</div><div>Fixing several minor issues with the system:<br /> ...</div>~ /minsoc/branches/rc-1.0/backend/altera_3c25_board/configure<br />~ /minsoc/branches/rc-1.0/prj/Makefile<br />- /minsoc/branches/rc-1.0/prj/scripts/altprj.sh<br />+ /minsoc/branches/rc-1.0/prj/scripts/altvhdprj.sh<br />+ /minsoc/branches/rc-1.0/prj/scripts/altvprj.sh<br />~ /minsoc/branches/rc-1.0/prj/scripts/simverilog.sh<br />~ /minsoc/branches/rc-1.0/prj/scripts/simvhdl.sh<br />~ /minsoc/branches/rc-1.0/prj/scripts/xilinxprj.sh<br />~ /minsoc/branches/rc-1.0/prj/src/or1200_top.prj<br />~ /minsoc/branches/rc-1.0/rtl/verilog<br />+ /minsoc/branches/rc-1.0/utils/setup/configure.sh<br />+ /minsoc/branches/rc-1.0/utils/setup/minsoc-configure.sh<br />~ /minsoc/branches/rc-1.0/utils/setup/minsoc-install.sh<br /> rfajardo Wed, 26 Oct 2011 21:41:05 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Fprj%2Fsrc%2F&rev=110 Creating a branche for release candidate 1.0. https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Fprj%2Fsrc%2F&rev=109 <div><strong>Rev 109 - rfajardo</strong> (1 file(s) modified)</div><div>Creating a branche for release candidate 1.0.</div>+ /minsoc/branches/rc-1.0<br /> rfajardo Wed, 26 Oct 2011 19:51:48 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Fprj%2Fsrc%2F&rev=109 Some files needed for Altera synthesis https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Fprj%2Fsrc%2F&rev=96 <div><strong>Rev 96 - javieralso</strong> (5 file(s) modified)</div><div>Some files needed for Altera synthesis</div>~ /minsoc/trunk/backend/altera_3c25_board/configure<br />+ /minsoc/trunk/prj/altera/altera_virtual_jtag.prj<br />~ /minsoc/trunk/prj/Makefile<br />+ /minsoc/trunk/prj/scripts/altprj.sh<br />+ /minsoc/trunk/prj/src/altera_virtual_jtag.prj<br /> javieralso Sun, 11 Sep 2011 22:08:57 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Fprj%2Fsrc%2F&rev=96 minsoc_top.prj was splited into minsoc_top and minsoc_bench. minsoc_top still had ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Fprj%2Fsrc%2F&rev=89 <div><strong>Rev 89 - rfajardo</strong> (1 file(s) modified)</div><div>minsoc_top.prj was splited into minsoc_top and minsoc_bench. minsoc_top still had ...</div>~ /minsoc/trunk/prj/src/minsoc_top.prj<br /> rfajardo Tue, 06 Sep 2011 17:10:28 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Fprj%2Fsrc%2F&rev=89 Project structure, Xilinx Makefiles and simulation working. https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Fprj%2Fsrc%2F&rev=88 <div><strong>Rev 88 - rfajardo</strong> (20 file(s) modified)</div><div>Project structure, Xilinx Makefiles and simulation working.</div>~ /minsoc/trunk/backend/spartan3a_dsp_kit/minsoc_defines.v<br />~ /minsoc/trunk/backend/spartan3e_starter_kit/minsoc_defines.v<br />~ /minsoc/trunk/backend/spartan3e_starter_kit_eth/minsoc_defines.v<br />~ /minsoc/trunk/prj/Makefile<br />~ /minsoc/trunk/prj/scripts/simprj.sh<br />~ /minsoc/trunk/prj/scripts/xilinxprj.sh<br />~ /minsoc/trunk/prj/scripts/xilinxxst.sh<br />~ /minsoc/trunk/prj/sim/minsoc.src<br />~ /minsoc/trunk/prj/sim/minsoc_top.src<br />+ /minsoc/trunk/prj/src/minsoc_bench.prj<br />~ /minsoc/trunk/prj/src/minsoc_top.prj<br />~ /minsoc/trunk/prj/xilinx/adbg_top.xst<br />~ /minsoc/trunk/prj/xilinx/ethmac.xst<br />~ /minsoc/trunk/prj/xilinx/jtag_top.xst<br />~ /minsoc/trunk/prj/xilinx/minsoc_top.prj<br />~ /minsoc/trunk/prj/xilinx/minsoc_top.xst<br />~ /minsoc/trunk/prj/xilinx/or1200_top.xst<br />~ /minsoc/trunk/prj/xilinx/uart_top.xst<br />~ /minsoc/trunk/rtl/verilog/xilinx_dcm.v<br />~ /minsoc/trunk/syn/xilinx/Makefile<br /> rfajardo Tue, 06 Sep 2011 16:54:44 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Fprj%2Fsrc%2F&rev=88 Central project definition under prj. Synthesis and simulation take their ... https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Fprj%2Fsrc%2F&rev=85 <div><strong>Rev 85 - rfajardo</strong> (55 file(s) modified)</div><div>Central project definition under prj. Synthesis and simulation take their ...</div>~ /minsoc/trunk/backend/spartan3a_dsp_kit/configure<br />~ /minsoc/trunk/backend/spartan3e_starter_kit/configure<br />~ /minsoc/trunk/backend/spartan3e_starter_kit_eth/configure<br />~ /minsoc/trunk/backend/std/configure<br />+ /minsoc/trunk/prj<br />+ /minsoc/trunk/prj/altera<br />+ /minsoc/trunk/prj/Makefile<br />+ /minsoc/trunk/prj/scripts<br />+ /minsoc/trunk/prj/scripts/simprj.sh<br />+ /minsoc/trunk/prj/scripts/xilinxprj.sh<br />+ /minsoc/trunk/prj/scripts/xilinxxst.sh<br />+ /minsoc/trunk/prj/sim<br />+ /minsoc/trunk/prj/sim/adbg_top.src<br />+ /minsoc/trunk/prj/sim/ethmac.src<br />+ /minsoc/trunk/prj/sim/jtag_top.src<br />+ /minsoc/trunk/prj/sim/minsoc.src<br />+ /minsoc/trunk/prj/sim/minsoc_top.src<br />+ /minsoc/trunk/prj/sim/or1200_top.src<br />+ /minsoc/trunk/prj/sim/uart_top.src<br />+ /minsoc/trunk/prj/src<br />+ /minsoc/trunk/prj/src/adbg_top.prj<br />+ /minsoc/trunk/prj/src/blackboxes<br />+ /minsoc/trunk/prj/src/blackboxes/ethmac.v<br />- /minsoc/trunk/prj/src/blackboxes/eth_top.v<br />+ /minsoc/trunk/prj/src/ethmac.prj<br />+ /minsoc/trunk/prj/src/jtag_top.prj<br />+ /minsoc/trunk/prj/src/minsoc_top.prj<br />+ /minsoc/trunk/prj/src/or1200_top.prj<br />+ /minsoc/trunk/prj/src/uart_top.prj<br />+ /minsoc/trunk/prj/xilinx<br />+ /minsoc/trunk/prj/xilinx/adbg_top.prj<br />+ /minsoc/trunk/prj/xilinx/adbg_top.xst<br />+ /minsoc/trunk/prj/xilinx/ethmac.prj<br />+ /minsoc/trunk/prj/xilinx/ethmac.xst<br />+ /minsoc/trunk/prj/xilinx/jtag_top.prj<br />+ /minsoc/trunk/prj/xilinx/jtag_top.xst<br />+ /minsoc/trunk/prj/xilinx/minsoc_top.prj<br />+ /minsoc/trunk/prj/xilinx/minsoc_top.xst<br />+ /minsoc/trunk/prj/xilinx/or1200_top.prj<br />+ /minsoc/trunk/prj/xilinx/or1200_top.xst<br />+ /minsoc/trunk/prj/xilinx/uart_top.prj<br />+ /minsoc/trunk/prj/xilinx/uart_top.xst<br />- /minsoc/trunk/sim/bin<br />~ /minsoc/trunk/sim/modelsim/compile_design.bat<br />~ /minsoc/trunk/sim/modelsim/compile_design.sh<br />~ /minsoc/trunk/sim/run/generate_bench<br />- /minsoc/trunk/syn/blackboxes<br />- /minsoc/trunk/syn/buildSupport/adbg_top.prj<br />- /minsoc/trunk/syn/buildSupport/eth_top.prj<br />- /minsoc/trunk/syn/buildSupport/minsoc_top.prj<br />- /minsoc/trunk/syn/buildSupport/or1200_top.prj<br />- /minsoc/trunk/syn/buildSupport/uart_top.prj<br />- /minsoc/trunk/syn/src<br />+ /minsoc/trunk/syn/xilinx<br />+ /minsoc/trunk/syn/xilinx/Makefile<br /> rfajardo Tue, 06 Sep 2011 15:34:18 +0100 https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Fbranches%2Fverilator%2Fprj%2Fsrc%2F&rev=85

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