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https://opencores.org/ocsvn/minsoc/minsoc/trunk
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minsoc
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https://opencores.org/websvn//websvn/listing?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Frtl%2F&
Sat, 16 May 2026 04:18:49 +0100
FeedCreator 1.7.2
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Too many `endifs added to minsoc_xilinx_internal_jtag.v in revision 174. Ronan ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Frtl%2F&rev=175
<div><strong>Rev 175 - rfajardo</strong> (1 file(s) modified)</div><div>Too many `endifs added to minsoc_xilinx_internal_jtag.v in revision 174. Ronan ...</div>~ /minsoc/trunk/rtl/verilog/minsoc_xilinx_internal_jtag.v<br />
rfajardo
Sun, 12 May 2013 18:51:08 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Frtl%2F&rev=175
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Jay Aurabind's contribution of a port to the Nexys 3 ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Frtl%2F&rev=173
<div><strong>Rev 173 - rfajardo</strong> (11 file(s) modified)</div><div>Jay Aurabind's contribution of a port to the Nexys 3 ...</div>+ /minsoc/trunk/backend/nexys3<br />+ /minsoc/trunk/backend/nexys3/board.h<br />+ /minsoc/trunk/backend/nexys3/configure<br />+ /minsoc/trunk/backend/nexys3/gcc-opt.mk<br />+ /minsoc/trunk/backend/nexys3/minsoc_bench_defines.v<br />+ /minsoc/trunk/backend/nexys3/minsoc_defines.v<br />+ /minsoc/trunk/backend/nexys3/nexys3_master.ucf<br />+ /minsoc/trunk/backend/nexys3/orp.ld<br />~ /minsoc/trunk/rtl/verilog/minsoc_onchip_ram.v<br />~ /minsoc/trunk/rtl/verilog/minsoc_xilinx_internal_jtag.v<br />~ /minsoc/trunk/rtl/verilog/xilinx_dcm.v<br />
rfajardo
Sun, 07 Apr 2013 14:44:43 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Frtl%2F&rev=173
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Adjusting internal initiator array widths. They were 1 bit too ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Frtl%2F&rev=163
<div><strong>Rev 163 - rfajardo</strong> (1 file(s) modified)</div><div>Adjusting internal initiator array widths. They were 1 bit too ...</div>~ /minsoc/trunk/rtl/verilog/minsoc_tc_top.v<br />
rfajardo
Thu, 26 Jan 2012 10:02:25 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Frtl%2F&rev=163
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Adding de2_115_board port, thanks to Richard Hasha.
Support to JSP (JTAG ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Frtl%2F&rev=158
<div><strong>Rev 158 - rfajardo</strong> (46 file(s) modified)</div><div>Adding de2_115_board port, thanks to Richard Hasha.<br />
<br />
Support to JSP (JTAG ...</div>~ /minsoc/trunk/backend/altera_3c25_board/board.h<br />~ /minsoc/trunk/backend/altera_3c25_board/configure<br />~ /minsoc/trunk/backend/altera_3c25_board/minsoc_defines.v<br />+ /minsoc/trunk/backend/de2_115_board<br />+ /minsoc/trunk/backend/de2_115_board/board.h<br />+ /minsoc/trunk/backend/de2_115_board/configure<br />+ /minsoc/trunk/backend/de2_115_board/de2_115_board.ucf<br />+ /minsoc/trunk/backend/de2_115_board/gcc-opt.mk<br />+ /minsoc/trunk/backend/de2_115_board/minsoc_bench_defines.v<br />+ /minsoc/trunk/backend/de2_115_board/minsoc_defines.v<br />+ /minsoc/trunk/backend/de2_115_board/orp.ld<br />~ /minsoc/trunk/backend/spartan3a_dsp_kit/board.h<br />~ /minsoc/trunk/backend/spartan3a_dsp_kit/configure<br />~ /minsoc/trunk/backend/spartan3a_dsp_kit/minsoc_defines.v<br />~ /minsoc/trunk/backend/spartan3e_starter_kit/board.h<br />~ /minsoc/trunk/backend/spartan3e_starter_kit/configure<br />~ /minsoc/trunk/backend/spartan3e_starter_kit/minsoc_defines.v<br />~ /minsoc/trunk/backend/spartan3e_starter_kit_eth/board.h<br />~ /minsoc/trunk/backend/spartan3e_starter_kit_eth/configure<br />~ /minsoc/trunk/backend/spartan3e_starter_kit_eth/minsoc_defines.v<br />~ /minsoc/trunk/backend/spartan3e_starter_kit_eth/spartan3e_starter_kit_eth.ucf<br />~ /minsoc/trunk/backend/std/board.h<br />~ /minsoc/trunk/backend/std/configure<br />~ /minsoc/trunk/backend/std/minsoc_defines.v<br />~ /minsoc/trunk/backend/ug257/board.h<br />~ /minsoc/trunk/backend/ug257/configure<br />~ /minsoc/trunk/backend/ug257/minsoc_defines.v<br />~ /minsoc/trunk/prj/src/adbg_top.prj<br />~ /minsoc/trunk/prj/src/minsoc_top.prj<br />+ /minsoc/trunk/rtl/verilog/interconnect_defines.v<br />~ /minsoc/trunk/rtl/verilog/minsoc_top.v<br />~ /minsoc/trunk/sw/drivers/can.c<br />~ /minsoc/trunk/sw/drivers/eth.c<br />~ /minsoc/trunk/sw/drivers/i2c.c<br />+ /minsoc/trunk/sw/drivers/interconnect.h<br />~ /minsoc/trunk/sw/drivers/uart.c<br />~ /minsoc/trunk/sw/drivers/uart.h<br />~ /minsoc/trunk/sw/eth/eth.c<br />~ /minsoc/trunk/sw/eth/Makefile<br />+ /minsoc/trunk/sw/jsp<br />+ /minsoc/trunk/sw/jsp/jsp.c<br />+ /minsoc/trunk/sw/jsp/Makefile<br />~ /minsoc/trunk/sw/uart/Makefile<br />~ /minsoc/trunk/sw/uart/uart.c<br />~ /minsoc/trunk/utils/setup/configure.sh<br />~ /minsoc/trunk/utils/setup/minsoc-install.sh<br />
rfajardo
Thu, 05 Jan 2012 19:32:03 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Frtl%2F&rev=158
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Added hardware watchpoint indicators to debug unit break input, to ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Frtl%2F&rev=156
<div><strong>Rev 156 - nyawn</strong> (1 file(s) modified)</div><div>Added hardware watchpoint indicators to debug unit break input, to ...</div>~ /minsoc/trunk/rtl/verilog/minsoc_top.v<br />
nyawn
Sat, 31 Dec 2011 00:34:04 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Frtl%2F&rev=156
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Project structure, Xilinx Makefiles and simulation working.
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Frtl%2F&rev=88
<div><strong>Rev 88 - rfajardo</strong> (20 file(s) modified)</div><div>Project structure, Xilinx Makefiles and simulation working.</div>~ /minsoc/trunk/backend/spartan3a_dsp_kit/minsoc_defines.v<br />~ /minsoc/trunk/backend/spartan3e_starter_kit/minsoc_defines.v<br />~ /minsoc/trunk/backend/spartan3e_starter_kit_eth/minsoc_defines.v<br />~ /minsoc/trunk/prj/Makefile<br />~ /minsoc/trunk/prj/scripts/simprj.sh<br />~ /minsoc/trunk/prj/scripts/xilinxprj.sh<br />~ /minsoc/trunk/prj/scripts/xilinxxst.sh<br />~ /minsoc/trunk/prj/sim/minsoc.src<br />~ /minsoc/trunk/prj/sim/minsoc_top.src<br />+ /minsoc/trunk/prj/src/minsoc_bench.prj<br />~ /minsoc/trunk/prj/src/minsoc_top.prj<br />~ /minsoc/trunk/prj/xilinx/adbg_top.xst<br />~ /minsoc/trunk/prj/xilinx/ethmac.xst<br />~ /minsoc/trunk/prj/xilinx/jtag_top.xst<br />~ /minsoc/trunk/prj/xilinx/minsoc_top.prj<br />~ /minsoc/trunk/prj/xilinx/minsoc_top.xst<br />~ /minsoc/trunk/prj/xilinx/or1200_top.xst<br />~ /minsoc/trunk/prj/xilinx/uart_top.xst<br />~ /minsoc/trunk/rtl/verilog/xilinx_dcm.v<br />~ /minsoc/trunk/syn/xilinx/Makefile<br />
rfajardo
Tue, 06 Sep 2011 16:54:44 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Frtl%2F&rev=88
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Adapting minsoc_top.v and minsoc_verilog_files.txt to new names for top modules ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Frtl%2F&rev=75
<div><strong>Rev 75 - rfajardo</strong> (2 file(s) modified)</div><div>Adapting minsoc_top.v and minsoc_verilog_files.txt to new names for top modules ...</div>~ /minsoc/trunk/rtl/verilog/minsoc_top.v<br />~ /minsoc/trunk/sim/bin/minsoc_verilog_files.txt<br />
rfajardo
Thu, 11 Aug 2011 17:39:35 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Frtl%2F&rev=75
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Including a global timescale under minsoc/rtl/verilog to control simulation. It ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Frtl%2F&rev=70
<div><strong>Rev 70 - rfajardo</strong> (10 file(s) modified)</div><div>Including a global timescale under minsoc/rtl/verilog to control simulation. It ...</div>~ /minsoc/trunk/backend/spartan3a_dsp_kit/minsoc_bench_defines.v<br />~ /minsoc/trunk/backend/spartan3e_starter_kit/minsoc_bench_defines.v<br />~ /minsoc/trunk/backend/spartan3e_starter_kit_eth/minsoc_bench_defines.v<br />~ /minsoc/trunk/backend/std/minsoc_bench_defines.v<br />+ /minsoc/trunk/rtl/verilog/timescale.v<br />~ /minsoc/trunk/sim/bin/minsoc_verilog_files.txt<br />+ /minsoc/trunk/sim/modelsim<br />+ /minsoc/trunk/sim/modelsim/compile_design.sh<br />+ /minsoc/trunk/sim/modelsim/prepare_modelsim.sh<br />+ /minsoc/trunk/sim/modelsim/run_sim.sh<br />
rfajardo
Tue, 10 May 2011 10:06:07 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Frtl%2F&rev=70
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firmware makefiles:
-every firmware makefile has now ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Frtl%2F&rev=64
<div><strong>Rev 64 - rfajardo</strong> (61 file(s) modified)</div><div>firmware makefiles:<br />
-every firmware makefile has now ...</div>+ /minsoc/trunk/backend/ml509<br />- /minsoc/trunk/backend/ml509.ucf<br />+ /minsoc/trunk/backend/ml509/ml509.ucf<br />+ /minsoc/trunk/backend/spartan3a_dsp_kit<br />- /minsoc/trunk/backend/spartan3a_dsp_kit.ucf<br />+ /minsoc/trunk/backend/spartan3a_dsp_kit/board.h<br />+ /minsoc/trunk/backend/spartan3a_dsp_kit/configure<br />+ /minsoc/trunk/backend/spartan3a_dsp_kit/minsoc_defines.v<br />+ /minsoc/trunk/backend/spartan3a_dsp_kit/orp.ld<br />+ /minsoc/trunk/backend/spartan3a_dsp_kit/spartan3a_dsp_kit.ucf<br />+ /minsoc/trunk/backend/spartan3e_starter_kit<br />- /minsoc/trunk/backend/spartan3e_starter_kit.ucf<br />+ /minsoc/trunk/backend/spartan3e_starter_kit/board.h<br />+ /minsoc/trunk/backend/spartan3e_starter_kit/configure<br />+ /minsoc/trunk/backend/spartan3e_starter_kit/minsoc_defines.v<br />+ /minsoc/trunk/backend/spartan3e_starter_kit/orp.ld<br />+ /minsoc/trunk/backend/spartan3e_starter_kit/spartan3e_starter_kit.ucf<br />+ /minsoc/trunk/backend/std<br />+ /minsoc/trunk/backend/std/board.h<br />+ /minsoc/trunk/backend/std/minsoc_defines.v<br />+ /minsoc/trunk/backend/std/orp.ld<br />~ /minsoc/trunk/bench/verilog/minsoc_bench_defines.v<br />- /minsoc/trunk/rtl/verilog/minsoc_defines.v<br />~ /minsoc/trunk/sim/bin/minsoc_verilog_files.txt<br />~ /minsoc/trunk/sw/drivers/can.c<br />+ /minsoc/trunk/sw/drivers/common.mk<br />~ /minsoc/trunk/sw/drivers/eth.c<br />~ /minsoc/trunk/sw/drivers/i2c.c<br />- /minsoc/trunk/sw/drivers/Makefile<br />~ /minsoc/trunk/sw/drivers/uart.c<br />+ /minsoc/trunk/sw/eth/common.mk<br />~ /minsoc/trunk/sw/eth/eth.c<br />- /minsoc/trunk/sw/eth/Makefile<br />- /minsoc/trunk/sw/support/board.h<br />+ /minsoc/trunk/sw/support/common.mk<br />/minsoc/trunk/sw/support/Makefile<br />~ /minsoc/trunk/sw/support/Makefile.inc<br />- /minsoc/trunk/sw/support/orp.ld<br />~ /minsoc/trunk/sw/support/reset.S<br />~ /minsoc/trunk/sw/support/tick.c<br />+ /minsoc/trunk/sw/uart/common.mk<br />- /minsoc/trunk/sw/uart/Makefile<br />~ /minsoc/trunk/sw/uart/uart.c<br />- /minsoc/trunk/syn/blackboxes/OR1K_startup_generic.v<br />- /minsoc/trunk/syn/buildSupport/adbg_top.xst<br />- /minsoc/trunk/syn/buildSupport/eth_top.xst<br />- /minsoc/trunk/syn/buildSupport/minsoc_startup_top.prj<br />- /minsoc/trunk/syn/buildSupport/minsoc_startup_top.xst<br />~ /minsoc/trunk/syn/buildSupport/minsoc_top.prj<br />- /minsoc/trunk/syn/buildSupport/minsoc_top.xst<br />- /minsoc/trunk/syn/buildSupport/or1200_top.xst<br />- /minsoc/trunk/syn/buildSupport/uart_top.xst<br />- /minsoc/trunk/syn/Makefile<br />+ /minsoc/trunk/syn/src<br />+ /minsoc/trunk/syn/src/adbg_top.xst<br />+ /minsoc/trunk/syn/src/eth_top.xst<br />+ /minsoc/trunk/syn/src/Makefile<br />+ /minsoc/trunk/syn/src/minsoc_top.xst<br />+ /minsoc/trunk/syn/src/or1200_top.xst<br />+ /minsoc/trunk/syn/src/uart_top.xst<br />- /minsoc/trunk/utils/contributions/.directory<br />
rfajardo
Tue, 03 May 2011 11:01:33 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Frtl%2F&rev=64
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Adding a functional synthesis Makefile system. Still needs a reviews ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Frtl%2F&rev=63
<div><strong>Rev 63 - rfajardo</strong> (26 file(s) modified)</div><div>Adding a functional synthesis Makefile system. Still needs a reviews ...</div>~ /minsoc/trunk/backend/spartan3a_dsp_kit.ucf<br />~ /minsoc/trunk/rtl/verilog/altera_pll.v<br />~ /minsoc/trunk/rtl/verilog/minsoc_defines.v<br />+ /minsoc/trunk/syn<br />+ /minsoc/trunk/syn/blackboxes<br />+ /minsoc/trunk/syn/blackboxes/adbg_top.v<br />+ /minsoc/trunk/syn/blackboxes/eth_top.v<br />+ /minsoc/trunk/syn/blackboxes/OR1K_startup_generic.v<br />+ /minsoc/trunk/syn/blackboxes/or1200_top.v<br />+ /minsoc/trunk/syn/blackboxes/uart_top.v<br />+ /minsoc/trunk/syn/buildSupport<br />+ /minsoc/trunk/syn/buildSupport/adbg_top.prj<br />+ /minsoc/trunk/syn/buildSupport/adbg_top.xst<br />+ /minsoc/trunk/syn/buildSupport/eth_top.prj<br />+ /minsoc/trunk/syn/buildSupport/eth_top.xst<br />+ /minsoc/trunk/syn/buildSupport/minsoc_startup_top.prj<br />+ /minsoc/trunk/syn/buildSupport/minsoc_startup_top.xst<br />+ /minsoc/trunk/syn/buildSupport/minsoc_top.prj<br />+ /minsoc/trunk/syn/buildSupport/minsoc_top.xst<br />+ /minsoc/trunk/syn/buildSupport/or1200_top.prj<br />+ /minsoc/trunk/syn/buildSupport/or1200_top.xst<br />+ /minsoc/trunk/syn/buildSupport/uart_top.prj<br />+ /minsoc/trunk/syn/buildSupport/uart_top.xst<br />+ /minsoc/trunk/syn/doc<br />+ /minsoc/trunk/syn/doc/guideTop.pdf<br />+ /minsoc/trunk/syn/Makefile<br />
rfajardo
Fri, 29 Apr 2011 17:26:11 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Frtl%2F&rev=63
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Wrapping different family modules of same manufacturer in a single ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Frtl%2F&rev=62
<div><strong>Rev 62 - rfajardo</strong> (4 file(s) modified)</div><div>Wrapping different family modules of same manufacturer in a single ...</div>+ /minsoc/trunk/rtl/verilog/altera_pll.v<br />~ /minsoc/trunk/rtl/verilog/minsoc_clock_manager.v<br />- /minsoc/trunk/rtl/verilog/minsoc_pll.v<br />+ /minsoc/trunk/rtl/verilog/xilinx_dcm.v<br />
rfajardo
Fri, 29 Apr 2011 10:32:37 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Frtl%2F&rev=62
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Selection of memory model or implementation memory is now made ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Frtl%2F&rev=60
<div><strong>Rev 60 - rfajardo</strong> (8 file(s) modified)</div><div>Selection of memory model or implementation memory is now made ...</div>~ /minsoc/trunk/bench/verilog/minsoc_bench.v<br />~ /minsoc/trunk/bench/verilog/minsoc_bench_defines.v<br />~ /minsoc/trunk/bench/verilog/minsoc_memory_model.v<br />~ /minsoc/trunk/rtl/verilog/minsoc_top.v<br />- /minsoc/trunk/sim/bin/minsoc_memory.txt<br />- /minsoc/trunk/sim/bin/minsoc_model.txt<br />+ /minsoc/trunk/sim/bin/minsoc_verilog_files.txt<br />~ /minsoc/trunk/sim/run/generate_bench<br />
rfajardo
Thu, 28 Apr 2011 22:44:09 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Frtl%2F&rev=60
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Standard definitions depended on implementation order. Now, this should be ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Frtl%2F&rev=58
<div><strong>Rev 58 - rfajardo</strong> (2 file(s) modified)</div><div>Standard definitions depended on implementation order. Now, this should be ...</div>~ /minsoc/trunk/bench/verilog/minsoc_bench_defines.v<br />~ /minsoc/trunk/rtl/verilog/minsoc_defines.v<br />
rfajardo
Thu, 28 Apr 2011 21:50:11 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Frtl%2F&rev=58
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If a FPGA manufacturer is selected, the FPGA families of ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Frtl%2F&rev=57
<div><strong>Rev 57 - rfajardo</strong> (1 file(s) modified)</div><div>If a FPGA manufacturer is selected, the FPGA families of ...</div>~ /minsoc/trunk/rtl/verilog/minsoc_defines.v<br />
rfajardo
Thu, 28 Apr 2011 21:27:09 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Frtl%2F&rev=57
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Macros for all Altera family devices and pll instantiation
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Frtl%2F&rev=56
<div><strong>Rev 56 - javieralso</strong> (4 file(s) modified)</div><div>Macros for all Altera family devices and pll instantiation</div>~ /minsoc/trunk/rtl/verilog/minsoc_clock_manager.v<br />~ /minsoc/trunk/rtl/verilog/minsoc_defines.v<br />~ /minsoc/trunk/rtl/verilog/minsoc_pll.v<br />~ /minsoc/trunk/rtl/verilog/minsoc_top.v<br />
javieralso
Thu, 21 Apr 2011 22:40:38 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Frtl%2F&rev=56
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Indentation, deleting redundant files and adding externals
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Frtl%2F&rev=53
<div><strong>Rev 53 - ConX.</strong> (29 file(s) modified)</div><div>Indentation, deleting redundant files and adding externals</div>~ /minsoc/trunk/rtl/verilog<br />~ /minsoc/trunk/sw/drivers/can.c<br />~ /minsoc/trunk/sw/drivers/can.h<br />~ /minsoc/trunk/sw/drivers/eth.c<br />~ /minsoc/trunk/sw/drivers/eth.h<br />~ /minsoc/trunk/sw/drivers/i2c.c<br />~ /minsoc/trunk/sw/drivers/i2c.h<br />~ /minsoc/trunk/sw/drivers/interrupts.c<br />~ /minsoc/trunk/sw/drivers/Makefile<br />- /minsoc/trunk/sw/drivers/tick.c<br />- /minsoc/trunk/sw/drivers/tick.h<br />~ /minsoc/trunk/sw/drivers/uart.c<br />~ /minsoc/trunk/sw/drivers/uart.h<br />~ /minsoc/trunk/sw/eth/eth.c<br />~ /minsoc/trunk/sw/support/board.h<br />~ /minsoc/trunk/sw/support/except.S<br />~ /minsoc/trunk/sw/support/int.c<br />~ /minsoc/trunk/sw/support/int.h<br />~ /minsoc/trunk/sw/support/Makefile<br />~ /minsoc/trunk/sw/support/reset.S<br />~ /minsoc/trunk/sw/support/support.c<br />~ /minsoc/trunk/sw/support/support.h<br />+ /minsoc/trunk/sw/support/tick.c<br />+ /minsoc/trunk/sw/support/tick.h<br />- /minsoc/trunk/sw/support/uart.c<br />- /minsoc/trunk/sw/support/uart.h<br />- /minsoc/trunk/sw/support/vfnprintf.c<br />- /minsoc/trunk/sw/support/vfnprintf.h<br />~ /minsoc/trunk/sw/uart/uart.c<br />
ConX.
Wed, 20 Apr 2011 11:16:36 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Frtl%2F&rev=53
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Altera ALTPLL Megafunction Instantiation
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Frtl%2F&rev=52
<div><strong>Rev 52 - javieralso</strong> (4 file(s) modified)</div><div>Altera ALTPLL Megafunction Instantiation</div>~ /minsoc/trunk/rtl/verilog/minsoc_clock_manager.v<br />~ /minsoc/trunk/rtl/verilog/minsoc_defines.v<br />+ /minsoc/trunk/rtl/verilog/minsoc_pll.v<br />~ /minsoc/trunk/rtl/verilog/minsoc_top.v<br />
javieralso
Mon, 11 Apr 2011 21:03:29 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Frtl%2F&rev=52
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Start-up Starter, included in the MinSoC top file, has been ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Frtl%2F&rev=33
<div><strong>Rev 33 - rfajardo</strong> (1 file(s) modified)</div><div>Start-up Starter, included in the MinSoC top file, has been ...</div>~ /minsoc/trunk/rtl/verilog/minsoc_top.v<br />
rfajardo
Thu, 07 Oct 2010 13:19:10 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Frtl%2F&rev=33
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Adaption to or1200_r3. It is still important to change or1200_defines.v:
-`define ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Frtl%2F&rev=31
<div><strong>Rev 31 - rfajardo</strong> (5 file(s) modified)</div><div>Adaption to or1200_r3. It is still important to change or1200_defines.v:<br />
-`define ...</div>~ /minsoc/trunk/doc/howto.pdf<br />~ /minsoc/trunk/doc/src/howto.odt<br />~ /minsoc/trunk/rtl/verilog/minsoc_top.v<br />~ /minsoc/trunk/sim/bin/minsoc_memory.txt<br />~ /minsoc/trunk/sim/bin/minsoc_model.txt<br />
rfajardo
Fri, 30 Jul 2010 08:22:31 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Frtl%2F&rev=31
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On version 34 of the Advanced Debug System the signal ...
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Frtl%2F&rev=26
<div><strong>Rev 26 - rfajardo</strong> (1 file(s) modified)</div><div>On version 34 of the Advanced Debug System the signal ...</div>~ /minsoc/trunk/rtl/verilog/minsoc_top.v<br />
rfajardo
Sun, 11 Apr 2010 01:32:44 +0100
https://opencores.org/websvn//websvn/revision?repname=minsoc&path=%2Fminsoc%2Ftrunk%2Frtl%2F&rev=26
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