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openrisc_2011-10-31 WebSVN RSS feed - openrisc_2011-10-31 https://opencores.org/websvn//websvn/listing?repname=openrisc_2011-10-31&path=%2Fopenrisc%2F& Mon, 18 May 2026 22:49:18 +0100 FeedCreator 1.7.2 ORPSoC: The ability to use a free/gimped version of Modelsim ... https://opencores.org/websvn//websvn/revision?repname=openrisc_2011-10-31&path=%2Fopenrisc%2F&rev=651 <div><strong>Rev 651 - julius</strong> (1 file(s) modified)</div><div>ORPSoC: The ability to use a free/gimped version of Modelsim ...</div>~ /openrisc/trunk/orpsocv2/scripts/make/Makefile-board-modelsim.inc<br /> julius Sun, 09 Oct 2011 18:19:53 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc_2011-10-31&path=%2Fopenrisc%2F&rev=651 ORPSoC: documentation update to fix explanation of Xilinx environment setup, ... https://opencores.org/websvn//websvn/revision?repname=openrisc_2011-10-31&path=%2Fopenrisc%2F&rev=650 <div><strong>Rev 650 - julius</strong> (1 file(s) modified)</div><div>ORPSoC: documentation update to fix explanation of Xilinx environment setup, ...</div>~ /openrisc/trunk/orpsocv2/doc/orpsoc.texi<br /> julius Sat, 08 Oct 2011 20:55:45 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc_2011-10-31&path=%2Fopenrisc%2F&rev=650 porting some of standard demo tasks fix serial port(UART) interrupt handler https://opencores.org/websvn//websvn/revision?repname=openrisc_2011-10-31&path=%2Fopenrisc%2F&rev=649 <div><strong>Rev 649 - filepang</strong> (5 file(s) modified)</div><div>porting some of standard demo tasks<br /> <br /> fix serial port(UART) interrupt handler</div>~ /openrisc/trunk/rtos/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/FreeRTOSConfig.h<br />~ /openrisc/trunk/rtos/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/main.c<br />~ /openrisc/trunk/rtos/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/Makefile<br />~ /openrisc/trunk/rtos/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/serial/serial.c<br />~ /openrisc/trunk/rtos/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/sim.cfg<br /> filepang Thu, 22 Sep 2011 15:12:12 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc_2011-10-31&path=%2Fopenrisc%2F&rev=649 docs: OR1K architecture now labeled as revision 0 in draft ... https://opencores.org/websvn//websvn/revision?repname=openrisc_2011-10-31&path=%2Fopenrisc%2F&rev=648 <div><strong>Rev 648 - julius</strong> (1 file(s) modified)</div><div>docs: OR1K architecture now labeled as revision 0 in draft ...</div>~ /openrisc/trunk/docs/openrisc_arch_draft.odt<br /> julius Mon, 19 Sep 2011 19:52:23 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc_2011-10-31&path=%2Fopenrisc%2F&rev=648 or1200: update documentation to go with recent rtl commits https://opencores.org/websvn//websvn/revision?repname=openrisc_2011-10-31&path=%2Fopenrisc%2F&rev=647 <div><strong>Rev 647 - julius</strong> (2 file(s) modified)</div><div>or1200: update documentation to go with recent rtl commits</div>~ /openrisc/trunk/or1200/doc/openrisc1200_spec.pdf<br />~ /openrisc/trunk/or1200/doc/openrisc1200_spec.txt<br /> julius Mon, 19 Sep 2011 19:16:43 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc_2011-10-31&path=%2Fopenrisc%2F&rev=647 Support ORSoC FT4232 board by using second JTAG; should make ... https://opencores.org/websvn//websvn/revision?repname=openrisc_2011-10-31&path=%2Fopenrisc%2F&rev=646 <div><strong>Rev 646 - yannv</strong> (1 file(s) modified)</div><div>Support ORSoC FT4232 board by using second JTAG; should make ...</div>~ /openrisc/trunk/or_debug_proxy/src/linux_usb_driver_calls.c<br /> yannv Fri, 16 Sep 2011 09:11:35 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc_2011-10-31&path=%2Fopenrisc%2F&rev=646 or1200: Specification document source now in asciidoc format. ODT and ... https://opencores.org/websvn//websvn/revision?repname=openrisc_2011-10-31&path=%2Fopenrisc%2F&rev=645 <div><strong>Rev 645 - julius</strong> (30 file(s) modified)</div><div>or1200: Specification document source now in asciidoc format. ODT and ...</div>+ /openrisc/trunk/or1200/doc/docbook-xsl.css<br />+ /openrisc/trunk/or1200/doc/docbook.xsl<br />+ /openrisc/trunk/or1200/doc/gen-docinfo.pl<br />+ /openrisc/trunk/or1200/doc/img<br />+ /openrisc/trunk/or1200/doc/img/addr_translation.gif<br />+ /openrisc/trunk/or1200/doc/img/core_arch.gif<br />+ /openrisc/trunk/or1200/doc/img/core_interfaces.gif<br />+ /openrisc/trunk/or1200/doc/img/cpu_fpu_dsp.gif<br />+ /openrisc/trunk/or1200/doc/img/data_cache_diag.gif<br />+ /openrisc/trunk/or1200/doc/img/debug_unit_diag.gif<br />+ /openrisc/trunk/or1200/doc/img/dev_interface_cycles.gif<br />+ /openrisc/trunk/or1200/doc/img/inst_cache_diag.gif<br />+ /openrisc/trunk/or1200/doc/img/inst_mmu_diag.gif<br />+ /openrisc/trunk/or1200/doc/img/interrupt_controller.gif<br />+ /openrisc/trunk/or1200/doc/img/or_family.gif<br />+ /openrisc/trunk/or1200/doc/img/powerup_seq.gif<br />+ /openrisc/trunk/or1200/doc/img/powerup_seq_gatedclk.gif<br />+ /openrisc/trunk/or1200/doc/img/tlb_diag.gif<br />+ /openrisc/trunk/or1200/doc/img/watchpoint_trigger.gif<br />+ /openrisc/trunk/or1200/doc/img/wb_block_read.gif<br />+ /openrisc/trunk/or1200/doc/img/wb_compatible.png<br />+ /openrisc/trunk/or1200/doc/img/wb_read.gif<br />+ /openrisc/trunk/or1200/doc/img/wb_rw.gif<br />+ /openrisc/trunk/or1200/doc/img/wb_write.gif<br />+ /openrisc/trunk/or1200/doc/Makefile<br />~ /openrisc/trunk/or1200/doc/openrisc1200_spec.doc<br />~ /openrisc/trunk/or1200/doc/openrisc1200_spec.odt<br />~ /openrisc/trunk/or1200/doc/openrisc1200_spec.pdf<br />+ /openrisc/trunk/or1200/doc/openrisc1200_spec.txt<br />+ /openrisc/trunk/or1200/doc/preprocess.pl<br /> julius Thu, 01 Sep 2011 19:55:33 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc_2011-10-31&path=%2Fopenrisc%2F&rev=645 or1200: the infamous l.rfe fix, and bug fix for when ... https://opencores.org/websvn//websvn/revision?repname=openrisc_2011-10-31&path=%2Fopenrisc%2F&rev=644 <div><strong>Rev 644 - julius</strong> (2 file(s) modified)</div><div>or1200: the infamous l.rfe fix, and bug fix for when ...</div>~ /openrisc/trunk/or1200/rtl/verilog/or1200_ctrl.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_mult_mac.v<br /> julius Thu, 01 Sep 2011 18:56:01 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc_2011-10-31&path=%2Fopenrisc%2F&rev=644 or1200: new ALU comparision implementation option, TLB invalidate register indicated ... https://opencores.org/websvn//websvn/revision?repname=openrisc_2011-10-31&path=%2Fopenrisc%2F&rev=643 <div><strong>Rev 643 - julius</strong> (4 file(s) modified)</div><div>or1200: new ALU comparision implementation option, TLB invalidate register indicated ...</div>~ /openrisc/trunk/or1200/rtl/verilog/or1200_alu.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_defines.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_mult_mac.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_rf.v<br /> julius Thu, 01 Sep 2011 18:53:54 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc_2011-10-31&path=%2Fopenrisc%2F&rev=643 or1200: add carry, overflow bits, and range exception https://opencores.org/websvn//websvn/revision?repname=openrisc_2011-10-31&path=%2Fopenrisc%2F&rev=642 <div><strong>Rev 642 - julius</strong> (6 file(s) modified)</div><div>or1200: add carry, overflow bits, and range exception</div>~ /openrisc/trunk/or1200/rtl/verilog/or1200_alu.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_cpu.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_defines.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_except.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_mult_mac.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_sprs.v<br /> julius Thu, 01 Sep 2011 18:49:24 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc_2011-10-31&path=%2Fopenrisc%2F&rev=642 or1200: fix serial multiply/divide bug https://opencores.org/websvn//websvn/revision?repname=openrisc_2011-10-31&path=%2Fopenrisc%2F&rev=641 <div><strong>Rev 641 - julius</strong> (1 file(s) modified)</div><div>or1200: fix serial multiply/divide bug</div>~ /openrisc/trunk/or1200/rtl/verilog/or1200_mult_mac.v<br /> julius Thu, 01 Sep 2011 18:47:46 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc_2011-10-31&path=%2Fopenrisc%2F&rev=641 or1200: add l.ext instructions, fix a MAC bug https://opencores.org/websvn//websvn/revision?repname=openrisc_2011-10-31&path=%2Fopenrisc%2F&rev=640 <div><strong>Rev 640 - julius</strong> (6 file(s) modified)</div><div>or1200: add l.ext instructions, fix a MAC bug</div>~ /openrisc/trunk/or1200/rtl/verilog/or1200_alu.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_cpu.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_ctrl.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_defines.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_freeze.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_mult_mac.v<br /> julius Thu, 01 Sep 2011 18:43:11 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc_2011-10-31&path=%2Fopenrisc%2F&rev=640 or1200: or1200_dpram.v change task set_gpr to function https://opencores.org/websvn//websvn/revision?repname=openrisc_2011-10-31&path=%2Fopenrisc%2F&rev=639 <div><strong>Rev 639 - julius</strong> (1 file(s) modified)</div><div>or1200: or1200_dpram.v change task set_gpr to function</div>~ /openrisc/trunk/or1200/rtl/verilog/or1200_dpram.v<br /> julius Thu, 01 Sep 2011 18:36:47 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc_2011-10-31&path=%2Fopenrisc%2F&rev=639 orpsoc: xilinx: use XILINX env variable instead of rely on custom ... https://opencores.org/websvn//websvn/revision?repname=openrisc_2011-10-31&path=%2Fopenrisc%2F&rev=638 <div><strong>Rev 638 - stekern</strong> (9 file(s) modified)</div><div>orpsoc: xilinx: use XILINX env variable<br /> <br /> instead of rely on custom ...</div>~ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/backend/par/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/Makefile.inc<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/syn/xst/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/par/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/Makefile.inc<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/syn/xst/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/backend/par/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/Makefile.inc<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/syn/xst/bin/Makefile<br /> stekern Mon, 29 Aug 2011 03:19:08 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc_2011-10-31&path=%2Fopenrisc%2F&rev=638 porint parallel port(gpio) management task https://opencores.org/websvn//websvn/revision?repname=openrisc_2011-10-31&path=%2Fopenrisc%2F&rev=637 <div><strong>Rev 637 - filepang</strong> (1 file(s) modified)</div><div>porint parallel port(gpio) management task</div>~ /openrisc/trunk/rtos/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/ParTest/ParTest.c<br /> filepang Fri, 26 Aug 2011 14:38:07 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc_2011-10-31&path=%2Fopenrisc%2F&rev=637 porting serial port management task, interrupt hander https://opencores.org/websvn//websvn/revision?repname=openrisc_2011-10-31&path=%2Fopenrisc%2F&rev=636 <div><strong>Rev 636 - filepang</strong> (1 file(s) modified)</div><div>porting serial port management task, interrupt hander</div>~ /openrisc/trunk/rtos/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/serial/serial.c<br /> filepang Fri, 26 Aug 2011 14:36:02 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc_2011-10-31&path=%2Fopenrisc%2F&rev=636 Patch for http://bugzilla.opencores.org/show_bug.cgi?id=69. * ... https://opencores.org/websvn//websvn/revision?repname=openrisc_2011-10-31&path=%2Fopenrisc%2F&rev=635 <div><strong>Rev 635 - jeremybennett</strong> (2 file(s) modified)</div><div>Patch for <a href="http://bugzilla.opencores.org/show_bug.cgi?id=69" target="_blank">http://bugzilla.opencores.org/show_bug.cgi?id=69</a>.<br /> <br /> * ...</div>~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/ChangeLog.or32<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/config/or32/linux-elf.h<br /> jeremybennett Thu, 25 Aug 2011 10:51:01 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc_2011-10-31&path=%2Fopenrisc%2F&rev=635 orpsoc: atlys: autoregenerate coregen cores Instead of keeping binary .ngc files ... https://opencores.org/websvn//websvn/revision?repname=openrisc_2011-10-31&path=%2Fopenrisc%2F&rev=634 <div><strong>Rev 634 - stekern</strong> (5 file(s) modified)</div><div>orpsoc: atlys: autoregenerate coregen cores<br /> <br /> Instead of keeping binary .ngc files ...</div>- /openrisc/trunk/orpsocv2/boards/xilinx/atlys/backend/bin/xilinx_ddr2_if_cache.ngc<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/syn/xst/bin/Makefile<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/syn/xst/coregen<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/syn/xst/coregen/coregen.cgp<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/syn/xst/coregen/xilinx_ddr2_if_cache.xco<br /> stekern Wed, 24 Aug 2011 03:28:33 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc_2011-10-31&path=%2Fopenrisc%2F&rev=634 orpsoc: add Digilent Atlys spartan6 board README Signed-off-by: Stefan Kristiansson ... https://opencores.org/websvn//websvn/revision?repname=openrisc_2011-10-31&path=%2Fopenrisc%2F&rev=633 <div><strong>Rev 633 - stekern</strong> (1 file(s) modified)</div><div>orpsoc: add Digilent Atlys spartan6 board README<br /> <br /> Signed-off-by: Stefan Kristiansson <<a href="mailto:stefan.kristiansson@saunalahti.fi">stefan.kristiansson@saunalahti.fi</a>></div>+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/README<br /> stekern Wed, 24 Aug 2011 03:28:29 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc_2011-10-31&path=%2Fopenrisc%2F&rev=633 orpsoc: add Digilent Atlys spartan6 board sw include file Signed-off-by: Stefan ... https://opencores.org/websvn//websvn/revision?repname=openrisc_2011-10-31&path=%2Fopenrisc%2F&rev=632 <div><strong>Rev 632 - stekern</strong> (3 file(s) modified)</div><div>orpsoc: add Digilent Atlys spartan6 board sw include file<br /> <br /> Signed-off-by: Stefan ...</div>+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/sw/board<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/sw/board/include<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/sw/board/include/board.h<br /> stekern Wed, 24 Aug 2011 03:28:27 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc_2011-10-31&path=%2Fopenrisc%2F&rev=632

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