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openrisc_me WebSVN RSS feed - openrisc_me https://opencores.org/websvn//websvn/listing?repname=openrisc_me&path=%2Fopenrisc%2F& Mon, 18 May 2026 18:22:33 +0100 FeedCreator 1.7.2 Updated with new opcodes to generate random numbers and to ... https://opencores.org/websvn//websvn/revision?repname=openrisc_me&path=%2Fopenrisc%2F&rev=486 <div><strong>Rev 486 - jeremybennett</strong> (20 file(s) modified)</div><div>Updated with new opcodes to generate random numbers and to ...</div>~ /openrisc/trunk/or1ksim/ChangeLog<br />~ /openrisc/trunk/or1ksim/configure<br />~ /openrisc/trunk/or1ksim/configure.ac<br />~ /openrisc/trunk/or1ksim/cpu/or1k/spr-defs.h<br />~ /openrisc/trunk/or1ksim/cpu/or32/insnset.c<br />~ /openrisc/trunk/or1ksim/doc/or1ksim.info<br />~ /openrisc/trunk/or1ksim/doc/or1ksim.texi<br />~ /openrisc/trunk/or1ksim/libtoplevel.c<br />~ /openrisc/trunk/or1ksim/NEWS<br />~ /openrisc/trunk/or1ksim/peripheral/memory.c<br />~ /openrisc/trunk/or1ksim/sim-config.c<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure.ac<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/support/spr-defs.h<br />~ /openrisc/trunk/or1ksim/toplevel-mprofile.c<br />~ /openrisc/trunk/or1ksim/toplevel-profile.c<br />~ /openrisc/trunk/or1ksim/toplevel-support.c<br />~ /openrisc/trunk/or1ksim/toplevel-support.h<br />~ /openrisc/trunk/or1ksim/toplevel.c<br /> jeremybennett Thu, 27 Jan 2011 17:23:31 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc_me&path=%2Fopenrisc%2F&rev=486 Use variable names in help text to describe default options https://opencores.org/websvn//websvn/revision?repname=openrisc_me&path=%2Fopenrisc%2F&rev=485 <div><strong>Rev 485 - olof</strong> (1 file(s) modified)</div><div>Use variable names in help text to describe default options</div>~ /openrisc/trunk/gnu-src/bld-all.sh<br /> olof Wed, 26 Jan 2011 21:50:51 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc_me&path=%2Fopenrisc%2F&rev=485 ORPSoC update - adding ability to use a Modelsim without ... https://opencores.org/websvn//websvn/revision?repname=openrisc_me&path=%2Fopenrisc%2F&rev=484 <div><strong>Rev 484 - julius</strong> (2 file(s) modified)</div><div>ORPSoC update - adding ability to use a Modelsim without ...</div>~ /openrisc/trunk/orpsocv2/doc/orpsoc.texi<br />~ /openrisc/trunk/orpsocv2/sim/bin/Makefile<br /> julius Mon, 24 Jan 2011 03:51:47 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc_me&path=%2Fopenrisc%2F&rev=484 ORPSoC OR1200 update. Adding parity testbench and generic fault tolerance ... https://opencores.org/websvn//websvn/revision?repname=openrisc_me&path=%2Fopenrisc%2F&rev=483 <div><strong>Rev 483 - julius</strong> (72 file(s) modified)</div><div>ORPSoC OR1200 update. Adding parity testbench and generic fault tolerance ...</div>~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/board/include/board.h<br />~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/Makefile.inc<br />+ /openrisc/trunk/orpsocv2/boards/generic<br />+ /openrisc/trunk/orpsocv2/boards/generic/ft<br />+ /openrisc/trunk/orpsocv2/boards/generic/ft/backend<br />+ /openrisc/trunk/orpsocv2/boards/generic/ft/backend/rtl<br />+ /openrisc/trunk/orpsocv2/boards/generic/ft/backend/rtl/verilog<br />+ /openrisc/trunk/orpsocv2/boards/generic/ft/backend/rtl/verilog/dummy.v<br />+ /openrisc/trunk/orpsocv2/boards/generic/ft/bench<br />+ /openrisc/trunk/orpsocv2/boards/generic/ft/bench/verilog<br />+ /openrisc/trunk/orpsocv2/boards/generic/ft/bench/verilog/include<br />+ /openrisc/trunk/orpsocv2/boards/generic/ft/bench/verilog/include/orpsoc-testbench-defines.v<br />+ /openrisc/trunk/orpsocv2/boards/generic/ft/bench/verilog/include/timescale.v<br />+ /openrisc/trunk/orpsocv2/boards/generic/ft/bench/verilog/or1200_ft_stim.v<br />+ /openrisc/trunk/orpsocv2/boards/generic/ft/bench/verilog/or1200_monitor.v<br />+ /openrisc/trunk/orpsocv2/boards/generic/ft/bench/verilog/orpsoc_testbench.v<br />+ /openrisc/trunk/orpsocv2/boards/generic/ft/doc<br />+ /openrisc/trunk/orpsocv2/boards/generic/ft/doc/README<br />+ /openrisc/trunk/orpsocv2/boards/generic/ft/rtl<br />+ /openrisc/trunk/orpsocv2/boards/generic/ft/rtl/verilog<br />+ /openrisc/trunk/orpsocv2/boards/generic/ft/rtl/verilog/arbiter<br />+ /openrisc/trunk/orpsocv2/boards/generic/ft/rtl/verilog/arbiter/arbiter_bytebus.v<br />+ /openrisc/trunk/orpsocv2/boards/generic/ft/rtl/verilog/arbiter/arbiter_dbus.v<br />+ /openrisc/trunk/orpsocv2/boards/generic/ft/rtl/verilog/arbiter/arbiter_ibus.v<br />+ /openrisc/trunk/orpsocv2/boards/generic/ft/rtl/verilog/clkgen<br />+ /openrisc/trunk/orpsocv2/boards/generic/ft/rtl/verilog/clkgen/clkgen.v<br />+ /openrisc/trunk/orpsocv2/boards/generic/ft/rtl/verilog/clkgen/README<br />+ /openrisc/trunk/orpsocv2/boards/generic/ft/rtl/verilog/include<br />+ /openrisc/trunk/orpsocv2/boards/generic/ft/rtl/verilog/include/or1200_defines.v<br />+ /openrisc/trunk/orpsocv2/boards/generic/ft/rtl/verilog/include/orpsoc-defines.v<br />+ /openrisc/trunk/orpsocv2/boards/generic/ft/rtl/verilog/include/orpsoc-params.v<br />+ /openrisc/trunk/orpsocv2/boards/generic/ft/rtl/verilog/orpsoc_top<br />+ /openrisc/trunk/orpsocv2/boards/generic/ft/rtl/verilog/orpsoc_top/orpsoc_top.v<br />+ /openrisc/trunk/orpsocv2/boards/generic/ft/rtl/verilog/parity_err_handler<br />+ /openrisc/trunk/orpsocv2/boards/generic/ft/rtl/verilog/parity_err_handler/parity_err_handler.v<br />+ /openrisc/trunk/orpsocv2/boards/generic/ft/sim<br />+ /openrisc/trunk/orpsocv2/boards/generic/ft/sim/bin<br />+ /openrisc/trunk/orpsocv2/boards/generic/ft/sim/bin/Makefile<br />+ /openrisc/trunk/orpsocv2/boards/generic/ft/sim/out<br />+ /openrisc/trunk/orpsocv2/boards/generic/ft/sim/run<br />+ /openrisc/trunk/orpsocv2/boards/generic/ft/sim/run/Makefile<br />+ /openrisc/trunk/orpsocv2/boards/generic/ft/sw<br />+ /openrisc/trunk/orpsocv2/boards/generic/ft/sw/board<br />+ /openrisc/trunk/orpsocv2/boards/generic/ft/sw/board/include<br />+ /openrisc/trunk/orpsocv2/boards/generic/ft/sw/board/include/board.h<br />+ /openrisc/trunk/orpsocv2/boards/generic/ft/sw/Makefile.inc<br />+ /openrisc/trunk/orpsocv2/boards/generic/ft/sw/tests<br />+ /openrisc/trunk/orpsocv2/boards/generic/ft/sw/tests/or1200ft<br />+ /openrisc/trunk/orpsocv2/boards/generic/ft/sw/tests/or1200ft/sim<br />+ /openrisc/trunk/orpsocv2/boards/generic/ft/sw/tests/or1200ft/sim/Makefile<br />+ /openrisc/trunk/orpsocv2/boards/generic/ft/sw/tests/or1200ft/sim/or1200ft-parity.c<br />~ /openrisc/trunk/orpsocv2/doc/orpsoc.texi<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_cpu.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_dc_ram.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_dc_tag.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_dc_top.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_dmmu_tlb.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_dmmu_top.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_dpram.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_ic_ram.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_ic_tag.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_ic_top.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_immu_tlb.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_immu_top.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_parity_chk.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_rf.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_spram.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_spram_32_bw.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_top.v<br />~ /openrisc/trunk/orpsocv2/sw/drivers/or1200/crt0.S<br />~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-dctest.c<br />~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-mmu.c<br /> julius Mon, 24 Jan 2011 00:35:27 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc_me&path=%2Fopenrisc%2F&rev=483 ORPSoC updates - adding parity checking RTL, ethernet MAC FIFO ... https://opencores.org/websvn//websvn/revision?repname=openrisc_me&path=%2Fopenrisc%2F&rev=482 <div><strong>Rev 482 - julius</strong> (20 file(s) modified)</div><div>ORPSoC updates - adding parity checking RTL, ethernet MAC FIFO ...</div>~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/include/eth_stim.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/include/ethmac_defines.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_fifo.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_wishbone.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/include/or1200_defines.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_dc_ram.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_dc_tag.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_dmmu_tlb.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_dpram.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_ic_ram.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_ic_tag.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_immu_tlb.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_parity_chk.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_parity_gen.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_rf.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_spram.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_spram_32_bw.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/orpsoc_top/orpsoc_top.v<br />~ /openrisc/trunk/orpsocv2/sw/drivers/simple-spi/simple-spi.c<br />~ /openrisc/trunk/orpsocv2/sw/drivers/uart/uart.c<br /> julius Wed, 19 Jan 2011 07:04:19 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc_me&path=%2Fopenrisc%2F&rev=482 OR1200 Update. RTL and spec. https://opencores.org/websvn//websvn/revision?repname=openrisc_me&path=%2Fopenrisc%2F&rev=481 <div><strong>Rev 481 - julius</strong> (23 file(s) modified)</div><div>OR1200 Update. RTL and spec.</div>~ /openrisc/trunk/or1200/doc/openrisc1200_spec.doc<br />~ /openrisc/trunk/or1200/doc/openrisc1200_spec.odt<br />~ /openrisc/trunk/or1200/doc/openrisc1200_spec.pdf<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_alu.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_cpu.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_dc_fsm.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_dc_ram.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_dc_tag.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_dc_top.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_defines.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_dpram.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_gmultp2_32x32.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_ic_fsm.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_ic_ram.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_ic_tag.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_ic_top.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_immu_top.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_mult_mac.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_rfram_generic.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_sprs.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_top.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_tt.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_wb_biu.v<br /> julius Wed, 19 Jan 2011 02:45:51 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc_me&path=%2Fopenrisc%2F&rev=481 ORPSoC updates - ml501 project cleanups, DDR2 cache bug fixes. https://opencores.org/websvn//websvn/revision?repname=openrisc_me&path=%2Fopenrisc%2F&rev=480 <div><strong>Rev 480 - julius</strong> (8 file(s) modified)</div><div>ORPSoC updates - ml501 project cleanups, DDR2 cache bug fixes.</div>~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/Makefile.inc<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/include/eth_stim.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/xilinx_ddr2/ddr2_ctrl.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/xilinx_ddr2/xilinx_ddr2_if.v<br />- /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/eth<br />- /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/gpio<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/Makefile.inc<br />- /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/memtest<br /> julius Tue, 18 Jan 2011 05:09:41 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc_me&path=%2Fopenrisc%2F&rev=480 ORPSoC update to ml501 board port. Memory controller caching fixed ... https://opencores.org/websvn//websvn/revision?repname=openrisc_me&path=%2Fopenrisc%2F&rev=479 <div><strong>Rev 479 - julius</strong> (11 file(s) modified)</div><div>ORPSoC update to ml501 board port. Memory controller caching fixed ...</div>~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/par/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/par/bin/ml501.ucf<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/include/or1200_defines.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/xilinx_ddr2/xilinx_ddr2_if.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sim/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/board/include/board.h<br />~ /openrisc/trunk/orpsocv2/doc/orpsoc.texi<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_wb_biu.v<br />~ /openrisc/trunk/orpsocv2/sw/bootrom/Makefile<br />~ /openrisc/trunk/orpsocv2/sw/Makefile.inc<br />~ /openrisc/trunk/orpsocv2/sw/tests/ethmac/board/ethmac-ping.c<br /> julius Mon, 17 Jan 2011 05:44:06 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc_me&path=%2Fopenrisc%2F&rev=479 ORPSoC update - ml501 or1200 cache configuration set to maximum, ... https://opencores.org/websvn//websvn/revision?repname=openrisc_me&path=%2Fopenrisc%2F&rev=478 <div><strong>Rev 478 - julius</strong> (4 file(s) modified)</div><div>ORPSoC update - ml501 or1200 cache configuration set to maximum, ...</div>~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/par/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/include/or1200_defines.v<br />- /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/boot<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_rfram_generic.v<br /> julius Sat, 15 Jan 2011 14:01:36 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc_me&path=%2Fopenrisc%2F&rev=478 ORPSoC update - Added ability to enable OR1200 caches up ... https://opencores.org/websvn//websvn/revision?repname=openrisc_me&path=%2Fopenrisc%2F&rev=477 <div><strong>Rev 477 - julius</strong> (13 file(s) modified)</div><div>ORPSoC update - Added ability to enable OR1200 caches up ...</div>~ /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/include/or1200_defines.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_dc_fsm.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_dc_ram.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_dc_tag.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_dc_top.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_ic_fsm.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_ic_ram.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_ic_tag.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_top.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_wb_biu.v<br />~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-mmu.c<br />~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-ticksyscall.S<br /> julius Sat, 15 Jan 2011 05:48:25 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc_me&path=%2Fopenrisc%2F&rev=477 ORPSoC updates. Added 16kB cache options to OR1200, now as ... https://opencores.org/websvn//websvn/revision?repname=openrisc_me&path=%2Fopenrisc%2F&rev=476 <div><strong>Rev 476 - julius</strong> (6 file(s) modified)</div><div>ORPSoC updates. Added 16kB cache options to OR1200, now as ...</div>~ /openrisc/trunk/orpsocv2/rtl/verilog/include/or1200_defines.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_dc_ram.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_dc_tag.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_ic_ram.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_ic_tag.v<br />~ /openrisc/trunk/orpsocv2/sim/bin/Makefile<br /> julius Fri, 14 Jan 2011 12:42:08 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc_me&path=%2Fopenrisc%2F&rev=476 ORPSoC main simulation makefile tidy up, addition of BSS test ... https://opencores.org/websvn//websvn/revision?repname=openrisc_me&path=%2Fopenrisc%2F&rev=475 <div><strong>Rev 475 - julius</strong> (8 file(s) modified)</div><div>ORPSoC main simulation makefile tidy up, addition of BSS test ...</div>+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sim/bin/ordb1a3pe1500-or1ksim.cfg<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sim/bin/ml501-or1ksim.cfg<br />~ /openrisc/trunk/orpsocv2/sim/bin/Makefile<br />- /openrisc/trunk/orpsocv2/sim/bin/or1ksim-orpsocv2.cfg<br />+ /openrisc/trunk/orpsocv2/sim/bin/refdesign-or1ksim.cfg<br />~ /openrisc/trunk/orpsocv2/sw/drivers/or1200/crt0.S<br />~ /openrisc/trunk/orpsocv2/sw/drivers/or1200/link.ld<br />~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-cbasic.c<br /> julius Fri, 14 Jan 2011 10:09:21 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc_me&path=%2Fopenrisc%2F&rev=475 uC/OS-II port linker flags updated. https://opencores.org/websvn//websvn/revision?repname=openrisc_me&path=%2Fopenrisc%2F&rev=474 <div><strong>Rev 474 - julius</strong> (2 file(s) modified)</div><div>uC/OS-II port linker flags updated.</div>~ /openrisc/trunk/rtos/ucos-ii/2.91/ChangeLog-OR32<br />~ /openrisc/trunk/rtos/ucos-ii/2.91/config.mk<br /> julius Fri, 14 Jan 2011 04:13:49 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc_me&path=%2Fopenrisc%2F&rev=474 Fix typos in tool chain build script. Add build script ... https://opencores.org/websvn//websvn/revision?repname=openrisc_me&path=%2Fopenrisc%2F&rev=473 <div><strong>Rev 473 - jeremybennett</strong> (7 file(s) modified)</div><div>Fix typos in tool chain build script. Add build script ...</div>- /openrisc/trunk/gnu-src/bld++.sh<br />~ /openrisc/trunk/gnu-src/bld-all.sh<br />+ /openrisc/trunk/gnu-src/bld-bb.sh<br />- /openrisc/trunk/gnu-src/bld.sh<br />~ /openrisc/trunk/gnu-src/boards/or32-linux-sim.exp<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/ChangeLog.or32<br />~ /openrisc/trunk/gnu-src/gcc-4.5.1/gcc/config/or32/or32.h<br /> jeremybennett Thu, 13 Jan 2011 09:43:04 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc_me&path=%2Fopenrisc%2F&rev=473 Various changes which improve the quality of the tracing. https://opencores.org/websvn//websvn/revision?repname=openrisc_me&path=%2Fopenrisc%2F&rev=472 <div><strong>Rev 472 - jeremybennett</strong> (8 file(s) modified)</div><div>Various changes which improve the quality of the tracing.</div>~ /openrisc/trunk/or1ksim/ChangeLog<br />~ /openrisc/trunk/or1ksim/cpu/common/abstract.c<br />~ /openrisc/trunk/or1ksim/cpu/common/abstract.h<br />~ /openrisc/trunk/or1ksim/cpu/or32/execute.c<br />~ /openrisc/trunk/or1ksim/doc/or1ksim.info<br />~ /openrisc/trunk/or1ksim/doc/or1ksim.texi<br />~ /openrisc/trunk/or1ksim/sim-config.c<br />~ /openrisc/trunk/or1ksim/sim-config.h<br /> jeremybennett Thu, 13 Jan 2011 08:22:43 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc_me&path=%2Fopenrisc%2F&rev=472 Adding ucos-ii port. https://opencores.org/websvn//websvn/revision?repname=openrisc_me&path=%2Fopenrisc%2F&rev=471 <div><strong>Rev 471 - julius</strong> (49 file(s) modified)</div><div>Adding ucos-ii port.</div>+ /openrisc/trunk/rtos/ucos-ii<br />+ /openrisc/trunk/rtos/ucos-ii/2.91<br />+ /openrisc/trunk/rtos/ucos-ii/2.91/ChangeLog-OR32<br />+ /openrisc/trunk/rtos/ucos-ii/2.91/common<br />+ /openrisc/trunk/rtos/ucos-ii/2.91/common/app_cfg.h<br />+ /openrisc/trunk/rtos/ucos-ii/2.91/common/cprintf.c<br />+ /openrisc/trunk/rtos/ucos-ii/2.91/common/cprintf_r.c<br />+ /openrisc/trunk/rtos/ucos-ii/2.91/common/ctype.c<br />+ /openrisc/trunk/rtos/ucos-ii/2.91/common/main.c<br />+ /openrisc/trunk/rtos/ucos-ii/2.91/common/Makefile<br />+ /openrisc/trunk/rtos/ucos-ii/2.91/common/string.c<br />+ /openrisc/trunk/rtos/ucos-ii/2.91/config.mk<br />+ /openrisc/trunk/rtos/ucos-ii/2.91/COPYING<br />+ /openrisc/trunk/rtos/ucos-ii/2.91/drivers<br />+ /openrisc/trunk/rtos/ucos-ii/2.91/drivers/console.c<br />+ /openrisc/trunk/rtos/ucos-ii/2.91/drivers/Makefile<br />+ /openrisc/trunk/rtos/ucos-ii/2.91/drivers/uart.c<br />+ /openrisc/trunk/rtos/ucos-ii/2.91/include<br />+ /openrisc/trunk/rtos/ucos-ii/2.91/include/board.h<br />+ /openrisc/trunk/rtos/ucos-ii/2.91/include/console.h<br />+ /openrisc/trunk/rtos/ucos-ii/2.91/include/cprintf_r.h<br />+ /openrisc/trunk/rtos/ucos-ii/2.91/include/ctype.h<br />+ /openrisc/trunk/rtos/ucos-ii/2.91/include/includes.h<br />+ /openrisc/trunk/rtos/ucos-ii/2.91/include/os_cfg.h<br />+ /openrisc/trunk/rtos/ucos-ii/2.91/include/os_cpu.h<br />+ /openrisc/trunk/rtos/ucos-ii/2.91/include/spr-defs.h<br />+ /openrisc/trunk/rtos/ucos-ii/2.91/include/spr_defs.h<br />+ /openrisc/trunk/rtos/ucos-ii/2.91/include/string.h<br />+ /openrisc/trunk/rtos/ucos-ii/2.91/include/uart.h<br />+ /openrisc/trunk/rtos/ucos-ii/2.91/include/ucos_ii.h<br />+ /openrisc/trunk/rtos/ucos-ii/2.91/Makefile<br />+ /openrisc/trunk/rtos/ucos-ii/2.91/ram.ld<br />+ /openrisc/trunk/rtos/ucos-ii/2.91/README<br />+ /openrisc/trunk/rtos/ucos-ii/2.91/sim.cfg<br />+ /openrisc/trunk/rtos/ucos-ii/2.91/tasks<br />+ /openrisc/trunk/rtos/ucos-ii/2.91/tasks/Makefile<br />+ /openrisc/trunk/rtos/ucos-ii/2.91/tasks/tasks1.c<br />+ /openrisc/trunk/rtos/ucos-ii/2.91/ucos<br />+ /openrisc/trunk/rtos/ucos-ii/2.91/ucos-port<br />+ /openrisc/trunk/rtos/ucos-ii/2.91/ucos-port/Makefile<br />+ /openrisc/trunk/rtos/ucos-ii/2.91/ucos-port/os_cpu_a.S<br />+ /openrisc/trunk/rtos/ucos-ii/2.91/ucos-port/os_cpu_c.c<br />+ /openrisc/trunk/rtos/ucos-ii/2.91/ucos/Makefile<br />+ /openrisc/trunk/rtos/ucos-ii/2.91/utils<br />+ /openrisc/trunk/rtos/ucos-ii/2.91/utils/bin2flimg<br />+ /openrisc/trunk/rtos/ucos-ii/2.91/utils/bin2flimg.c<br />+ /openrisc/trunk/rtos/ucos-ii/2.91/utils/bin2srec<br />+ /openrisc/trunk/rtos/ucos-ii/2.91/utils/bin2srec.c<br />+ /openrisc/trunk/rtos/ucos-ii/2.91/utils/Makefile<br /> julius Tue, 11 Jan 2011 05:22:52 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc_me&path=%2Fopenrisc%2F&rev=471 ORPSoC OR1200 crt0 updates. https://opencores.org/websvn//websvn/revision?repname=openrisc_me&path=%2Fopenrisc%2F&rev=470 <div><strong>Rev 470 - julius</strong> (1 file(s) modified)</div><div>ORPSoC OR1200 crt0 updates.</div>~ /openrisc/trunk/orpsocv2/sw/drivers/or1200/crt0.S<br /> julius Mon, 10 Jan 2011 10:05:26 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc_me&path=%2Fopenrisc%2F&rev=470 newlib update - added zeroing of r0 to crt0.S https://opencores.org/websvn//websvn/revision?repname=openrisc_me&path=%2Fopenrisc%2F&rev=469 <div><strong>Rev 469 - julius</strong> (3 file(s) modified)</div><div>newlib update - added zeroing of r0 to crt0.S</div>~ /openrisc/trunk/gnu-src/gcc-4.5.1/LAST_UPDATED<br />~ /openrisc/trunk/gnu-src/newlib-1.18.0/libgloss/ChangeLog.or32<br />~ /openrisc/trunk/gnu-src/newlib-1.18.0/libgloss/or32/crt0.S<br /> julius Sun, 09 Jan 2011 09:05:30 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc_me&path=%2Fopenrisc%2F&rev=469 ORPSoC update: Added USER_ELF and USER_VMEM options to reference design simulation ... https://opencores.org/websvn//websvn/revision?repname=openrisc_me&path=%2Fopenrisc%2F&rev=468 <div><strong>Rev 468 - julius</strong> (14 file(s) modified)</div><div>ORPSoC update:<br /> Added USER_ELF and USER_VMEM options to reference design simulation ...</div>~ /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v<br />~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sim/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/bootrom/Makefile<br />~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/Makefile.inc<br />~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/syn/synplify/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sim/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/board/include/board.h<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/bootrom/Makefile<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/Makefile.inc<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/syn/xst/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/doc/orpsoc.texi<br />~ /openrisc/trunk/orpsocv2/sim/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/sw/lib/Makefile<br />~ /openrisc/trunk/orpsocv2/sw/Makefile.inc<br /> julius Sun, 09 Jan 2011 08:57:32 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc_me&path=%2Fopenrisc%2F&rev=468 ORPmon - bug fixes and clean up. https://opencores.org/websvn//websvn/revision?repname=openrisc_me&path=%2Fopenrisc%2F&rev=467 <div><strong>Rev 467 - julius</strong> (19 file(s) modified)</div><div>ORPmon - bug fixes and clean up.</div>~ /openrisc/trunk/bootloaders/orpmon/ChangeLog<br />~ /openrisc/trunk/bootloaders/orpmon/cmds/global.c<br />~ /openrisc/trunk/bootloaders/orpmon/cmds/memory.c<br />~ /openrisc/trunk/bootloaders/orpmon/common/common.c<br />~ /openrisc/trunk/bootloaders/orpmon/common/Makefile<br />- /openrisc/trunk/bootloaders/orpmon/common/spincursor.c<br />~ /openrisc/trunk/bootloaders/orpmon/config.mk<br />~ /openrisc/trunk/bootloaders/orpmon/drivers/tick.c<br />~ /openrisc/trunk/bootloaders/orpmon/drivers/uart.c<br />~ /openrisc/trunk/bootloaders/orpmon/flash.ld<br />~ /openrisc/trunk/bootloaders/orpmon/include/board.h<br />~ /openrisc/trunk/bootloaders/orpmon/include/build.h<br />~ /openrisc/trunk/bootloaders/orpmon/include/common.h<br />~ /openrisc/trunk/bootloaders/orpmon/include/flash.h<br />- /openrisc/trunk/bootloaders/orpmon/include/spincursor.h<br />~ /openrisc/trunk/bootloaders/orpmon/ram.ld<br />~ /openrisc/trunk/bootloaders/orpmon/reset.S<br />~ /openrisc/trunk/bootloaders/orpmon/services/Makefile<br />~ /openrisc/trunk/bootloaders/orpmon/sim.cfg<br /> julius Sat, 08 Jan 2011 11:26:04 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc_me&path=%2Fopenrisc%2F&rev=467
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