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https://opencores.org/websvn//websvn/listing?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fbench%2Fsysc%2Fsrc%2F&
Sat, 09 May 2026 11:30:02 +0100
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sysc: avoid using orpsoc internal classes directly
The problem with using ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fbench%2Fsysc%2Fsrc%2F&rev=862
<div><strong>Rev 862 - stekern</strong> (2 file(s) modified)</div><div>sysc: avoid using orpsoc internal classes directly<br />
<br />
The problem with using ...</div>~ /openrisc/trunk/orpsocv2/bench/sysc/include/OrpsocAccess.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocAccess.cpp<br />
stekern
Wed, 03 Jul 2013 02:46:44 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fbench%2Fsysc%2Fsrc%2F&rev=862
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sysc: include unistd.h
write, read, pipe et al are declared in ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fbench%2Fsysc%2Fsrc%2F&rev=861
<div><strong>Rev 861 - stekern</strong> (4 file(s) modified)</div><div>sysc: include unistd.h<br />
<br />
write, read, pipe et al are declared in ...</div>~ /openrisc/trunk/orpsocv2/bench/sysc/src/GdbServerSC.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/RspConnection.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/UartSC.cpp<br />
stekern
Wed, 03 Jul 2013 02:46:42 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fbench%2Fsysc%2Fsrc%2F&rev=861
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ORPSoC's System C UART model can now accept input from ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fbench%2Fsysc%2Fsrc%2F&rev=500
<div><strong>Rev 500 - julius</strong> (5 file(s) modified)</div><div>ORPSoC's System C UART model can now accept input from ...</div>~ /openrisc/trunk/orpsocv2/bench/sysc/include/UartSC.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocMain.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/UartSC.cpp<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sim/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/sim/bin/Makefile<br />
julius
Thu, 10 Mar 2011 15:22:20 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fbench%2Fsysc%2Fsrc%2F&rev=500
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ORPSoC SystemC wrapper updates, monitor output more similar to or1ksim.
RAM ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fbench%2Fsysc%2Fsrc%2F&rev=462
<div><strong>Rev 462 - julius</strong> (53 file(s) modified)</div><div>ORPSoC SystemC wrapper updates, monitor output more similar to or1ksim.<br />
<br />
RAM ...</div>~ /openrisc/trunk/orpsocv2/bench/sysc/include/coff.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/DebugUnitSC.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/elf.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/GdbServerSC.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/JtagDriverSC.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/JtagSC.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/JtagSC_includes.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/MemCache.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/MemoryLoad.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/MpHash.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/Or1200MonitorSC.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/OrpsocAccess.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/OrpsocMain.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/ResetSC.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/RspConnection.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/RspPacket.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/SprCache.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/TapAction.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/TapActionDRScan.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/TapActionIRScan.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/TapActionReset.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/TapStateMachine.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/TraceSC.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/UartSC.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/Utils.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/DebugUnitSC.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/GdbServerSC.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/JtagDriverSC.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/JtagSC.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/MemCache.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/MemoryLoad.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/MpHash.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocAccess.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocMain.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/ResetSC.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/RspConnection.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/RspPacket.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/SprCache.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/TapAction.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/TapActionDRScan.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/TapActionIRScan.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/TapActionReset.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/TapStateMachine.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/TraceSC.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/UartSC.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/Utils.cpp<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/include/or1200_defines.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_dpram.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_rfram_generic.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ram_wb/ram_wb_b3.v<br />+ /openrisc/trunk/orpsocv2/sw/tests/or1200/board/or1200-mmu.c<br />~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-mmu.c<br />
julius
Fri, 07 Jan 2011 06:51:10 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fbench%2Fsysc%2Fsrc%2F&rev=462
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ORPSoC update
Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fbench%2Fsysc%2Fsrc%2F&rev=439
<div><strong>Rev 439 - julius</strong> (45 file(s) modified)</div><div>ORPSoC update<br />
<br />
Ethernet MAC synthesis issues with Actel Synplify D-2009.12A<br />
Ethernet MAC ...</div>~ /openrisc/trunk/orpsocv2/bench/sysc/include/OrpsocAccess.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocAccess.cpp<br />~ /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v<br />~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/backend/par/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/bench/verilog/include/eth_stim.v<br />~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include/ethmac_defines.v<br />~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include/orpsoc-params.v<br />~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/orpsoc_top/orpsoc_top.v<br />~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/syn/synplify/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/include/eth_stim.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/include/ethmac_defines.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/orpsoc_top/orpsoc_top.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/xilinx_ddr2/xilinx_ddr2.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/xilinx_ddr2/xilinx_ddr2_if.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/board/include/board.h<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/syn/xst/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/doc/orpsoc.texi<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/ethmac.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_clockgen.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_fifo.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_miim.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_receivecontrol.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_registers.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_rxcounters.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_rxethmac.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_rxstatem.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_shiftreg.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_spram_256x32.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_transmitcontrol.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_txcounters.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_txethmac.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_wishbone.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/include/ethmac_defines.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/orpsoc_top/orpsoc_top.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ram_wb/ram_wb.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ram_wb/ram_wb_b3.v<br />~ /openrisc/trunk/orpsocv2/sw/drivers/or1200/link.ld<br />~ /openrisc/trunk/orpsocv2/sw/tests/ethmac/sim/ethmac-rx.c<br />~ /openrisc/trunk/orpsocv2/sw/tests/ethmac/sim/ethmac-rxtx.c<br />~ /openrisc/trunk/orpsocv2/sw/tests/ethmac/sim/ethmac-tx.c<br />+ /openrisc/trunk/orpsocv2/sw/tests/or1200/board/or1200-div.c<br />+ /openrisc/trunk/orpsocv2/sw/tests/or1200/board/or1200-mul.c<br />~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-dctest.c<br />~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-mmu.c<br />+ /openrisc/trunk/orpsocv2/sw/tests/uart/sim/uart-interruptloopback.c<br />
julius
Mon, 06 Dec 2010 15:22:50 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fbench%2Fsysc%2Fsrc%2F&rev=439
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ORPSoC updates
OR1200 multiply/MAC/division unit update with serial multiply and
divide ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fbench%2Fsysc%2Fsrc%2F&rev=435
<div><strong>Rev 435 - julius</strong> (15 file(s) modified)</div><div>ORPSoC updates<br />
OR1200 multiply/MAC/division unit update with serial multiply and <br />
divide ...</div>~ /openrisc/trunk/orpsocv2/bench/sysc/include/Or1200MonitorSC.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp<br />~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include/or1200_defines.v<br />- /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/ddr2_mig<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/include/or1200_defines.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/syn/xst/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/include/or1200_defines.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_alu.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_cpu.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_gmultp2_32x32.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_mult_mac.v<br />~ /openrisc/trunk/orpsocv2/sim/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/sw/tests/ethmac/board/ethmac-ping.c<br />~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-div.c<br />+ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-mul.c<br />
julius
Tue, 30 Nov 2010 00:08:53 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fbench%2Fsysc%2Fsrc%2F&rev=435
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ORPSoC update:
GDB servers in VPI and System C model updated ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fbench%2Fsysc%2Fsrc%2F&rev=425
<div><strong>Rev 425 - julius</strong> (32 file(s) modified)</div><div>ORPSoC update:<br />
<br />
GDB servers in VPI and System C model updated ...</div>~ /openrisc/trunk/orpsocv2/bench/sysc/src/GdbServerSC.cpp<br />~ /openrisc/trunk/orpsocv2/bench/verilog/vpi/c/gdb.c<br />~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/Makefile<br />+ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/versatile_fifo_dual_port_ram_dc_sw.v<br />~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/Makefile.inc<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/README<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sim/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/doc/orpsoc.texi<br />~ /openrisc/trunk/orpsocv2/sim/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/sim/bin/or1ksim-orpsocv2.cfg<br />~ /openrisc/trunk/orpsocv2/sw/apps/testfloat/fail.c<br />~ /openrisc/trunk/orpsocv2/sw/apps/testfloat/random.c<br />~ /openrisc/trunk/orpsocv2/sw/apps/testfloat/testfloat.c<br />~ /openrisc/trunk/orpsocv2/sw/apps/testfloat/testFunction.c<br />~ /openrisc/trunk/orpsocv2/sw/apps/testfloat/testLoops.c<br />~ /openrisc/trunk/orpsocv2/sw/apps/testfloat/testsoftfloat.c<br />~ /openrisc/trunk/orpsocv2/sw/apps/testfloat/writeHex.c<br />~ /openrisc/trunk/orpsocv2/sw/drivers/or1200/crt0.S<br />~ /openrisc/trunk/orpsocv2/sw/Makefile.inc<br />~ /openrisc/trunk/orpsocv2/sw/tests/ethmac/board/ethmac-ping.c<br />~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-basic.S<br />~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-cbasic.c<br />~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-dctest.c<br />~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-except.S<br />~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-ffl1.S<br />~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-float.c<br />~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-fp.S<br />~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-linkregtest.S<br />~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-mac.S<br />~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-maci.S<br />~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-mmu.c<br />~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-ticksyscall.S<br />
julius
Tue, 16 Nov 2010 23:49:00 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fbench%2Fsysc%2Fsrc%2F&rev=425
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ORPSoC big upgrade - intermediate check in. Lots still missing. ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fbench%2Fsysc%2Fsrc%2F&rev=403
<div><strong>Rev 403 - julius</strong> (60 file(s) modified)</div><div>ORPSoC big upgrade - intermediate check in. Lots still missing. ...</div>~ /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocAccess.cpp<br />~ /openrisc/trunk/orpsocv2/bench/verilog/AT26DFxxx.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/include<br />+ /openrisc/trunk/orpsocv2/bench/verilog/include/orpsoc-testbench-defines.v<br />+ /openrisc/trunk/orpsocv2/bench/verilog/include/timescale.v<br />~ /openrisc/trunk/orpsocv2/bench/verilog/mt48lc16m16a2.v<br />~ /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v<br />- /openrisc/trunk/orpsocv2/bench/verilog/orpsoc-testbench-defines.v<br />~ /openrisc/trunk/orpsocv2/bench/verilog/orpsoc_testbench.v<br />~ /openrisc/trunk/orpsocv2/bench/verilog/smii_phy.v<br />- /openrisc/trunk/orpsocv2/bench/verilog/timescale.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_clockgen.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_crc.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_fifo.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_maccontrol.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_macstatus.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_miim.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_outputcontrol.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_random.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_receivecontrol.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_register.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_registers.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_rxaddrcheck.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_rxcounters.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_rxethmac.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_rxstatem.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_shiftreg.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_spram_256x32.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_transmitcontrol.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_txcounters.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_txethmac.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_txstatem.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/eth/eth_wishbone.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/include/eth_defines.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/include/or1200_defines.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/include/orpsoc-defines.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_alu.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_cpu.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_ctrl.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/orpsoc_top/orpsoc_top.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/smii/smii_txrx.v<br />- /openrisc/trunk/orpsocv2/rtl/verilog/wb_conbus<br />+ /openrisc/trunk/orpsocv2/sim/bin/definesgen.inc<br />- /openrisc/trunk/orpsocv2/sim/bin/icarus.scr<br />~ /openrisc/trunk/orpsocv2/sim/bin/Makefile<br />- /openrisc/trunk/orpsocv2/sim/bin/modelsim.scr<br />- /openrisc/trunk/orpsocv2/sim/bin/verilator.scr<br />~ /openrisc/trunk/orpsocv2/sw/board/include/board.h<br />~ /openrisc/trunk/orpsocv2/sw/bootrom/bootrom.S<br />- /openrisc/trunk/orpsocv2/sw/drivers/i2c_host_slave<br />+ /openrisc/trunk/orpsocv2/sw/drivers/i2c_master_slave<br />~ /openrisc/trunk/orpsocv2/sw/drivers/i2c_master_slave/i2c_master_slave.c<br />~ /openrisc/trunk/orpsocv2/sw/drivers/i2c_master_slave/include/i2c_master_slave.h<br />~ /openrisc/trunk/orpsocv2/sw/Makefile.inc<br />~ /openrisc/trunk/orpsocv2/sw/tests/eth/sim/Makefile<br />+ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-ffl1.S<br />~ /openrisc/trunk/orpsocv2/sw/tests/sdram/sim/sdram-rows.c<br />~ /openrisc/trunk/orpsocv2/sw/tests/spi/sim/Makefile<br />~ /openrisc/trunk/orpsocv2/sw/tests/spi/sim/spi-interrupt.c<br />~ /openrisc/trunk/orpsocv2/sw/tests/spi/sim/spi-simple.c<br />
julius
Mon, 01 Nov 2010 19:26:38 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fbench%2Fsysc%2Fsrc%2F&rev=403
-
ORPSoCv2:
doc/ path added, with Texinfo documentation. Still a work ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fbench%2Fsysc%2Fsrc%2F&rev=397
<div><strong>Rev 397 - julius</strong> (44 file(s) modified)</div><div>ORPSoCv2:<br />
<br />
doc/ path added, with Texinfo documentation. Still a work ...</div>~ /openrisc/trunk/orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocMain.cpp<br />~ /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v<br />~ /openrisc/trunk/orpsocv2/bench/verilog/orpsoc_testbench.v<br />~ /openrisc/trunk/orpsocv2/bench/verilog/vpi/c/gdb.c<br />~ /openrisc/trunk/orpsocv2/bench/verilog/vpi/c/jp_vpi.c<br />~ /openrisc/trunk/orpsocv2/bench/verilog/vpi/c/Makefile<br />~ /openrisc/trunk/orpsocv2/bench/verilog/vpi/c/rsp-rtl_sim.c<br />~ /openrisc/trunk/orpsocv2/bench/verilog/vpi/c/rsp-rtl_sim.h<br />~ /openrisc/trunk/orpsocv2/bench/verilog/vpi/c/rsp-vpi.h<br />~ /openrisc/trunk/orpsocv2/bench/verilog/vpi/verilog/vpi_debug_defines.v<br />~ /openrisc/trunk/orpsocv2/bench/verilog/vpi/verilog/vpi_debug_module.v<br />+ /openrisc/trunk/orpsocv2/doc<br />+ /openrisc/trunk/orpsocv2/doc/aclocal.m4<br />+ /openrisc/trunk/orpsocv2/doc/autom4te.cache<br />+ /openrisc/trunk/orpsocv2/doc/autom4te.cache/output.0<br />+ /openrisc/trunk/orpsocv2/doc/autom4te.cache/output.1<br />+ /openrisc/trunk/orpsocv2/doc/autom4te.cache/output.2<br />+ /openrisc/trunk/orpsocv2/doc/autom4te.cache/requests<br />+ /openrisc/trunk/orpsocv2/doc/autom4te.cache/traces.0<br />+ /openrisc/trunk/orpsocv2/doc/autom4te.cache/traces.1<br />+ /openrisc/trunk/orpsocv2/doc/autom4te.cache/traces.2<br />+ /openrisc/trunk/orpsocv2/doc/config.log<br />+ /openrisc/trunk/orpsocv2/doc/config.status<br />+ /openrisc/trunk/orpsocv2/doc/config.texi<br />+ /openrisc/trunk/orpsocv2/doc/configure<br />+ /openrisc/trunk/orpsocv2/doc/configure.in<br />+ /openrisc/trunk/orpsocv2/doc/fdl-1.2.texi<br />+ /openrisc/trunk/orpsocv2/doc/install-sh<br />+ /openrisc/trunk/orpsocv2/doc/Makefile<br />+ /openrisc/trunk/orpsocv2/doc/Makefile.am<br />+ /openrisc/trunk/orpsocv2/doc/Makefile.in<br />+ /openrisc/trunk/orpsocv2/doc/missing<br />+ /openrisc/trunk/orpsocv2/doc/orpsoc.texi<br />+ /openrisc/trunk/orpsocv2/doc/texinfo.tex<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/include/orpsoc-defines.v<br />~ /openrisc/trunk/orpsocv2/sim/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/sw/apps/dhry/dhry.c<br />~ /openrisc/trunk/orpsocv2/sw/apps/dhry/Makefile<br />~ /openrisc/trunk/orpsocv2/sw/apps/spiflash/Makefile<br />~ /openrisc/trunk/orpsocv2/sw/apps/testfloat/Makefile<br />~ /openrisc/trunk/orpsocv2/sw/Makefile.inc<br />+ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-maci.S<br />~ /openrisc/trunk/orpsocv2/sw/tests/uart/sim/uart-interrupt.c<br />
julius
Sat, 30 Oct 2010 13:51:16 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fbench%2Fsysc%2Fsrc%2F&rev=397
-
ORPSoC's RTL code fixed to pass linting by Verilator.
ORPSoC's debug ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fbench%2Fsysc%2Fsrc%2F&rev=363
<div><strong>Rev 363 - julius</strong> (38 file(s) modified)</div><div>ORPSoC's RTL code fixed to pass linting by Verilator.<br />
<br />
ORPSoC's debug ...</div>~ /openrisc/trunk/orpsocv2/bench/sysc/include/OrpsocAccess.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocAccess.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocMain.cpp<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/arbiter/arbiter_ibus.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/clkgen/clkgen.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_cpu.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_if.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_wb.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/include/dbg_cpu_defines.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/include/dbg_wb_defines.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/include/or1200_defines.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/include/orpsoc-defines.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/jtag_tap/jtag_tap.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_alu.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_ctrl.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_dc_fsm.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_dmmu_top.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_du.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_except.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_freeze.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_genpc.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_lsu.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_mult_mac.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_operandmuxes.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_reg2mem.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_sprs.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_top.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_wbmux.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_wb_biu.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/orpsoc_top/orpsoc_top.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart_receiver.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart_regs.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart_rfifo.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart_tfifo.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart_transmitter.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/wb_ram_b3/wb_ram_b3.v<br />~ /openrisc/trunk/orpsocv2/sim/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/sw/dhry/Makefile<br />
julius
Sun, 12 Sep 2010 07:57:53 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fbench%2Fsysc%2Fsrc%2F&rev=363
-
ORPSoCv2 verilator building working again. Board build fixes to follow
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fbench%2Fsysc%2Fsrc%2F&rev=362
<div><strong>Rev 362 - julius</strong> (7 file(s) modified)</div><div>ORPSoCv2 verilator building working again. Board build fixes to follow</div>~ /openrisc/trunk/orpsocv2/bench/sysc/include/OrpsocAccess.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocAccess.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocMain.cpp<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/arbiter/arbiter_dbus.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/clkgen/clkgen.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/wb_ram_b3/wb_ram_b3.v<br />~ /openrisc/trunk/orpsocv2/sim/bin/Makefile<br />
julius
Fri, 10 Sep 2010 22:42:38 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fbench%2Fsysc%2Fsrc%2F&rev=362
-
Fixed ORPSoCv2 Dhrystone test, rewrote timer interrut
* sw/support/crt0.S: Tick timer ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fbench%2Fsysc%2Fsrc%2F&rev=354
<div><strong>Rev 354 - julius</strong> (15 file(s) modified)</div><div>Fixed ORPSoCv2 Dhrystone test, rewrote timer interrut<br />
<br />
* sw/support/crt0.S: Tick timer ...</div>~ /openrisc/trunk/orpsocv2/bench/sysc/include/OrpsocMain.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocMain.cpp<br />~ /openrisc/trunk/orpsocv2/bench/verilog/orpsoc_testbench.v<br />~ /openrisc/trunk/orpsocv2/bench/verilog/orpsoc_testbench_defines.v<br />~ /openrisc/trunk/orpsocv2/bench/verilog/uart_decoder.v<br />~ /openrisc/trunk/orpsocv2/sim/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/sim/bin/or1ksim-orpsocv2.cfg<br />~ /openrisc/trunk/orpsocv2/sw/dhry/dhry.c<br />- /openrisc/trunk/orpsocv2/sw/dhry/dhry.h<br />~ /openrisc/trunk/orpsocv2/sw/dhry/Makefile<br />~ /openrisc/trunk/orpsocv2/sw/include/board.h<br />+ /openrisc/trunk/orpsocv2/sw/include/dhry.h<br />~ /openrisc/trunk/orpsocv2/sw/or1200/or1200-simple.c<br />~ /openrisc/trunk/orpsocv2/sw/support/crt0.S<br />
julius
Wed, 08 Sep 2010 18:00:48 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fbench%2Fsysc%2Fsrc%2F&rev=354
-
OR1200 RTL and ORPSoCv2 update, fixing Verilator build capability. ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fbench%2Fsysc%2Fsrc%2F&rev=353
<div><strong>Rev 353 - julius</strong> (19 file(s) modified)</div><div>OR1200 RTL and ORPSoCv2 update, fixing Verilator build capability.<br />
* or1200/rtl/verilog/or1200_sprs.v: ...</div>~ /openrisc/trunk/bootloaders/orpmon/config.mk<br />~ /openrisc/trunk/bootloaders/orpmon/flash.ld<br />~ /openrisc/trunk/bootloaders/orpmon/include/build.h<br />~ /openrisc/trunk/bootloaders/orpmon/ram.ld<br />~ /openrisc/trunk/bootloaders/orpmon/reset.S<br />~ /openrisc/trunk/docs/openrisc1200_supplementary_prm.odt<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_ctrl.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_except.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_sprs.v<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/Or1200MonitorSC.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/OrpsocAccess.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocAccess.cpp<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_ctrl.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_except.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_sprs.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/components/wb_ram_b3/wb_ram_b3.v<br />~ /openrisc/trunk/or_debug_proxy/Makefile<br />~ /openrisc/trunk/or_debug_proxy/src/gdb.c<br />
julius
Wed, 08 Sep 2010 15:42:13 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fbench%2Fsysc%2Fsrc%2F&rev=353
-
ORPSoC cycle accurate trace generation now compatible with latest version ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fbench%2Fsysc%2Fsrc%2F&rev=70
<div><strong>Rev 70 - julius</strong> (3 file(s) modified)</div><div>ORPSoC cycle accurate trace generation now compatible with latest version ...</div>~ /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocMain.cpp<br />~ /openrisc/trunk/orpsocv2/sim/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/sim/bin/verilator.scr<br />
julius
Fri, 19 Feb 2010 04:22:14 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fbench%2Fsysc%2Fsrc%2F&rev=70
-
Fixed the simulator-assisted printf l.nop in cycle accurate, and supporting ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fbench%2Fsysc%2Fsrc%2F&rev=66
<div><strong>Rev 66 - julius</strong> (8 file(s) modified)</div><div>Fixed the simulator-assisted printf l.nop in cycle accurate, and supporting ...</div>~ /openrisc/trunk/orpsocv2/bench/sysc/include/Or1200MonitorSC.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/OrpsocAccess.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/GdbServerSC.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/MemoryLoad.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocAccess.cpp<br />~ /openrisc/trunk/orpsocv2/sim/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/sw/support/support.c<br />
julius
Wed, 27 Jan 2010 10:49:09 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fbench%2Fsysc%2Fsrc%2F&rev=66
-
Trying to fix the system c model jtagsc.h checkout problem, ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fbench%2Fsysc%2Fsrc%2F&rev=64
<div><strong>Rev 64 - julius</strong> (10 file(s) modified)</div><div>Trying to fix the system c model jtagsc.h checkout problem, ...</div>~ /openrisc/trunk/orpsocv2/bench/sysc/include/DebugUnitSC.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/GdbServerSC.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/JtagDriverSC.h<br />- /openrisc/trunk/orpsocv2/bench/sysc/include/jtagsc.h<br />+ /openrisc/trunk/orpsocv2/bench/sysc/include/JtagSC_includes.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/Or1200MonitorSC.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/Modules.make<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocMain.cpp<br />~ /openrisc/trunk/orpsocv2/sim/bin/Makefile<br />
julius
Wed, 20 Jan 2010 09:36:54 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fbench%2Fsysc%2Fsrc%2F&rev=64
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Finally adding RSP server to cycle accurate model, based on ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fbench%2Fsysc%2Fsrc%2F&rev=63
<div><strong>Rev 63 - julius</strong> (49 file(s) modified)</div><div>Finally adding RSP server to cycle accurate model, based on ...</div>+ /openrisc/trunk/orpsocv2/bench/sysc/include/DebugUnitSC.h<br />+ /openrisc/trunk/orpsocv2/bench/sysc/include/GdbServerSC.h<br />+ /openrisc/trunk/orpsocv2/bench/sysc/include/JtagDriverSC.h<br />+ /openrisc/trunk/orpsocv2/bench/sysc/include/JtagSC.h<br />+ /openrisc/trunk/orpsocv2/bench/sysc/include/jtagsc.h<br />+ /openrisc/trunk/orpsocv2/bench/sysc/include/MemCache.h<br />+ /openrisc/trunk/orpsocv2/bench/sysc/include/MpHash.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/Or1200MonitorSC.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/OrpsocAccess.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/OrpsocMain.h<br />+ /openrisc/trunk/orpsocv2/bench/sysc/include/RspConnection.h<br />+ /openrisc/trunk/orpsocv2/bench/sysc/include/RspPacket.h<br />+ /openrisc/trunk/orpsocv2/bench/sysc/include/SprCache.h<br />+ /openrisc/trunk/orpsocv2/bench/sysc/include/TapAction.h<br />+ /openrisc/trunk/orpsocv2/bench/sysc/include/TapActionDRScan.h<br />+ /openrisc/trunk/orpsocv2/bench/sysc/include/TapActionIRScan.h<br />+ /openrisc/trunk/orpsocv2/bench/sysc/include/TapActionReset.h<br />+ /openrisc/trunk/orpsocv2/bench/sysc/include/TapStateMachine.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/UartSC.h<br />+ /openrisc/trunk/orpsocv2/bench/sysc/include/Utils.h<br />+ /openrisc/trunk/orpsocv2/bench/sysc/src/DebugUnitSC.cpp<br />+ /openrisc/trunk/orpsocv2/bench/sysc/src/GdbServerSC.cpp<br />+ /openrisc/trunk/orpsocv2/bench/sysc/src/JtagDriverSC.cpp<br />+ /openrisc/trunk/orpsocv2/bench/sysc/src/JtagSC.cpp<br />+ /openrisc/trunk/orpsocv2/bench/sysc/src/MemCache.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/MemoryLoad.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/Modules.make<br />+ /openrisc/trunk/orpsocv2/bench/sysc/src/MpHash.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocAccess.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocMain.cpp<br />+ /openrisc/trunk/orpsocv2/bench/sysc/src/RspConnection.cpp<br />+ /openrisc/trunk/orpsocv2/bench/sysc/src/RspPacket.cpp<br />+ /openrisc/trunk/orpsocv2/bench/sysc/src/SprCache.cpp<br />+ /openrisc/trunk/orpsocv2/bench/sysc/src/TapAction.cpp<br />+ /openrisc/trunk/orpsocv2/bench/sysc/src/TapActionDRScan.cpp<br />+ /openrisc/trunk/orpsocv2/bench/sysc/src/TapActionIRScan.cpp<br />+ /openrisc/trunk/orpsocv2/bench/sysc/src/TapActionReset.cpp<br />+ /openrisc/trunk/orpsocv2/bench/sysc/src/TapStateMachine.cpp<br />+ /openrisc/trunk/orpsocv2/bench/sysc/src/Utils.cpp<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/components/debug_if/dbg_cpu.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_ctrl.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_du.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/components/wb_conbus/wb_conbus_top.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200_defines.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/orpsoc_top.v<br />~ /openrisc/trunk/orpsocv2/sim/bin/Makefile<br />+ /openrisc/trunk/orpsocv2/sw/utils/binlog2readable.cpp<br />~ /openrisc/trunk/orpsocv2/sw/utils/Makefile<br />
julius
Sun, 10 Jan 2010 12:31:11 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fbench%2Fsysc%2Fsrc%2F&rev=63
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ORPSoC execution logs created by event sim and cycle accurate ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fbench%2Fsysc%2Fsrc%2F&rev=57
<div><strong>Rev 57 - julius</strong> (4 file(s) modified)</div><div>ORPSoC execution logs created by event sim and cycle accurate ...</div>~ /openrisc/trunk/orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp<br />~ /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200_defines.v<br />~ /openrisc/trunk/orpsocv2/sim/bin/Makefile<br />
julius
Tue, 24 Nov 2009 12:48:15 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fbench%2Fsysc%2Fsrc%2F&rev=57
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Fixed incorrect commandline option for ORPSoC and main makefile setting
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fbench%2Fsysc%2Fsrc%2F&rev=53
<div><strong>Rev 53 - julius</strong> (2 file(s) modified)</div><div>Fixed incorrect commandline option for ORPSoC and main makefile setting</div>~ /openrisc/trunk/orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp<br />~ /openrisc/trunk/orpsocv2/sim/bin/Makefile<br />
julius
Fri, 16 Oct 2009 12:34:44 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fbench%2Fsysc%2Fsrc%2F&rev=53
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ORPSoC update - ability to dump part or all of ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fbench%2Fsysc%2Fsrc%2F&rev=52
<div><strong>Rev 52 - julius</strong> (5 file(s) modified)</div><div>ORPSoC update - ability to dump part or all of ...</div>~ /openrisc/trunk/orpsocv2/bench/sysc/include/MemoryLoad.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/Or1200MonitorSC.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/include/OrpsocMain.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocMain.cpp<br />
julius
Thu, 15 Oct 2009 16:31:10 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fbench%2Fsysc%2Fsrc%2F&rev=52
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