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openrisc WebSVN RSS feed - openrisc https://opencores.org/websvn//websvn/listing?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Frtl%2F& Tue, 16 Jun 2026 16:56:26 +0100 FeedCreator 1.7.2 Declare pcreg_boot before usage When things were moved around in rev ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Frtl%2F&rev=853 <div><strong>Rev 853 - olof</strong> (1 file(s) modified)</div><div>Declare pcreg_boot before usage<br /> <br /> When things were moved around in rev ...</div>~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_genpc.v<br /> olof Thu, 08 Nov 2012 19:17:37 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Frtl%2F&rev=853 or1200_genpc: fix ipcu_cycstb_o generation In some circumstances the CPU is still ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Frtl%2F&rev=850 <div><strong>Rev 850 - stekern</strong> (2 file(s) modified)</div><div>or1200_genpc: fix ipcu_cycstb_o generation<br /> <br /> In some circumstances the CPU is still ...</div>~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_cpu.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_genpc.v<br /> stekern Thu, 25 Oct 2012 03:30:22 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Frtl%2F&rev=850 or1200: Fix for cache bug related to first_{hit|miss}_ack Under certain circumstances, ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Frtl%2F&rev=849 <div><strong>Rev 849 - stekern</strong> (2 file(s) modified)</div><div>or1200: Fix for cache bug related to first_{hit|miss}_ack<br /> <br /> Under certain circumstances, ...</div>~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_dc_fsm.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_ic_fsm.v<br /> stekern Thu, 25 Oct 2012 03:30:20 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Frtl%2F&rev=849 or1200: l.lws support Using the l.lws instruction doesn't work currently. It simply ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Frtl%2F&rev=848 <div><strong>Rev 848 - stekern</strong> (2 file(s) modified)</div><div>or1200: l.lws support<br /> <br /> Using the l.lws instruction doesn't work currently.<br /> It simply ...</div>~ /openrisc/trunk/orpsocv2/rtl/verilog/include/or1200_defines.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_ctrl.v<br /> stekern Thu, 25 Oct 2012 03:30:18 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Frtl%2F&rev=848 OR1200 debug unit: prevent deadlock when trap instruction stalls As per ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Frtl%2F&rev=815 <div><strong>Rev 815 - yannv</strong> (2 file(s) modified)</div><div>OR1200 debug unit: prevent deadlock when trap instruction stalls<br /> <br /> As per ...</div>~ /openrisc/trunk/or1200/rtl/verilog/or1200_du.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_du.v<br /> yannv Thu, 04 Oct 2012 09:52:36 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Frtl%2F&rev=815 orpsoc/or1200: Set correct PC after reset when parameter boot_adr is ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Frtl%2F&rev=814 <div><strong>Rev 814 - olof</strong> (3 file(s) modified)</div><div>orpsoc/or1200: Set correct PC after reset when parameter boot_adr is ...</div>~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_cpu.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_genpc.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_top.v<br /> olof Wed, 19 Sep 2012 17:06:03 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Frtl%2F&rev=814 ORPSoC: Commit for bug 85 - add DSX support to ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Frtl%2F&rev=807 <div><strong>Rev 807 - julius</strong> (6 file(s) modified)</div><div>ORPSoC: Commit for bug 85 - add DSX support to ...</div>~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_cpu.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_except.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_sprs.v<br />~ /openrisc/trunk/orpsocv2/sim/bin/Makefile<br />+ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-dsx.S<br />+ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-dsxinsn.S<br /> julius Sat, 26 May 2012 23:26:42 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Frtl%2F&rev=807 ORPSoC: Fix for bug 90 - EPCR on range exception ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Frtl%2F&rev=805 <div><strong>Rev 805 - julius</strong> (2 file(s) modified)</div><div>ORPSoC: Fix for bug 90 - EPCR on range exception ...</div>~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_except.v<br />+ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-range.S<br /> julius Sat, 26 May 2012 23:09:51 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Frtl%2F&rev=805 ORPSoC: Fix for bug 91, l.sub not setting overflow flag ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Frtl%2F&rev=803 <div><strong>Rev 803 - julius</strong> (2 file(s) modified)</div><div>ORPSoC: Fix for bug 91, l.sub not setting overflow flag ...</div>~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_alu.v<br />~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-ov.S<br /> julius Sat, 26 May 2012 22:56:30 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Frtl%2F&rev=803 ORPSoC: Fix bug 88 http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=88 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Frtl%2F&rev=801 <div><strong>Rev 801 - julius</strong> (2 file(s) modified)</div><div>ORPSoC: Fix bug 88<br /> <br /> <a href="http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=88" target="_blank">http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=88</a></div>~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_alu.v<br />~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-ext.S<br /> julius Mon, 21 May 2012 17:41:34 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Frtl%2F&rev=801 ORPSoC, or1200: split out or1200_fpu_intfloat_conv_except module into own file Fixes lint ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Frtl%2F&rev=794 <div><strong>Rev 794 - julius</strong> (4 file(s) modified)</div><div>ORPSoC, or1200: split out or1200_fpu_intfloat_conv_except module into own file<br /> <br /> Fixes lint ...</div>~ /openrisc/trunk/or1200/rtl/verilog/or1200_fpu_intfloat_conv.v<br />+ /openrisc/trunk/or1200/rtl/verilog/or1200_fpu_intfloat_conv_except.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_fpu_intfloat_conv.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_fpu_intfloat_conv_except.v<br /> julius Wed, 18 Apr 2012 08:17:03 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Frtl%2F&rev=794 or1200: Patch from R Diez to remove l.cust5 signal from ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Frtl%2F&rev=788 <div><strong>Rev 788 - julius</strong> (2 file(s) modified)</div><div>or1200: Patch from R Diez to remove l.cust5 signal from ...</div>~ /openrisc/trunk/or1200/rtl/verilog/or1200_alu.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_alu.v<br /> julius Sat, 24 Mar 2012 18:13:15 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Frtl%2F&rev=788 Allow setting the boot address as an external parameter. If no ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Frtl%2F&rev=679 <div><strong>Rev 679 - olof</strong> (4 file(s) modified)</div><div>Allow setting the boot address as an external<br /> parameter. If no ...</div>~ /openrisc/trunk/or1200/rtl/verilog/or1200_immu_top.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_top.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_immu_top.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_top.v<br /> olof Wed, 29 Feb 2012 18:04:38 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Frtl%2F&rev=679 ORPSoC: Fix Bug 76 - Incorrect unsigned integer less-than compare ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Frtl%2F&rev=672 <div><strong>Rev 672 - julius</strong> (2 file(s) modified)</div><div>ORPSoC: Fix Bug 76 - Incorrect unsigned integer less-than compare ...</div>~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_alu.v<br />~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-sf.S<br /> julius Mon, 12 Dec 2011 22:32:30 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Frtl%2F&rev=672 ORPSoC: add CFI flash controller to ml501, sw driver, tests, ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Frtl%2F&rev=655 <div><strong>Rev 655 - julius</strong> (45 file(s) modified)</div><div>ORPSoC: add CFI flash controller to ml501, sw driver, tests, ...</div>+ /openrisc/trunk/orpsocv2/bench/verilog/include/cfi_flash_BankLib.h<br />+ /openrisc/trunk/orpsocv2/bench/verilog/include/cfi_flash_CUIcommandData.h<br />+ /openrisc/trunk/orpsocv2/bench/verilog/include/cfi_flash_data.h<br />+ /openrisc/trunk/orpsocv2/bench/verilog/include/cfi_flash_def.h<br />+ /openrisc/trunk/orpsocv2/bench/verilog/include/cfi_flash_TimingData.h<br />+ /openrisc/trunk/orpsocv2/bench/verilog/include/cfi_flash_UserData.h<br />+ /openrisc/trunk/orpsocv2/bench/verilog/x28fxxxp30.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/par/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/backend/par/bin/ml501.ucf<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/orpsoc_testbench.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/arbiter/arbiter_dbus.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/arbiter/arbiter_ibus.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/include/or1200_defines.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/include/orpsoc-defines.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/include/orpsoc-params.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/orpsoc_top/orpsoc_top.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/board/include/board.h<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/syn/xst/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/doc/orpsoc.texi<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/cfi_ctrl<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/cfi_ctrl/cfi_ctrl.v<br />+ /openrisc/trunk/orpsocv2/rtl/verilog/cfi_ctrl/cfi_ctrl_engine.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ram_wb/ram_wb_b3.v<br />~ /openrisc/trunk/orpsocv2/scripts/make/Makefile-sim-definesgen.inc<br />~ /openrisc/trunk/orpsocv2/scripts/make/Makefile-swrules.inc<br />+ /openrisc/trunk/orpsocv2/sw/apps/cfi_ctrl_programmer<br />+ /openrisc/trunk/orpsocv2/sw/apps/cfi_ctrl_programmer/cfi_ctrl_programmer.c<br />+ /openrisc/trunk/orpsocv2/sw/apps/cfi_ctrl_programmer/cfi_ctrl_programmer.ld<br />+ /openrisc/trunk/orpsocv2/sw/apps/cfi_ctrl_programmer/Makefile<br />+ /openrisc/trunk/orpsocv2/sw/drivers/cfi-ctrl<br />+ /openrisc/trunk/orpsocv2/sw/drivers/cfi-ctrl/cfi_ctrl.c<br />+ /openrisc/trunk/orpsocv2/sw/drivers/cfi-ctrl/include<br />+ /openrisc/trunk/orpsocv2/sw/drivers/cfi-ctrl/include/cfi_ctrl.h<br />+ /openrisc/trunk/orpsocv2/sw/drivers/cfi-ctrl/Makefile<br />~ /openrisc/trunk/orpsocv2/sw/lib/Makefile<br />~ /openrisc/trunk/orpsocv2/sw/Makefile.inc<br />+ /openrisc/trunk/orpsocv2/sw/tests/cfi_ctrl<br />+ /openrisc/trunk/orpsocv2/sw/tests/cfi_ctrl/board<br />+ /openrisc/trunk/orpsocv2/sw/tests/cfi_ctrl/board/cfi_ctrl-readid.c<br />+ /openrisc/trunk/orpsocv2/sw/tests/cfi_ctrl/board/cfi_ctrl-simple.c<br />+ /openrisc/trunk/orpsocv2/sw/tests/cfi_ctrl/board/Makefile<br />+ /openrisc/trunk/orpsocv2/sw/tests/cfi_ctrl/sim<br />+ /openrisc/trunk/orpsocv2/sw/tests/cfi_ctrl/sim/cfi_ctrl-readid.c<br />+ /openrisc/trunk/orpsocv2/sw/tests/cfi_ctrl/sim/cfi_ctrl-simple.c<br />+ /openrisc/trunk/orpsocv2/sw/tests/cfi_ctrl/sim/Makefile<br /> julius Sat, 22 Oct 2011 20:32:59 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Frtl%2F&rev=655 ORPSoC OR1200 fix and regression test for bug 51. signed-off Julius ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Frtl%2F&rev=619 <div><strong>Rev 619 - julius</strong> (2 file(s) modified)</div><div>ORPSoC OR1200 fix and regression test for bug 51.<br /> <br /> signed-off Julius ...</div>~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_alu.v<br />~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-sf.S<br /> julius Tue, 02 Aug 2011 21:06:40 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Frtl%2F&rev=619 Remove unused parameter Tp https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Frtl%2F&rev=618 <div><strong>Rev 618 - olof</strong> (16 file(s) modified)</div><div>Remove unused parameter Tp</div>~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_clockgen.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_crc.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_maccontrol.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_macstatus.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_miim.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_outputcontrol.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_random.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_receivecontrol.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_registers.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_rxaddrcheck.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_rxstatem.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_shiftreg.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_transmitcontrol.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_txcounters.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_txethmac.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_txstatem.v<br /> olof Tue, 02 Aug 2011 13:52:01 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Frtl%2F&rev=618 Fix white space in ethmac headers https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Frtl%2F&rev=570 <div><strong>Rev 570 - olof</strong> (20 file(s) modified)</div><div>Fix white space in ethmac headers</div>~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_clockgen.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_crc.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_maccontrol.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_macstatus.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_miim.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_outputcontrol.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_random.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_receivecontrol.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_register.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_registers.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_rxcounters.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_rxethmac.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_rxstatem.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_shiftreg.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_spram_256x32.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_transmitcontrol.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_txcounters.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_txethmac.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_txstatem.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_wishbone.v<br /> olof Mon, 18 Jul 2011 18:14:27 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Frtl%2F&rev=570 ORPSoC dbg_if fix for slow Wishbone slaves https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Frtl%2F&rev=547 <div><strong>Rev 547 - julius</strong> (1 file(s) modified)</div><div>ORPSoC dbg_if fix for slow Wishbone slaves</div>~ /openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_wb.v<br /> julius Wed, 01 Jun 2011 11:30:32 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Frtl%2F&rev=547 ORPSoC update: Fix WB B3 bursting termination on error in ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Frtl%2F&rev=546 <div><strong>Rev 546 - julius</strong> (1 file(s) modified)</div><div>ORPSoC update: Fix WB B3 bursting termination on error in ...</div>~ /openrisc/trunk/orpsocv2/rtl/verilog/ram_wb/ram_wb_b3.v<br /> julius Tue, 31 May 2011 18:48:18 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Frtl%2F&rev=546

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