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https://opencores.org/websvn//websvn/listing?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsw%2Flib%2Finclude%2F&
Mon, 06 Apr 2026 03:59:05 +0100
FeedCreator 1.7.2
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ORPSoC updates - or1200 monitor now has separate defines file, ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsw%2Flib%2Finclude%2F&rev=485
<div><strong>Rev 485 - julius</strong> (33 file(s) modified)</div><div>ORPSoC updates - or1200 monitor now has separate defines file, ...</div>+ /openrisc/trunk/orpsocv2/bench/verilog/include/or1200_monitor_defines.v<br />~ /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v<br />~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/orpsoc_top/orpsoc_top.v<br />~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/board/include/board.h<br />~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/Makefile.inc<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/include/eth_stim.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/include/ethmac_defines.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/board/include/board.h<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/tests<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/tests/ethmac<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/tests/ethmac/sim<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/tests/ethmac/sim/ethmac-rx.c<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/tests/ethmac/sim/ethmac-rxtx.c<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/tests/ethmac/sim/ethmac-rxtxcallresponse.c<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/tests/ethmac/sim/ethmac-tx.c<br />+ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/tests/ethmac/sim/Makefile<br />~ /openrisc/trunk/orpsocv2/doc/orpsoc.texi<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_fifo.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_wishbone.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/include/or1200_defines.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_dpram.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/orpsoc_top/orpsoc_top.v<br />~ /openrisc/trunk/orpsocv2/sim/bin/Makefile<br />~ /openrisc/trunk/orpsocv2/sw/board/include/board.h<br />~ /openrisc/trunk/orpsocv2/sw/drivers/or1200/crt0.S<br />~ /openrisc/trunk/orpsocv2/sw/drivers/simple-spi/simple-spi.c<br />~ /openrisc/trunk/orpsocv2/sw/drivers/uart/uart.c<br />~ /openrisc/trunk/orpsocv2/sw/lib/include/printf.h<br />~ /openrisc/trunk/orpsocv2/sw/lib/printf.c<br />~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-dctest.c<br />~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-mmu.c<br />- /openrisc/trunk/orpsocv2/sw/utils/marksec<br />- /openrisc/trunk/orpsocv2/sw/utils/merge2srec<br />
julius
Fri, 04 Feb 2011 09:33:38 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsw%2Flib%2Finclude%2F&rev=485
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ORPSoCv2 software rearrangement in progress. Basic tests should now run ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsw%2Flib%2Finclude%2F&rev=393
<div><strong>Rev 393 - julius</strong> (131 file(s) modified)</div><div>ORPSoCv2 software rearrangement in progress. Basic tests should now run ...</div>~ /openrisc/trunk/orpsocv2/sim/bin/Makefile<br />+ /openrisc/trunk/orpsocv2/sw/apps<br />+ /openrisc/trunk/orpsocv2/sw/apps/dhry<br />+ /openrisc/trunk/orpsocv2/sw/apps/dhry/dhry.h<br />+ /openrisc/trunk/orpsocv2/sw/apps/spiflash<br />+ /openrisc/trunk/orpsocv2/sw/apps/testfloat<br />+ /openrisc/trunk/orpsocv2/sw/board<br />+ /openrisc/trunk/orpsocv2/sw/board/include<br />+ /openrisc/trunk/orpsocv2/sw/board/include/board.h<br />~ /openrisc/trunk/orpsocv2/sw/bootrom/Makefile<br />- /openrisc/trunk/orpsocv2/sw/dhry<br />+ /openrisc/trunk/orpsocv2/sw/drivers<br />+ /openrisc/trunk/orpsocv2/sw/drivers/i2c_host_slave<br />+ /openrisc/trunk/orpsocv2/sw/drivers/i2c_host_slave/i2c_master_slave.c<br />+ /openrisc/trunk/orpsocv2/sw/drivers/i2c_host_slave/include<br />+ /openrisc/trunk/orpsocv2/sw/drivers/i2c_host_slave/include/i2c_master_slave.h<br />+ /openrisc/trunk/orpsocv2/sw/drivers/i2c_host_slave/Makefile<br />+ /openrisc/trunk/orpsocv2/sw/drivers/or1200<br />+ /openrisc/trunk/orpsocv2/sw/drivers/or1200/crt0.S<br />+ /openrisc/trunk/orpsocv2/sw/drivers/or1200/exceptions.c<br />+ /openrisc/trunk/orpsocv2/sw/drivers/or1200/include<br />+ /openrisc/trunk/orpsocv2/sw/drivers/or1200/include/int.h<br />+ /openrisc/trunk/orpsocv2/sw/drivers/or1200/include/or1200-utils.h<br />+ /openrisc/trunk/orpsocv2/sw/drivers/or1200/include/spr-defs.h<br />+ /openrisc/trunk/orpsocv2/sw/drivers/or1200/int.c<br />+ /openrisc/trunk/orpsocv2/sw/drivers/or1200/link.ld<br />+ /openrisc/trunk/orpsocv2/sw/drivers/or1200/or1200-mmu.S<br />+ /openrisc/trunk/orpsocv2/sw/drivers/or1200/or1200-utils.c<br />+ /openrisc/trunk/orpsocv2/sw/drivers/simple-spi<br />+ /openrisc/trunk/orpsocv2/sw/drivers/simple-spi/include<br />+ /openrisc/trunk/orpsocv2/sw/drivers/simple-spi/include/simple-spi.h<br />+ /openrisc/trunk/orpsocv2/sw/drivers/simple-spi/Makefile<br />+ /openrisc/trunk/orpsocv2/sw/drivers/simple-spi/simple-spi.c<br />+ /openrisc/trunk/orpsocv2/sw/drivers/uart<br />+ /openrisc/trunk/orpsocv2/sw/drivers/uart/include<br />+ /openrisc/trunk/orpsocv2/sw/drivers/uart/include/uart.h<br />+ /openrisc/trunk/orpsocv2/sw/drivers/uart/Makefile<br />+ /openrisc/trunk/orpsocv2/sw/drivers/uart/uart.c<br />- /openrisc/trunk/orpsocv2/sw/include/board.h<br />- /openrisc/trunk/orpsocv2/sw/include/dhry.h<br />- /openrisc/trunk/orpsocv2/sw/include/int.h<br />- /openrisc/trunk/orpsocv2/sw/include/or32-utils.h<br />- /openrisc/trunk/orpsocv2/sw/include/printf.h<br />- /openrisc/trunk/orpsocv2/sw/include/simple-spi.h<br />- /openrisc/trunk/orpsocv2/sw/include/spr-defs.h<br />- /openrisc/trunk/orpsocv2/sw/include/uart.h<br />+ /openrisc/trunk/orpsocv2/sw/lib<br />+ /openrisc/trunk/orpsocv2/sw/lib/include<br />+ /openrisc/trunk/orpsocv2/sw/lib/include/cpu-utils.h<br />+ /openrisc/trunk/orpsocv2/sw/lib/include/lib-utils.h<br />+ /openrisc/trunk/orpsocv2/sw/lib/include/printf.h<br />+ /openrisc/trunk/orpsocv2/sw/lib/lib-utils.c<br />+ /openrisc/trunk/orpsocv2/sw/lib/Makefile<br />+ /openrisc/trunk/orpsocv2/sw/lib/printf.c<br />~ /openrisc/trunk/orpsocv2/sw/Makefile.inc<br />- /openrisc/trunk/orpsocv2/sw/or1200/Makefile<br />- /openrisc/trunk/orpsocv2/sw/or1200/or1200-cbasic.c<br />- /openrisc/trunk/orpsocv2/sw/or1200/or1200-dctest.c<br />- /openrisc/trunk/orpsocv2/sw/or1200/or1200-div.c<br />- /openrisc/trunk/orpsocv2/sw/or1200/or1200-float.c<br />- /openrisc/trunk/orpsocv2/sw/or1200/or1200-mmu.c<br />- /openrisc/trunk/orpsocv2/sw/or1200/or1200-simple.c<br />- /openrisc/trunk/orpsocv2/sw/or1200asm/or1200asm-basic.S<br />- /openrisc/trunk/orpsocv2/sw/or1200asm/or1200asm-except.S<br />- /openrisc/trunk/orpsocv2/sw/or1200asm/or1200asm-fp.S<br />- /openrisc/trunk/orpsocv2/sw/or1200asm/or1200asm-linkregtest.S<br />- /openrisc/trunk/orpsocv2/sw/or1200asm/or1200asm-mac.S<br />- /openrisc/trunk/orpsocv2/sw/or1200asm/or1200asm-tick.S<br />- /openrisc/trunk/orpsocv2/sw/or1200asm/or1200asm-ticksyscall.S<br />- /openrisc/trunk/orpsocv2/sw/sdram/Makefile<br />- /openrisc/trunk/orpsocv2/sw/sdram/sdram-bankrows.c<br />- /openrisc/trunk/orpsocv2/sw/sdram/sdram-banks.c<br />- /openrisc/trunk/orpsocv2/sw/sdram/sdram-board-rows.c<br />- /openrisc/trunk/orpsocv2/sw/sdram/sdram-cols.c<br />- /openrisc/trunk/orpsocv2/sw/sdram/sdram-rows.c<br />- /openrisc/trunk/orpsocv2/sw/spi/Makefile<br />- /openrisc/trunk/orpsocv2/sw/spi/spi-interrupt.c<br />- /openrisc/trunk/orpsocv2/sw/spi/spi-simple.c<br />- /openrisc/trunk/orpsocv2/sw/spiflash<br />- /openrisc/trunk/orpsocv2/sw/support/crt0.S<br />- /openrisc/trunk/orpsocv2/sw/support/exceptions.c<br />- /openrisc/trunk/orpsocv2/sw/support/int.c<br />- /openrisc/trunk/orpsocv2/sw/support/or32-utils.c<br />- /openrisc/trunk/orpsocv2/sw/support/or32.ld<br />- /openrisc/trunk/orpsocv2/sw/support/or1200-mmu.S<br />- /openrisc/trunk/orpsocv2/sw/support/printf.c<br />- /openrisc/trunk/orpsocv2/sw/support/simple-spi.c<br />- /openrisc/trunk/orpsocv2/sw/support/uart.c<br />- /openrisc/trunk/orpsocv2/sw/testfloat<br />+ /openrisc/trunk/orpsocv2/sw/tests<br />+ /openrisc/trunk/orpsocv2/sw/tests/or1200<br />+ /openrisc/trunk/orpsocv2/sw/tests/or1200/board<br />+ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim<br />+ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/Makefile<br />+ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-basic.S<br />+ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-cbasic.c<br />+ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-dctest.c<br />+ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-div.c<br />+ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-except.S<br />+ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-float.c<br />+ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-fp.S<br />+ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-linkregtest.S<br />+ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-mac.S<br />+ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-mmu.c<br />+ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-simple.c<br />+ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-tick.S<br />+ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-ticksyscall.S<br />+ /openrisc/trunk/orpsocv2/sw/tests/sdram<br />+ /openrisc/trunk/orpsocv2/sw/tests/sdram/sim<br />+ /openrisc/trunk/orpsocv2/sw/tests/sdram/sim/Makefile<br />+ /openrisc/trunk/orpsocv2/sw/tests/sdram/sim/sdram-bankrows.c<br />+ /openrisc/trunk/orpsocv2/sw/tests/sdram/sim/sdram-banks.c<br />+ /openrisc/trunk/orpsocv2/sw/tests/sdram/sim/sdram-board-rows.c<br />+ /openrisc/trunk/orpsocv2/sw/tests/sdram/sim/sdram-cols.c<br />+ /openrisc/trunk/orpsocv2/sw/tests/sdram/sim/sdram-rows.c<br />+ /openrisc/trunk/orpsocv2/sw/tests/sdram/sim/sdram.h<br />+ /openrisc/trunk/orpsocv2/sw/tests/spi<br />+ /openrisc/trunk/orpsocv2/sw/tests/spi/sim<br />+ /openrisc/trunk/orpsocv2/sw/tests/spi/sim/Makefile<br />+ /openrisc/trunk/orpsocv2/sw/tests/spi/sim/spi-interrupt.c<br />+ /openrisc/trunk/orpsocv2/sw/tests/spi/sim/spi-simple.c<br />+ /openrisc/trunk/orpsocv2/sw/tests/uart<br />+ /openrisc/trunk/orpsocv2/sw/tests/uart/sim<br />+ /openrisc/trunk/orpsocv2/sw/tests/uart/sim/Makefile<br />+ /openrisc/trunk/orpsocv2/sw/tests/uart/sim/uart-echo.c<br />+ /openrisc/trunk/orpsocv2/sw/tests/uart/sim/uart-interrupt.c<br />+ /openrisc/trunk/orpsocv2/sw/tests/uart/sim/uart-simple.c<br />- /openrisc/trunk/orpsocv2/sw/uart/Makefile<br />- /openrisc/trunk/orpsocv2/sw/uart/uart-echo.c<br />- /openrisc/trunk/orpsocv2/sw/uart/uart-interrupt.c<br />- /openrisc/trunk/orpsocv2/sw/uart/uart-simple.c<br />
julius
Wed, 27 Oct 2010 14:30:36 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fsw%2Flib%2Finclude%2F&rev=393
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