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https://opencores.org/ocsvn/rtf65002/rtf65002/trunk
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rtf65002
WebSVN RSS feed - rtf65002
https://opencores.org/websvn//websvn/listing?repname=rtf65002&path=%2Frtf65002%2Ftrunk%2Frtl%2Fverilog%2F&
Thu, 18 Jun 2026 03:34:45 +0100
FeedCreator 1.7.2
-
- update for 65c816 support
https://opencores.org/websvn//websvn/revision?repname=rtf65002&path=%2Frtf65002%2Ftrunk%2Frtl%2Fverilog%2F&rev=41
<div><strong>Rev 41 - robfinch</strong> (2 file(s) modified)</div><div>- update for 65c816 support</div>+ /rtf65002/trunk/rtl/verilog/half_calc.v<br />+ /rtf65002/trunk/rtl/verilog/misc_task.v<br />
robfinch
Sun, 04 May 2014 02:24:58 +0100
https://opencores.org/websvn//websvn/revision?repname=rtf65002&path=%2Frtf65002%2Ftrunk%2Frtl%2Fverilog%2F&rev=41
-
- updated to support the 65c816 opcodes
https://opencores.org/websvn//websvn/revision?repname=rtf65002&path=%2Frtf65002%2Ftrunk%2Frtl%2Fverilog%2F&rev=38
<div><strong>Rev 38 - robfinch</strong> (16 file(s) modified)</div><div>- updated to support the 65c816 opcodes</div>~ /rtf65002/trunk/rtl/verilog/byte_calc.v<br />~ /rtf65002/trunk/rtl/verilog/byte_decode.v<br />~ /rtf65002/trunk/rtl/verilog/byte_ifetch.v<br />~ /rtf65002/trunk/rtl/verilog/cache_controller.v<br />~ /rtf65002/trunk/rtl/verilog/calc.v<br />~ /rtf65002/trunk/rtl/verilog/decode.v<br />~ /rtf65002/trunk/rtl/verilog/ifetch.v<br />~ /rtf65002/trunk/rtl/verilog/load_mac.v<br />~ /rtf65002/trunk/rtl/verilog/load_tsk.v<br />~ /rtf65002/trunk/rtl/verilog/rtf65002d.v<br />~ /rtf65002/trunk/rtl/verilog/rtf65002_alu.v<br />~ /rtf65002/trunk/rtl/verilog/rtf65002_defines.v<br />~ /rtf65002/trunk/rtl/verilog/rtf65002_pcinc.v<br />~ /rtf65002/trunk/rtl/verilog/rtf65002_pcinc8.v<br />~ /rtf65002/trunk/rtl/verilog/rtf65002_string.v<br />~ /rtf65002/trunk/rtl/verilog/store.v<br />
robfinch
Sun, 04 May 2014 02:20:22 +0100
https://opencores.org/websvn//websvn/revision?repname=rtf65002&path=%2Frtf65002%2Ftrunk%2Frtl%2Fverilog%2F&rev=38
-
- missing TRB/TSB instructions in 32 bit mode added
https://opencores.org/websvn//websvn/revision?repname=rtf65002&path=%2Frtf65002%2Ftrunk%2Frtl%2Fverilog%2F&rev=36
<div><strong>Rev 36 - robfinch</strong> (11 file(s) modified)</div><div>- missing TRB/TSB instructions in 32 bit mode added</div>~ /rtf65002/trunk/rtl/verilog/calc.v<br />~ /rtf65002/trunk/rtl/verilog/decode.v<br />~ /rtf65002/trunk/rtl/verilog/ifetch.v<br />~ /rtf65002/trunk/rtl/verilog/load_mac.v<br />~ /rtf65002/trunk/rtl/verilog/load_tsk.v<br />~ /rtf65002/trunk/rtl/verilog/rtf65002d.v<br />~ /rtf65002/trunk/rtl/verilog/rtf65002_alu.v<br />~ /rtf65002/trunk/rtl/verilog/rtf65002_defines.v<br />~ /rtf65002/trunk/rtl/verilog/rtf65002_pcinc.v<br />~ /rtf65002/trunk/rtl/verilog/rtf65002_tb.v<br />~ /rtf65002/trunk/rtl/verilog/store.v<br />
robfinch
Fri, 06 Dec 2013 07:18:10 +0100
https://opencores.org/websvn//websvn/revision?repname=rtf65002&path=%2Frtf65002%2Ftrunk%2Frtl%2Fverilog%2F&rev=36
-
- several bug fixes
- mul,mod,div immediates mode than 8 bits
- ...
https://opencores.org/websvn//websvn/revision?repname=rtf65002&path=%2Frtf65002%2Ftrunk%2Frtl%2Fverilog%2F&rev=35
<div><strong>Rev 35 - robfinch</strong> (20 file(s) modified)</div><div>- several bug fixes<br />
- mul,mod,div immediates mode than 8 bits<br />
- ...</div>~ /rtf65002/trunk/rtl/verilog/byte_calc.v<br />~ /rtf65002/trunk/rtl/verilog/byte_ifetch.v<br />~ /rtf65002/trunk/rtl/verilog/cache_controller.v<br />~ /rtf65002/trunk/rtl/verilog/decode.v<br />~ /rtf65002/trunk/rtl/verilog/ifetch.v<br />~ /rtf65002/trunk/rtl/verilog/load_mac.v<br />~ /rtf65002/trunk/rtl/verilog/load_tsk.v<br />~ /rtf65002/trunk/rtl/verilog/mult_div.v<br />~ /rtf65002/trunk/rtl/verilog/rtf65002d.v<br />~ /rtf65002/trunk/rtl/verilog/rtf65002_alu.v<br />~ /rtf65002/trunk/rtl/verilog/rtf65002_defines.v<br />~ /rtf65002/trunk/rtl/verilog/rtf65002_dtagmem.v<br />~ /rtf65002/trunk/rtl/verilog/rtf65002_itagmem.v<br />~ /rtf65002/trunk/rtl/verilog/rtf65002_itagmem2way.v<br />~ /rtf65002/trunk/rtl/verilog/rtf65002_itagmem4k.v<br />~ /rtf65002/trunk/rtl/verilog/rtf65002_itagmem8k.v<br />~ /rtf65002/trunk/rtl/verilog/rtf65002_pcinc.v<br />~ /rtf65002/trunk/rtl/verilog/rtf65002_pcinc8.v<br />~ /rtf65002/trunk/rtl/verilog/store.v<br />+ /rtf65002/trunk/rtl/verilog/wb_task.v<br />
robfinch
Sun, 20 Oct 2013 14:25:43 +0100
https://opencores.org/websvn//websvn/revision?repname=rtf65002&path=%2Frtf65002%2Ftrunk%2Frtl%2Fverilog%2F&rev=35
-
- many changes
- new instructions
- code reorganization
https://opencores.org/websvn//websvn/revision?repname=rtf65002&path=%2Frtf65002%2Ftrunk%2Frtl%2Fverilog%2F&rev=32
<div><strong>Rev 32 - robfinch</strong> (25 file(s) modified)</div><div>- many changes<br />
- new instructions<br />
- code reorganization</div>~ /rtf65002/trunk/rtl/verilog/byte_calc.v<br />~ /rtf65002/trunk/rtl/verilog/byte_decode.v<br />+ /rtf65002/trunk/rtl/verilog/byte_ifetch.v<br />~ /rtf65002/trunk/rtl/verilog/cache_controller.v<br />~ /rtf65002/trunk/rtl/verilog/calc.v<br />~ /rtf65002/trunk/rtl/verilog/decode.v<br />~ /rtf65002/trunk/rtl/verilog/ifetch.v<br />~ /rtf65002/trunk/rtl/verilog/load_mac.v<br />+ /rtf65002/trunk/rtl/verilog/load_tsk.v<br />~ /rtf65002/trunk/rtl/verilog/mult_div.v<br />~ /rtf65002/trunk/rtl/verilog/rtf65002d.v<br />+ /rtf65002/trunk/rtl/verilog/rtf65002_alu.v<br />~ /rtf65002/trunk/rtl/verilog/rtf65002_defines.v<br />~ /rtf65002/trunk/rtl/verilog/rtf65002_dtagmem.v<br />+ /rtf65002/trunk/rtl/verilog/rtf65002_icachemem2way.v<br />+ /rtf65002/trunk/rtl/verilog/rtf65002_icachemem4k.v<br />+ /rtf65002/trunk/rtl/verilog/rtf65002_icachemem8k.v<br />+ /rtf65002/trunk/rtl/verilog/rtf65002_icachemem16k.v<br />+ /rtf65002/trunk/rtl/verilog/rtf65002_itagmem2way.v<br />+ /rtf65002/trunk/rtl/verilog/rtf65002_itagmem4k.v<br />+ /rtf65002/trunk/rtl/verilog/rtf65002_itagmem8k.v<br />~ /rtf65002/trunk/rtl/verilog/rtf65002_pcinc.v<br />+ /rtf65002/trunk/rtl/verilog/rtf65002_pcinc8.v<br />+ /rtf65002/trunk/rtl/verilog/rtf65002_string.v<br />~ /rtf65002/trunk/rtl/verilog/store.v<br />
robfinch
Thu, 10 Oct 2013 00:32:29 +0100
https://opencores.org/websvn//websvn/revision?repname=rtf65002&path=%2Frtf65002%2Ftrunk%2Frtl%2Fverilog%2F&rev=32
-
- added additional branches
- modified the pc increment
- modified interrupts, ...
https://opencores.org/websvn//websvn/revision?repname=rtf65002&path=%2Frtf65002%2Ftrunk%2Frtl%2Fverilog%2F&rev=30
<div><strong>Rev 30 - robfinch</strong> (17 file(s) modified)</div><div>- added additional branches<br />
- modified the pc increment<br />
- modified interrupts, ...</div>~ /rtf65002/trunk/rtl/verilog/byte_irq.v<br />~ /rtf65002/trunk/rtl/verilog/cache_controller.v<br />~ /rtf65002/trunk/rtl/verilog/calc.v<br />~ /rtf65002/trunk/rtl/verilog/decode.v<br />~ /rtf65002/trunk/rtl/verilog/ifetch.v<br />~ /rtf65002/trunk/rtl/verilog/load_mac.v<br />~ /rtf65002/trunk/rtl/verilog/mult_div.v<br />+ /rtf65002/trunk/rtl/verilog/overflow.v<br />~ /rtf65002/trunk/rtl/verilog/rtf65002d.v<br />~ /rtf65002/trunk/rtl/verilog/RTF65002PIC.v<br />+ /rtf65002/trunk/rtl/verilog/rtf65002_dcachemem.v<br />+ /rtf65002/trunk/rtl/verilog/rtf65002_defines.v<br />+ /rtf65002/trunk/rtl/verilog/rtf65002_dtagmem.v<br />+ /rtf65002/trunk/rtl/verilog/rtf65002_icachemem.v<br />+ /rtf65002/trunk/rtl/verilog/rtf65002_itagmem.v<br />+ /rtf65002/trunk/rtl/verilog/rtf65002_pcinc.v<br />~ /rtf65002/trunk/rtl/verilog/store.v<br />
robfinch
Mon, 30 Sep 2013 02:36:45 +0100
https://opencores.org/websvn//websvn/revision?repname=rtf65002&path=%2Frtf65002%2Ftrunk%2Frtl%2Fverilog%2F&rev=30
-
- add EXEC and ATNI instructions
- fix store byte zero ...
https://opencores.org/websvn//websvn/revision?repname=rtf65002&path=%2Frtf65002%2Ftrunk%2Frtl%2Fverilog%2F&rev=25
<div><strong>Rev 25 - robfinch</strong> (6 file(s) modified)</div><div>- add EXEC and ATNI instructions<br />
- fix store byte zero ...</div>~ /rtf65002/trunk/rtl/verilog/byte_decode.v<br />~ /rtf65002/trunk/rtl/verilog/decode.v<br />~ /rtf65002/trunk/rtl/verilog/ifetch.v<br />~ /rtf65002/trunk/rtl/verilog/php.v<br />~ /rtf65002/trunk/rtl/verilog/rtf65002d.v<br />~ /rtf65002/trunk/rtl/verilog/store.v<br />
robfinch
Mon, 23 Sep 2013 00:44:13 +0100
https://opencores.org/websvn//websvn/revision?repname=rtf65002&path=%2Frtf65002%2Ftrunk%2Frtl%2Fverilog%2F&rev=25
-
- added subtract immediate from sp
- added stack relative addressing ...
https://opencores.org/websvn//websvn/revision?repname=rtf65002&path=%2Frtf65002%2Ftrunk%2Frtl%2Fverilog%2F&rev=23
<div><strong>Rev 23 - robfinch</strong> (8 file(s) modified)</div><div>- added subtract immediate from sp<br />
- added stack relative addressing ...</div>~ /rtf65002/trunk/rtl/verilog/byte_jsl.v<br />~ /rtf65002/trunk/rtl/verilog/byte_jsr.v<br />~ /rtf65002/trunk/rtl/verilog/decode.v<br />~ /rtf65002/trunk/rtl/verilog/ifetch.v<br />~ /rtf65002/trunk/rtl/verilog/load_mac.v<br />~ /rtf65002/trunk/rtl/verilog/php.v<br />~ /rtf65002/trunk/rtl/verilog/rtf65002d.v<br />~ /rtf65002/trunk/rtl/verilog/store.v<br />
robfinch
Tue, 17 Sep 2013 02:59:46 +0100
https://opencores.org/websvn//websvn/revision?repname=rtf65002&path=%2Frtf65002%2Ftrunk%2Frtl%2Fverilog%2F&rev=23
-
- fix indirect load
https://opencores.org/websvn//websvn/revision?repname=rtf65002&path=%2Frtf65002%2Ftrunk%2Frtl%2Fverilog%2F&rev=22
<div><strong>Rev 22 - robfinch</strong> (1 file(s) modified)</div><div>- fix indirect load</div>~ /rtf65002/trunk/rtl/verilog/load_mac.v<br />
robfinch
Sun, 15 Sep 2013 13:05:52 +0100
https://opencores.org/websvn//websvn/revision?repname=rtf65002&path=%2Frtf65002%2Ftrunk%2Frtl%2Fverilog%2F&rev=22
-
- config processor mode on reset
- D flag flags extended ...
https://opencores.org/websvn//websvn/revision?repname=rtf65002&path=%2Frtf65002%2Ftrunk%2Frtl%2Fverilog%2F&rev=21
<div><strong>Rev 21 - robfinch</strong> (22 file(s) modified)</div><div>- config processor mode on reset<br />
- D flag flags extended ...</div>~ /rtf65002/trunk/rtl/verilog/byte_decode.v<br />~ /rtf65002/trunk/rtl/verilog/byte_irq.v<br />~ /rtf65002/trunk/rtl/verilog/byte_ix.v<br />~ /rtf65002/trunk/rtl/verilog/byte_iy.v<br />~ /rtf65002/trunk/rtl/verilog/byte_jmp_ind.v<br />~ /rtf65002/trunk/rtl/verilog/byte_jsl.v<br />~ /rtf65002/trunk/rtl/verilog/byte_jsr.v<br />~ /rtf65002/trunk/rtl/verilog/byte_plp.v<br />~ /rtf65002/trunk/rtl/verilog/byte_rti.v<br />~ /rtf65002/trunk/rtl/verilog/byte_rts.v<br />~ /rtf65002/trunk/rtl/verilog/cache_controller.v<br />~ /rtf65002/trunk/rtl/verilog/calc.v<br />~ /rtf65002/trunk/rtl/verilog/decode.v<br />~ /rtf65002/trunk/rtl/verilog/load.v<br />+ /rtf65002/trunk/rtl/verilog/load_mac.v<br />~ /rtf65002/trunk/rtl/verilog/php.v<br />~ /rtf65002/trunk/rtl/verilog/pla.v<br />~ /rtf65002/trunk/rtl/verilog/plp.v<br />~ /rtf65002/trunk/rtl/verilog/rtf65002d.v<br />~ /rtf65002/trunk/rtl/verilog/rti.v<br />~ /rtf65002/trunk/rtl/verilog/rts.v<br />~ /rtf65002/trunk/rtl/verilog/store.v<br />
robfinch
Sun, 15 Sep 2013 07:42:11 +0100
https://opencores.org/websvn//websvn/revision?repname=rtf65002&path=%2Frtf65002%2Ftrunk%2Frtl%2Fverilog%2F&rev=21
-
- greater separation of emulation and native mode in source ...
https://opencores.org/websvn//websvn/revision?repname=rtf65002&path=%2Frtf65002%2Ftrunk%2Frtl%2Fverilog%2F&rev=20
<div><strong>Rev 20 - robfinch</strong> (13 file(s) modified)</div><div>- greater separation of emulation and native mode in source ...</div>+ /rtf65002/trunk/rtl/verilog/byte_calc.v<br />+ /rtf65002/trunk/rtl/verilog/byte_decode.v<br />~ /rtf65002/trunk/rtl/verilog/byte_iy.v<br />~ /rtf65002/trunk/rtl/verilog/byte_jsr.v<br />~ /rtf65002/trunk/rtl/verilog/cache_controller.v<br />~ /rtf65002/trunk/rtl/verilog/calc.v<br />+ /rtf65002/trunk/rtl/verilog/decode.v<br />+ /rtf65002/trunk/rtl/verilog/ifetch.v<br />+ /rtf65002/trunk/rtl/verilog/load.v<br />+ /rtf65002/trunk/rtl/verilog/php.v<br />~ /rtf65002/trunk/rtl/verilog/rtf65002d.v<br />~ /rtf65002/trunk/rtl/verilog/rtf65002_tb.v<br />+ /rtf65002/trunk/rtl/verilog/store.v<br />
robfinch
Sat, 14 Sep 2013 01:36:54 +0100
https://opencores.org/websvn//websvn/revision?repname=rtf65002&path=%2Frtf65002%2Ftrunk%2Frtl%2Fverilog%2F&rev=20
-
- added multibit shifts
- added eight bit CMP instruction
https://opencores.org/websvn//websvn/revision?repname=rtf65002&path=%2Frtf65002%2Ftrunk%2Frtl%2Fverilog%2F&rev=19
<div><strong>Rev 19 - robfinch</strong> (2 file(s) modified)</div><div>- added multibit shifts<br />
- added eight bit CMP instruction</div>~ /rtf65002/trunk/rtl/verilog/calc.v<br />~ /rtf65002/trunk/rtl/verilog/rtf65002d.v<br />
robfinch
Fri, 13 Sep 2013 03:19:10 +0100
https://opencores.org/websvn//websvn/revision?repname=rtf65002&path=%2Frtf65002%2Ftrunk%2Frtl%2Fverilog%2F&rev=19
-
- fix overflow in immediate mode
- fix bit instruction N,V ...
https://opencores.org/websvn//websvn/revision?repname=rtf65002&path=%2Frtf65002%2Ftrunk%2Frtl%2Fverilog%2F&rev=13
<div><strong>Rev 13 - robfinch</strong> (10 file(s) modified)</div><div>- fix overflow in immediate mode<br />
- fix bit instruction N,V ...</div>~ /rtf65002/trunk/rtl/verilog/byte_irq.v<br />~ /rtf65002/trunk/rtl/verilog/byte_jsl.v<br />~ /rtf65002/trunk/rtl/verilog/byte_jsr.v<br />~ /rtf65002/trunk/rtl/verilog/byte_plp.v<br />~ /rtf65002/trunk/rtl/verilog/byte_rti.v<br />~ /rtf65002/trunk/rtl/verilog/byte_rts.v<br />~ /rtf65002/trunk/rtl/verilog/calc.v<br />~ /rtf65002/trunk/rtl/verilog/plp.v<br />~ /rtf65002/trunk/rtl/verilog/rtf65002d.v<br />~ /rtf65002/trunk/rtl/verilog/RTF65002PIC.v<br />
robfinch
Thu, 12 Sep 2013 03:06:08 +0100
https://opencores.org/websvn//websvn/revision?repname=rtf65002&path=%2Frtf65002%2Ftrunk%2Frtl%2Fverilog%2F&rev=13
-
- added LFSR and TICK count special registers
- added MUL/DIV/MOD ...
https://opencores.org/websvn//websvn/revision?repname=rtf65002&path=%2Frtf65002%2Ftrunk%2Frtl%2Fverilog%2F&rev=12
<div><strong>Rev 12 - robfinch</strong> (2 file(s) modified)</div><div>- added LFSR and TICK count special registers<br />
- added MUL/DIV/MOD ...</div>+ /rtf65002/trunk/rtl/verilog/mult_div.v<br />~ /rtf65002/trunk/rtl/verilog/rtf65002d.v<br />
robfinch
Wed, 11 Sep 2013 02:42:36 +0100
https://opencores.org/websvn//websvn/revision?repname=rtf65002&path=%2Frtf65002%2Ftrunk%2Frtl%2Fverilog%2F&rev=12
-
- fix rind mode in 32 bit mode
- fix flag ...
https://opencores.org/websvn//websvn/revision?repname=rtf65002&path=%2Frtf65002%2Ftrunk%2Frtl%2Fverilog%2F&rev=10
<div><strong>Rev 10 - robfinch</strong> (17 file(s) modified)</div><div>- fix rind mode in 32 bit mode<br />
- fix flag ...</div>~ /rtf65002/trunk/rtl/verilog/byte_irq.v<br />~ /rtf65002/trunk/rtl/verilog/byte_ix.v<br />~ /rtf65002/trunk/rtl/verilog/byte_iy.v<br />~ /rtf65002/trunk/rtl/verilog/byte_jmp_ind.v<br />~ /rtf65002/trunk/rtl/verilog/byte_jsl.v<br />~ /rtf65002/trunk/rtl/verilog/byte_jsr.v<br />~ /rtf65002/trunk/rtl/verilog/byte_plp.v<br />~ /rtf65002/trunk/rtl/verilog/byte_rti.v<br />~ /rtf65002/trunk/rtl/verilog/byte_rts.v<br />~ /rtf65002/trunk/rtl/verilog/cache_controller.v<br />~ /rtf65002/trunk/rtl/verilog/calc.v<br />~ /rtf65002/trunk/rtl/verilog/pla.v<br />~ /rtf65002/trunk/rtl/verilog/plp.v<br />~ /rtf65002/trunk/rtl/verilog/rtf65002d.v<br />+ /rtf65002/trunk/rtl/verilog/RTF65002PIC.v<br />~ /rtf65002/trunk/rtl/verilog/rti.v<br />~ /rtf65002/trunk/rtl/verilog/rts.v<br />
robfinch
Sun, 08 Sep 2013 21:52:21 +0100
https://opencores.org/websvn//websvn/revision?repname=rtf65002&path=%2Frtf65002%2Ftrunk%2Frtl%2Fverilog%2F&rev=10
-
setting up project
https://opencores.org/websvn//websvn/revision?repname=rtf65002&path=%2Frtf65002%2Ftrunk%2Frtl%2Fverilog%2F&rev=5
<div><strong>Rev 5 - robfinch</strong> (18 file(s) modified)</div><div>setting up project</div>+ /rtf65002/trunk/rtl/verilog<br />+ /rtf65002/trunk/rtl/verilog/byte_irq.v<br />+ /rtf65002/trunk/rtl/verilog/byte_ix.v<br />+ /rtf65002/trunk/rtl/verilog/byte_iy.v<br />+ /rtf65002/trunk/rtl/verilog/byte_jmp_ind.v<br />+ /rtf65002/trunk/rtl/verilog/byte_jsl.v<br />+ /rtf65002/trunk/rtl/verilog/byte_jsr.v<br />+ /rtf65002/trunk/rtl/verilog/byte_plp.v<br />+ /rtf65002/trunk/rtl/verilog/byte_rti.v<br />+ /rtf65002/trunk/rtl/verilog/byte_rts.v<br />+ /rtf65002/trunk/rtl/verilog/cache_controller.v<br />+ /rtf65002/trunk/rtl/verilog/calc.v<br />+ /rtf65002/trunk/rtl/verilog/pla.v<br />+ /rtf65002/trunk/rtl/verilog/plp.v<br />+ /rtf65002/trunk/rtl/verilog/rtf65002d.v<br />+ /rtf65002/trunk/rtl/verilog/rtf65002_tb.v<br />+ /rtf65002/trunk/rtl/verilog/rti.v<br />+ /rtf65002/trunk/rtl/verilog/rts.v<br />
robfinch
Thu, 05 Sep 2013 14:29:08 +0100
https://opencores.org/websvn//websvn/revision?repname=rtf65002&path=%2Frtf65002%2Ftrunk%2Frtl%2Fverilog%2F&rev=5
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