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            <description>&lt;div&gt;&lt;strong&gt;Rev 47 - fransschreuder&lt;/strong&gt; (6 file(s) modified)&lt;/div&gt;&lt;div&gt;Deleted all files, the repository was moved to Nikhef Gitlab, ...&lt;/div&gt;- /virtex7_pcie_dma/trunk/documentation&lt;br /&gt;- /virtex7_pcie_dma/trunk/firmware&lt;br /&gt;- /virtex7_pcie_dma/trunk/LICENSE.txt&lt;br /&gt;~ /virtex7_pcie_dma/trunk/README.md&lt;br /&gt;- /virtex7_pcie_dma/trunk/software&lt;br /&gt;- /virtex7_pcie_dma/trunk/WupperCodeGenScripts&lt;br /&gt;</description>
            <author>fransschreuder</author>
            <pubDate>Fri, 10 Sep 2021 12:18:52 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=virtex7_pcie_dma&amp;path=%2Fvirtex7_pcie_dma%2F&amp;rev=47</guid>
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            <title>New Vivado version, changed regmap clock, added byte enable to ...</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=virtex7_pcie_dma&amp;path=%2Fvirtex7_pcie_dma%2F&amp;rev=46</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 46 - fransschreuder&lt;/strong&gt; (66 file(s) modified)&lt;/div&gt;&lt;div&gt;New Vivado version, changed regmap clock, added byte enable to ...&lt;/div&gt;~ /virtex7_pcie_dma/trunk/documentation/bibliography.tex&lt;br /&gt;~ /virtex7_pcie_dma/trunk/documentation/design.tex&lt;br /&gt;~ /virtex7_pcie_dma/trunk/documentation/et_template/template.tex&lt;br /&gt;~ /virtex7_pcie_dma/trunk/documentation/figures/dma_core_structure.png&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/figures/Endless_DMA_impression.pdf&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/figures/felix_PCIeEngine_to_hostBuffer_interface.odg&lt;br /&gt;~ /virtex7_pcie_dma/trunk/documentation/figures/pcie_core_basic.png&lt;br /&gt;~ /virtex7_pcie_dma/trunk/documentation/figures/pcie_core_config1.pdf&lt;br /&gt;~ /virtex7_pcie_dma/trunk/documentation/figures/pcie_core_config2.pdf&lt;br /&gt;~ /virtex7_pcie_dma/trunk/documentation/figures/pcie_core_config3.pdf&lt;br /&gt;~ /virtex7_pcie_dma/trunk/documentation/figures/pcie_core_pf0_bar.png&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/figures/wb_compatible.pdf&lt;br /&gt;~ /virtex7_pcie_dma/trunk/documentation/figures/wupper_structure.odg&lt;br /&gt;~ /virtex7_pcie_dma/trunk/documentation/introduction.tex&lt;br /&gt;~ /virtex7_pcie_dma/trunk/documentation/registermap.tex&lt;br /&gt;~ /virtex7_pcie_dma/trunk/documentation/registers-1.0.html&lt;br /&gt;~ /virtex7_pcie_dma/trunk/documentation/supportedtools.tex&lt;br /&gt;~ /virtex7_pcie_dma/trunk/documentation/versionhistory.tex&lt;br /&gt;~ /virtex7_pcie_dma/trunk/documentation/wupper.pdf&lt;br /&gt;~ /virtex7_pcie_dma/trunk/documentation/wupper.tex&lt;br /&gt;~ /virtex7_pcie_dma/trunk/documentation/xilinx_core.tex&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/scripts/Wupper/vivado_import_kintexultrascale.tcl&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/scripts/Wupper/vivado_import_virtex7.tcl&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/sources/application/xadc_drp.vhd&lt;br /&gt;- /virtex7_pcie_dma/trunk/firmware/sources/ip_cores/ku/clk_wiz_40.xci&lt;br /&gt;+ /virtex7_pcie_dma/trunk/firmware/sources/ip_cores/ku/clk_wiz_regmap.xci&lt;br /&gt;- /virtex7_pcie_dma/trunk/firmware/sources/ip_cores/ku/fifo4KB_256bit.xci&lt;br /&gt;+ /virtex7_pcie_dma/trunk/firmware/sources/ip_cores/ku/fifo16KB_256bit.xci&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/sources/ip_cores/ku/fifo128KB_256bit.xci&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/sources/ip_cores/ku/I2C_RDFifo.xci&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/sources/ip_cores/ku/I2C_WRFifo.xci&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/sources/ip_cores/ku/pcie3_ultrascale_7038.xci&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/sources/ip_cores/ku/pcie3_ultrascale_7039.xci&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/sources/ip_cores/ku/system_management_wiz_0.xci&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/sources/ip_cores/ku/wishbone_memory.xci&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/sources/ip_cores/ku/wishbone_to_wupper_fifo.xci&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/sources/ip_cores/ku/wupper_to_wishbone_fifo.xci&lt;br /&gt;+ /virtex7_pcie_dma/trunk/firmware/sources/ip_cores/virtex7/clk_wiz_regmap.xci&lt;br /&gt;- /virtex7_pcie_dma/trunk/firmware/sources/ip_cores/virtex7/fifo4KB_256bit.xci&lt;br /&gt;+ /virtex7_pcie_dma/trunk/firmware/sources/ip_cores/virtex7/fifo16KB_256bit.xci&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/sources/ip_cores/virtex7/fifo128KB_256bit.xci&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/sources/ip_cores/virtex7/I2C_RDFifo.xci&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/sources/ip_cores/virtex7/I2C_WRFifo.xci&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/sources/ip_cores/virtex7/pcie_x8_gen3_3_0.xci&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/sources/ip_cores/virtex7/wishbone_memory.xci&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/sources/ip_cores/virtex7/wishbone_to_wupper_fifo.xci&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/sources/ip_cores/virtex7/wupper_to_wishbone_fifo.xci&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/sources/ip_cores/virtex7/xadc_wiz_0.xci&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/sources/packages/pcie_package.vhd&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/sources/pcie/dma_control.vhd&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/sources/pcie/dma_read_write.vhd&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/sources/pcie/intr_ctrl.vhd&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/sources/pcie/pcie_ep_wrap.vhd&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/sources/pcie/pcie_init.vhd&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/sources/pcie/pcie_slow_clock.vhd&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/sources/pcie/wupper.vhd&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/sources/pcie/wupper_core.vhd&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/sources/shared/housekeeping.vhd&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/sources/shared/wupper_oc_top.vhd&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/sources/templates/dma_control.vhd.template&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/sources/templates/pcie_package.vhd.template&lt;br /&gt;~ /virtex7_pcie_dma/trunk/software/regmap/regmap/regmap-struct.h&lt;br /&gt;~ /virtex7_pcie_dma/trunk/software/regmap/regmap/regmap-symbol.h&lt;br /&gt;~ /virtex7_pcie_dma/trunk/software/regmap/src/regmap-symbol.c&lt;br /&gt;~ /virtex7_pcie_dma/trunk/software/wuppercodegen/wuppercodegen/classes.py&lt;br /&gt;~ /virtex7_pcie_dma/trunk/WupperCodeGenScripts/registers-1.0.yaml&lt;br /&gt;</description>
            <author>fransschreuder</author>
            <pubDate>Fri, 17 May 2019 14:41:06 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=virtex7_pcie_dma&amp;path=%2Fvirtex7_pcie_dma%2F&amp;rev=46</guid>
        </item>
        <item>
            <title>Fixed duplicate driver and Vivado 2018.1 PCIe core</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=virtex7_pcie_dma&amp;path=%2Fvirtex7_pcie_dma%2F&amp;rev=45</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 45 - fransschreuder&lt;/strong&gt; (2 file(s) modified)&lt;/div&gt;&lt;div&gt;Fixed duplicate driver and Vivado 2018.1 PCIe core&lt;/div&gt;~ /virtex7_pcie_dma/trunk/firmware/sources/pcie/pcie_ep_wrap.vhd&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/sources/shared/housekeeping.vhd&lt;br /&gt;</description>
            <author>fransschreuder</author>
            <pubDate>Tue, 23 Apr 2019 06:43:57 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=virtex7_pcie_dma&amp;path=%2Fvirtex7_pcie_dma%2F&amp;rev=45</guid>
        </item>
        <item>
            <title>EDITED: added image size</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=virtex7_pcie_dma&amp;path=%2Fvirtex7_pcie_dma%2F&amp;rev=44</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 44 - aborga&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;EDITED: added image size&lt;/div&gt;~ /virtex7_pcie_dma/trunk/README.md&lt;br /&gt;</description>
            <author>aborga</author>
            <pubDate>Fri, 25 Jan 2019 14:57:47 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=virtex7_pcie_dma&amp;path=%2Fvirtex7_pcie_dma%2F&amp;rev=44</guid>
        </item>
        <item>
            <title>ADDED: README.md to be parsed by the OC project page</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=virtex7_pcie_dma&amp;path=%2Fvirtex7_pcie_dma%2F&amp;rev=43</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 43 - aborga&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;ADDED: README.md to be parsed by the OC project page&lt;/div&gt;+ /virtex7_pcie_dma/trunk/README.md&lt;br /&gt;</description>
            <author>aborga</author>
            <pubDate>Fri, 25 Jan 2019 09:42:50 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=virtex7_pcie_dma&amp;path=%2Fvirtex7_pcie_dma%2F&amp;rev=43</guid>
        </item>
        <item>
            <title>Added filter in wuppercodegen in order to generate 2d arrays ...</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=virtex7_pcie_dma&amp;path=%2Fvirtex7_pcie_dma%2F&amp;rev=42</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 42 - fransschreuder&lt;/strong&gt; (2 file(s) modified)&lt;/div&gt;&lt;div&gt;Added filter in wuppercodegen in order to generate 2d arrays ...&lt;/div&gt;~ /virtex7_pcie_dma/trunk/firmware/sources/templates/pcie_package.vhd.template&lt;br /&gt;~ /virtex7_pcie_dma/trunk/software/wuppercodegen/wuppercodegen/filter.py&lt;br /&gt;</description>
            <author>fransschreuder</author>
            <pubDate>Wed, 14 Feb 2018 09:57:39 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=virtex7_pcie_dma&amp;path=%2Fvirtex7_pcie_dma%2F&amp;rev=42</guid>
        </item>
        <item>
            <title>Added brief description of Wishbone</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=virtex7_pcie_dma&amp;path=%2Fvirtex7_pcie_dma%2F&amp;rev=41</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 41 - broel&lt;/strong&gt; (6 file(s) modified)&lt;/div&gt;&lt;div&gt;Added brief description of Wishbone&lt;/div&gt;~ /virtex7_pcie_dma/trunk/documentation/design.tex&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/figures/wupper_to_wishbone.tex&lt;br /&gt;~ /virtex7_pcie_dma/trunk/documentation/titlepage.tex&lt;br /&gt;~ /virtex7_pcie_dma/trunk/documentation/versionhistory.tex&lt;br /&gt;~ /virtex7_pcie_dma/trunk/documentation/wupper.pdf&lt;br /&gt;~ /virtex7_pcie_dma/trunk/documentation/wupper.tex&lt;br /&gt;</description>
            <author>broel</author>
            <pubDate>Mon, 06 Nov 2017 10:39:55 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=virtex7_pcie_dma&amp;path=%2Fvirtex7_pcie_dma%2F&amp;rev=41</guid>
        </item>
        <item>
            <title>Updated comment header for syscon.</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=virtex7_pcie_dma&amp;path=%2Fvirtex7_pcie_dma%2F&amp;rev=40</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 40 - broel&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;Updated comment header for syscon.&lt;/div&gt;~ /virtex7_pcie_dma/trunk/firmware/sources/Wishbone/wb_syscon.vhd&lt;br /&gt;</description>
            <author>broel</author>
            <pubDate>Mon, 06 Nov 2017 08:44:29 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=virtex7_pcie_dma&amp;path=%2Fvirtex7_pcie_dma%2F&amp;rev=40</guid>
        </item>
        <item>
            <title>Added Wishbone bus to Wupper plus a Wishbone memory as ...</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=virtex7_pcie_dma&amp;path=%2Fvirtex7_pcie_dma%2F&amp;rev=39</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 39 - broel&lt;/strong&gt; (42 file(s) modified)&lt;/div&gt;&lt;div&gt;Added Wishbone bus to Wupper plus a Wishbone memory as ...&lt;/div&gt;~ /virtex7_pcie_dma/trunk/documentation/registermap.tex&lt;br /&gt;~ /virtex7_pcie_dma/trunk/documentation/registers-1.0.html&lt;br /&gt;~ /virtex7_pcie_dma/trunk/documentation/wupper.pdf&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/scripts/Wupper/do_implementation_HTG710.tcl&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/scripts/Wupper/do_implementation_KCU105.tcl&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/scripts/Wupper/do_implementation_VC709.tcl&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/scripts/Wupper/vivado_import_kintexultrascale.tcl&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/scripts/Wupper/vivado_import_virtex7.tcl&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/sources/ip_cores/ku/clk_wiz_40.xci&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/sources/ip_cores/ku/fifo4KB_256bit.xci&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/sources/ip_cores/ku/fifo128KB_256bit.xci&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/sources/ip_cores/ku/I2C_RDFifo.xci&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/sources/ip_cores/ku/I2C_WRFifo.xci&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/sources/ip_cores/ku/pcie3_ultrascale_7038.xci&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/sources/ip_cores/ku/pcie3_ultrascale_7039.xci&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/sources/ip_cores/ku/system_management_wiz_0.xci&lt;br /&gt;+ /virtex7_pcie_dma/trunk/firmware/sources/ip_cores/ku/wishbone_memory.xci&lt;br /&gt;+ /virtex7_pcie_dma/trunk/firmware/sources/ip_cores/ku/wishbone_to_wupper_fifo.xci&lt;br /&gt;+ /virtex7_pcie_dma/trunk/firmware/sources/ip_cores/ku/wupper_to_wishbone_fifo.xci&lt;br /&gt;+ /virtex7_pcie_dma/trunk/firmware/sources/ip_cores/virtex7/wishbone_memory.xci&lt;br /&gt;+ /virtex7_pcie_dma/trunk/firmware/sources/ip_cores/virtex7/wishbone_to_wupper_fifo.xci&lt;br /&gt;+ /virtex7_pcie_dma/trunk/firmware/sources/ip_cores/virtex7/wupper_to_wishbone_fifo.xci&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/sources/packages/pcie_package.vhd&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/sources/pcie/dma_control.vhd&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/sources/pcie/wupper.vhd&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/sources/pcie/wupper_core.vhd&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/sources/shared/wupper_oc_top.vhd&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/sources/templates/dma_control.vhd.template&lt;br /&gt;+ /virtex7_pcie_dma/trunk/firmware/sources/Wishbone&lt;br /&gt;+ /virtex7_pcie_dma/trunk/firmware/sources/Wishbone/genram_pkg.vhd&lt;br /&gt;+ /virtex7_pcie_dma/trunk/firmware/sources/Wishbone/wb_intercon.vhd&lt;br /&gt;+ /virtex7_pcie_dma/trunk/firmware/sources/Wishbone/wb_memory.vhd&lt;br /&gt;+ /virtex7_pcie_dma/trunk/firmware/sources/Wishbone/wb_syscon.vhd&lt;br /&gt;+ /virtex7_pcie_dma/trunk/firmware/sources/Wishbone/wishbone_pkg.vhd&lt;br /&gt;+ /virtex7_pcie_dma/trunk/firmware/sources/Wishbone/wupper_to_wb.vhd&lt;br /&gt;+ /virtex7_pcie_dma/trunk/firmware/sources/Wishbone/xwb_crossbar.vhd&lt;br /&gt;~ /virtex7_pcie_dma/trunk/software/regmap/regmap/regmap-struct.h&lt;br /&gt;~ /virtex7_pcie_dma/trunk/software/regmap/regmap/regmap-symbol.h&lt;br /&gt;~ /virtex7_pcie_dma/trunk/software/regmap/src/regmap-symbol.c&lt;br /&gt;~ /virtex7_pcie_dma/trunk/software/wupper_tools/CMakeLists.txt&lt;br /&gt;+ /virtex7_pcie_dma/trunk/software/wupper_tools/src/wupper-wishbone.cpp&lt;br /&gt;~ /virtex7_pcie_dma/trunk/WupperCodeGenScripts/registers-1.0.yaml&lt;br /&gt;</description>
            <author>broel</author>
            <pubDate>Thu, 02 Nov 2017 14:04:16 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=virtex7_pcie_dma&amp;path=%2Fvirtex7_pcie_dma%2F&amp;rev=39</guid>
        </item>
        <item>
            <title>Fixed include of stdint.h</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=virtex7_pcie_dma&amp;path=%2Fvirtex7_pcie_dma%2F&amp;rev=38</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 38 - broel&lt;/strong&gt; (2 file(s) modified)&lt;/div&gt;&lt;div&gt;Fixed include of stdint.h&lt;/div&gt;~ /virtex7_pcie_dma/trunk/software/wupper_gui/include/chaintest-thread.h&lt;br /&gt;~ /virtex7_pcie_dma/trunk/software/wupper_gui/include/throughput-thread.h&lt;br /&gt;</description>
            <author>broel</author>
            <pubDate>Wed, 25 Oct 2017 07:27:50 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=virtex7_pcie_dma&amp;path=%2Fvirtex7_pcie_dma%2F&amp;rev=38</guid>
        </item>
        <item>
            <title>* Added WupperCodeGen, a tool to generate the registermap vhdl, ...</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=virtex7_pcie_dma&amp;path=%2Fvirtex7_pcie_dma%2F&amp;rev=37</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 37 - fransschreuder&lt;/strong&gt; (295 file(s) modified)&lt;/div&gt;&lt;div&gt;* Added WupperCodeGen, a tool to generate the registermap vhdl, ...&lt;/div&gt;~ /virtex7_pcie_dma/trunk/documentation/customizing.tex&lt;br /&gt;~ /virtex7_pcie_dma/trunk/documentation/example_application/figures/benchmark_application.pdf&lt;br /&gt;~ /virtex7_pcie_dma/trunk/documentation/example_application/internship-wupper.pdf&lt;br /&gt;~ /virtex7_pcie_dma/trunk/documentation/example_application/wupper.tex&lt;br /&gt;~ /virtex7_pcie_dma/trunk/documentation/figures/Endless_DMA_diagram.pdf&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/registermap.tex&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/registermap.tex.template&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/registers-1.0.html&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/registers.html.template&lt;br /&gt;- /virtex7_pcie_dma/trunk/documentation/regmap.tex&lt;br /&gt;~ /virtex7_pcie_dma/trunk/documentation/wupper.pdf&lt;br /&gt;~ /virtex7_pcie_dma/trunk/documentation/wupper.tex&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/constraints/pcie_dma_top_HTG710.xdc&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/constraints/pcie_dma_top_kcu105.xdc&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/constraints/pcie_dma_top_VC709.xdc&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/scripts/Wupper/do_implementation_HTG710.tcl&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/scripts/Wupper/do_implementation_KCU105.tcl&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/scripts/Wupper/do_implementation_VC709.tcl&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/scripts/Wupper/vivado_import_kintexultrascale.tcl&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/scripts/Wupper/vivado_import_virtex7.tcl&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/sources/application/application.vhd&lt;br /&gt;- /virtex7_pcie_dma/trunk/firmware/sources/application/fifo_256x256.xci&lt;br /&gt;- /virtex7_pcie_dma/trunk/firmware/sources/application/fifo_256x512.xci&lt;br /&gt;- /virtex7_pcie_dma/trunk/firmware/sources/application/multiplier.xci&lt;br /&gt;- /virtex7_pcie_dma/trunk/firmware/sources/application/pcie_x8_gen3_3_0.xci&lt;br /&gt;- /virtex7_pcie_dma/trunk/firmware/sources/application/system_management_wiz_0.xci&lt;br /&gt;- /virtex7_pcie_dma/trunk/firmware/sources/application/xadc_wiz_0.xci&lt;br /&gt;+ /virtex7_pcie_dma/trunk/firmware/sources/ip_cores&lt;br /&gt;+ /virtex7_pcie_dma/trunk/firmware/sources/ip_cores/ku&lt;br /&gt;+ /virtex7_pcie_dma/trunk/firmware/sources/ip_cores/ku/clk_wiz_40.xci&lt;br /&gt;+ /virtex7_pcie_dma/trunk/firmware/sources/ip_cores/ku/fifo4KB_256bit.xci&lt;br /&gt;+ /virtex7_pcie_dma/trunk/firmware/sources/ip_cores/ku/fifo128KB_256bit.xci&lt;br /&gt;+ /virtex7_pcie_dma/trunk/firmware/sources/ip_cores/ku/I2C_RDFifo.xci&lt;br /&gt;+ /virtex7_pcie_dma/trunk/firmware/sources/ip_cores/ku/I2C_WRFifo.xci&lt;br /&gt;+ /virtex7_pcie_dma/trunk/firmware/sources/ip_cores/ku/pcie3_ultrascale_7038.xci&lt;br /&gt;+ /virtex7_pcie_dma/trunk/firmware/sources/ip_cores/ku/pcie3_ultrascale_7039.xci&lt;br /&gt;+ /virtex7_pcie_dma/trunk/firmware/sources/ip_cores/ku/pcie_x8_gen3_3_0_stub.vhdl&lt;br /&gt;+ /virtex7_pcie_dma/trunk/firmware/sources/ip_cores/ku/system_management_wiz_0.xci&lt;br /&gt;+ /virtex7_pcie_dma/trunk/firmware/sources/ip_cores/ku/xadc_wiz_0_stub.vhdl&lt;br /&gt;+ /virtex7_pcie_dma/trunk/firmware/sources/ip_cores/virtex7&lt;br /&gt;+ /virtex7_pcie_dma/trunk/firmware/sources/ip_cores/virtex7/clk_wiz_40.xci&lt;br /&gt;+ /virtex7_pcie_dma/trunk/firmware/sources/ip_cores/virtex7/fifo4KB_256bit.xci&lt;br /&gt;+ /virtex7_pcie_dma/trunk/firmware/sources/ip_cores/virtex7/fifo128KB_256bit.xci&lt;br /&gt;+ /virtex7_pcie_dma/trunk/firmware/sources/ip_cores/virtex7/I2C_RDFifo.xci&lt;br /&gt;+ /virtex7_pcie_dma/trunk/firmware/sources/ip_cores/virtex7/I2C_WRFifo.xci&lt;br /&gt;+ /virtex7_pcie_dma/trunk/firmware/sources/ip_cores/virtex7/multiplier.xci&lt;br /&gt;+ /virtex7_pcie_dma/trunk/firmware/sources/ip_cores/virtex7/pcie3_ultrascale_7038_stub.vhdl&lt;br /&gt;+ /virtex7_pcie_dma/trunk/firmware/sources/ip_cores/virtex7/pcie3_ultrascale_7039_stub.vhdl&lt;br /&gt;+ /virtex7_pcie_dma/trunk/firmware/sources/ip_cores/virtex7/pcie_x8_gen3_3_0.xci&lt;br /&gt;+ /virtex7_pcie_dma/trunk/firmware/sources/ip_cores/virtex7/system_management_wiz_0_stub.vhdl&lt;br /&gt;+ /virtex7_pcie_dma/trunk/firmware/sources/ip_cores/virtex7/xadc_wiz_0.xci&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/sources/packages/pcie_package.vhd&lt;br /&gt;- /virtex7_pcie_dma/trunk/firmware/sources/pcie/clk_wiz_40.xci&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/sources/pcie/dma_control.vhd&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/sources/pcie/dma_read_write.vhd&lt;br /&gt;- /virtex7_pcie_dma/trunk/firmware/sources/pcie/pcie3_ultrascale_7038.xci&lt;br /&gt;- /virtex7_pcie_dma/trunk/firmware/sources/pcie/pcie3_ultrascale_7039.xci&lt;br /&gt;- /virtex7_pcie_dma/trunk/firmware/sources/pcie/pcie3_x8_gen3.xci&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/sources/pcie/pcie_slow_clock.vhd&lt;br /&gt;- /virtex7_pcie_dma/trunk/firmware/sources/pcie/pcie_x8_gen3_3_0.xci&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/sources/pcie/wupper.vhd&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/sources/pcie/wupper_core.vhd&lt;br /&gt;- /virtex7_pcie_dma/trunk/firmware/sources/shared/clock_and_reset.vhd&lt;br /&gt;+ /virtex7_pcie_dma/trunk/firmware/sources/shared/dna.vhd&lt;br /&gt;+ /virtex7_pcie_dma/trunk/firmware/sources/shared/housekeeping.vhd&lt;br /&gt;+ /virtex7_pcie_dma/trunk/firmware/sources/shared/i2c.vhd&lt;br /&gt;+ /virtex7_pcie_dma/trunk/firmware/sources/shared/i2c_interface.vhd&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/sources/shared/wupper_oc_top.vhd&lt;br /&gt;+ /virtex7_pcie_dma/trunk/firmware/sources/templates&lt;br /&gt;+ /virtex7_pcie_dma/trunk/firmware/sources/templates/dma_control.vhd.template&lt;br /&gt;+ /virtex7_pcie_dma/trunk/firmware/sources/templates/pcie_package.vhd.template&lt;br /&gt;- /virtex7_pcie_dma/trunk/hostSoftware&lt;br /&gt;+ /virtex7_pcie_dma/trunk/software&lt;br /&gt;+ /virtex7_pcie_dma/trunk/software/DFDebug&lt;br /&gt;+ /virtex7_pcie_dma/trunk/software/DFDebug/CMakeLists.txt&lt;br /&gt;+ /virtex7_pcie_dma/trunk/software/DFDebug/DFDebug&lt;br /&gt;+ /virtex7_pcie_dma/trunk/software/DFDebug/DFDebug/DFDebug.h&lt;br /&gt;+ /virtex7_pcie_dma/trunk/software/DFDebug/DFDebug/GlobalDebugSettings.h&lt;br /&gt;+ /virtex7_pcie_dma/trunk/software/DFDebug/doc&lt;br /&gt;+ /virtex7_pcie_dma/trunk/software/DFDebug/doc/RELEASE_NOTES&lt;br /&gt;+ /virtex7_pcie_dma/trunk/software/DFDebug/src&lt;br /&gt;+ /virtex7_pcie_dma/trunk/software/DFDebug/src/GlobalDebugSettings.cpp&lt;br /&gt;- /virtex7_pcie_dma/trunk/software/driver&lt;br /&gt;+ /virtex7_pcie_dma/trunk/software/drivers&lt;br /&gt;+ /virtex7_pcie_dma/trunk/software/drivers/CMakeLists.txt&lt;br /&gt;+ /virtex7_pcie_dma/trunk/software/drivers/cmem_rcc&lt;br /&gt;+ /virtex7_pcie_dma/trunk/software/drivers/cmem_rcc/cmem_rcc.h&lt;br /&gt;+ /virtex7_pcie_dma/trunk/software/drivers/cmem_rcc/cmem_rcc_common.h&lt;br /&gt;+ /virtex7_pcie_dma/trunk/software/drivers/cmem_rcc/cmem_rcc_drv.h&lt;br /&gt;+ /virtex7_pcie_dma/trunk/software/drivers/drivers&lt;br /&gt;+ /virtex7_pcie_dma/trunk/software/drivers/README.txt&lt;br /&gt;+ /virtex7_pcie_dma/trunk/software/drivers/scripts&lt;br /&gt;+ /virtex7_pcie_dma/trunk/software/drivers/scripts/drivers_wupper&lt;br /&gt;+ /virtex7_pcie_dma/trunk/software/drivers/scripts/drivers_wupper_local&lt;br /&gt;+ /virtex7_pcie_dma/trunk/software/drivers/src&lt;br /&gt;+ /virtex7_pcie_dma/trunk/software/drivers/src/cmem_rcc.c&lt;br /&gt;+ /virtex7_pcie_dma/trunk/software/drivers/src/lib&lt;br /&gt;+ /virtex7_pcie_dma/trunk/software/drivers/src/lib/cmem_rcc_lib.cpp&lt;br /&gt;+ /virtex7_pcie_dma/trunk/software/drivers/src/Makefile&lt;br /&gt;+ /virtex7_pcie_dma/trunk/software/drivers/src/wupper.c&lt;br /&gt;+ /virtex7_pcie_dma/trunk/software/drivers/wupper&lt;br /&gt;+ /virtex7_pcie_dma/trunk/software/drivers/wupper/wupper_common.h&lt;br /&gt;+ /virtex7_pcie_dma/trunk/software/rcc_error&lt;br /&gt;+ /virtex7_pcie_dma/trunk/software/rcc_error/CMakeLists.txt&lt;br /&gt;+ /virtex7_pcie_dma/trunk/software/rcc_error/rcc_error&lt;br /&gt;+ /virtex7_pcie_dma/trunk/software/rcc_error/rcc_error/rcc_error.h&lt;br /&gt;+ /virtex7_pcie_dma/trunk/software/rcc_error/src&lt;br /&gt;+ /virtex7_pcie_dma/trunk/software/rcc_error/src/rcc_error.cpp&lt;br /&gt;+ /virtex7_pcie_dma/trunk/software/README.md&lt;br /&gt;+ /virtex7_pcie_dma/trunk/software/regmap&lt;br /&gt;+ /virtex7_pcie_dma/trunk/software/regmap/CMakeLists.txt&lt;br /&gt;+ /virtex7_pcie_dma/trunk/software/regmap/README.md&lt;br /&gt;+ /virtex7_pcie_dma/trunk/software/regmap/regmap&lt;br /&gt;+ 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/virtex7_pcie_dma/trunk/software/wupper_tools/tools&lt;br /&gt;+ /virtex7_pcie_dma/trunk/software/wupper_tools/version.h&lt;br /&gt;+ /virtex7_pcie_dma/trunk/software/wupper_tools/wupper&lt;br /&gt;- /virtex7_pcie_dma/trunk/software/wupper_tools/wupper-chaintest.c&lt;br /&gt;- /virtex7_pcie_dma/trunk/software/wupper_tools/wupper-config.c&lt;br /&gt;- /virtex7_pcie_dma/trunk/software/wupper_tools/wupper-dma-test.cpp&lt;br /&gt;- /virtex7_pcie_dma/trunk/software/wupper_tools/wupper-dma-transfer.c&lt;br /&gt;- /virtex7_pcie_dma/trunk/software/wupper_tools/wupper-info.c&lt;br /&gt;- /virtex7_pcie_dma/trunk/software/wupper_tools/wupper-irq-test.c&lt;br /&gt;- /virtex7_pcie_dma/trunk/software/wupper_tools/wupper-reset.c&lt;br /&gt;- /virtex7_pcie_dma/trunk/software/wupper_tools/wupper-throughput.c&lt;br /&gt;- /virtex7_pcie_dma/trunk/software/wupper_tools/wupper-write.c&lt;br /&gt;- /virtex7_pcie_dma/trunk/software/wupper_tools/wupper.c&lt;br /&gt;- /virtex7_pcie_dma/trunk/software/wupper_tools/wupper.h&lt;br /&gt;+ /virtex7_pcie_dma/trunk/software/wupper_tools/wupper/Wupper.h&lt;br /&gt;+ /virtex7_pcie_dma/trunk/software/wupper_tools/wupper/WupperException.h&lt;br /&gt;+ /virtex7_pcie_dma/trunk/WupperCodeGenScripts&lt;br /&gt;+ /virtex7_pcie_dma/trunk/WupperCodeGenScripts/build-doc.sh&lt;br /&gt;+ /virtex7_pcie_dma/trunk/WupperCodeGenScripts/build-firmware.sh&lt;br /&gt;+ /virtex7_pcie_dma/trunk/WupperCodeGenScripts/build-software.sh&lt;br /&gt;+ /virtex7_pcie_dma/trunk/WupperCodeGenScripts/registers-1.0.yaml&lt;br /&gt;</description>
            <author>fransschreuder</author>
            <pubDate>Tue, 24 Oct 2017 14:44:56 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=virtex7_pcie_dma&amp;path=%2Fvirtex7_pcie_dma%2F&amp;rev=37</guid>
        </item>
        <item>
            <title>Updated documentation</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=virtex7_pcie_dma&amp;path=%2Fvirtex7_pcie_dma%2F&amp;rev=36</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 36 - fransschreuder&lt;/strong&gt; (55 file(s) modified)&lt;/div&gt;&lt;div&gt;Updated documentation&lt;/div&gt;+ /virtex7_pcie_dma/trunk/documentation/benchmark.tex&lt;br /&gt;~ /virtex7_pcie_dma/trunk/documentation/bibliography.tex&lt;br /&gt;~ /virtex7_pcie_dma/trunk/documentation/customizing.tex&lt;br /&gt;~ /virtex7_pcie_dma/trunk/documentation/design.tex&lt;br /&gt;~ /virtex7_pcie_dma/trunk/documentation/et_template/template.tex&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/example_application.tex&lt;br /&gt;~ /virtex7_pcie_dma/trunk/documentation/example_application/internship-wupper.pdf&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/figures&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/figures/benchmark_application.pdf&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/figures/blocksize_plot.pdf&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/figures/dma_core_structure.odg&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/figures/dma_core_structure.pdf&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/figures/dma_core_structure.png&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/figures/Endless_DMA_diagram.pdf&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/figures/full_application_structure.pdf&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/figures/generate_output_products.png&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/figures/gui_printscreen_tb.PNG&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/figures/lfsr.pdf&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/figures/oclogo.jpg&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/figures/pcie_core_basic.png&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/figures/pcie_core_config1.pdf&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/figures/pcie_core_config2.pdf&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/figures/pcie_core_config3.pdf&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/figures/pcie_core_config4.pdf&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/figures/pcie_core_config5.pdf&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/figures/pcie_core_coreintpar.png&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/figures/pcie_core_extcapa1.png&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/figures/pcie_core_extcapa2.png&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/figures/pcie_core_legaciMSI.png&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/figures/pcie_core_msix.png&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/figures/pcie_core_pf0_bar.png&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/figures/pcie_core_pwr.png&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/figures/pcie_core_shared.png&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/figures/PG023.pdf&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/figures/random_wupper_orange.pdf&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/figures/tree.pdf&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/figures/wupper_gui_threads_overview.pdf&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/figures/wupper_package_simple.pdf&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/figures/wupper_structure.odg&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/figures/wupper_structure.pdf&lt;br /&gt;~ /virtex7_pcie_dma/trunk/documentation/introduction.tex&lt;br /&gt;~ /virtex7_pcie_dma/trunk/documentation/obtaining.tex&lt;br /&gt;- /virtex7_pcie_dma/trunk/documentation/pcie_dma_core.pdf&lt;br /&gt;- /virtex7_pcie_dma/trunk/documentation/pcie_dma_core.tex&lt;br /&gt;- /virtex7_pcie_dma/trunk/documentation/pictures&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/regmap.tex&lt;br /&gt;~ /virtex7_pcie_dma/trunk/documentation/simulation.tex&lt;br /&gt;~ /virtex7_pcie_dma/trunk/documentation/testing.tex&lt;br /&gt;~ /virtex7_pcie_dma/trunk/documentation/titlepage.tex&lt;br /&gt;~ /virtex7_pcie_dma/trunk/documentation/versionhistory.tex&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/wupper.pdf&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/wupper.tex&lt;br /&gt;~ /virtex7_pcie_dma/trunk/documentation/xilinx_core.tex&lt;br /&gt;~ /virtex7_pcie_dma/trunk/hostSoftware/driver/cmem/cmem.c&lt;br /&gt;~ /virtex7_pcie_dma/trunk/hostSoftware/driver/scripts/drivers_wupper&lt;br /&gt;</description>
            <author>fransschreuder</author>
            <pubDate>Wed, 23 Nov 2016 13:52:50 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=virtex7_pcie_dma&amp;path=%2Fvirtex7_pcie_dma%2F&amp;rev=36</guid>
        </item>
        <item>
            <title>FIXED:
 * PCIe lock when reading registers on a high ...</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=virtex7_pcie_dma&amp;path=%2Fvirtex7_pcie_dma%2F&amp;rev=35</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 35 - fransschreuder&lt;/strong&gt; (9 file(s) modified)&lt;/div&gt;&lt;div&gt;FIXED:&lt;br /&gt;
 * PCIe lock when reading registers on a high ...&lt;/div&gt;~ /virtex7_pcie_dma/trunk/firmware/sources/application/application.vhd&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/sources/packages/pcie_package.vhd&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/sources/pcie/dma_control.vhd&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/sources/pcie/dma_read_write.vhd&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/sources/pcie/pcie_ep_wrap.vhd&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/sources/pcie/pcie_init.vhd&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/sources/pcie/wupper.vhd&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/sources/pcie/wupper_core.vhd&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/sources/shared/wupper_oc_top.vhd&lt;br /&gt;</description>
            <author>fransschreuder</author>
            <pubDate>Fri, 30 Sep 2016 09:11:53 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=virtex7_pcie_dma&amp;path=%2Fvirtex7_pcie_dma%2F&amp;rev=35</guid>
        </item>
        <item>
            <title>FIXED:
 * Wrong TLP length reported on register writes
 * ...</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=virtex7_pcie_dma&amp;path=%2Fvirtex7_pcie_dma%2F&amp;rev=34</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 34 - fransschreuder&lt;/strong&gt; (17 file(s) modified)&lt;/div&gt;&lt;div&gt;FIXED:&lt;br /&gt;
 * Wrong TLP length reported on register writes&lt;br /&gt;
 * ...&lt;/div&gt;- /virtex7_pcie_dma/trunk/firmware/scripts/Wupper/vivado_import.tcl&lt;br /&gt;+ /virtex7_pcie_dma/trunk/firmware/scripts/Wupper/vivado_import_kintexultrascale.tcl&lt;br /&gt;+ /virtex7_pcie_dma/trunk/firmware/scripts/Wupper/vivado_import_virtex7.tcl&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/sources/application/application.vhd&lt;br /&gt;+ /virtex7_pcie_dma/trunk/firmware/sources/application/system_management_wiz_0.xci&lt;br /&gt;+ /virtex7_pcie_dma/trunk/firmware/sources/application/xadc_drp.vhd&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/sources/application/xadc_wiz_0.xci&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/sources/packages/pcie_package.vhd&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/sources/pcie/clk_wiz_40.xci&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/sources/pcie/dma_control.vhd&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/sources/pcie/intr_ctrl.vhd&lt;br /&gt;+ /virtex7_pcie_dma/trunk/firmware/sources/pcie/pcie3_ultrascale_7038.xci&lt;br /&gt;+ /virtex7_pcie_dma/trunk/firmware/sources/pcie/pcie3_ultrascale_7039.xci&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/sources/pcie/pcie_ep_wrap.vhd&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/sources/pcie/pcie_x8_gen3_3_0.xci&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/sources/pcie/wupper.vhd&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/sources/shared/wupper_oc_top.vhd&lt;br /&gt;</description>
            <author>fransschreuder</author>
            <pubDate>Thu, 16 Jun 2016 14:29:02 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=virtex7_pcie_dma&amp;path=%2Fvirtex7_pcie_dma%2F&amp;rev=34</guid>
        </item>
        <item>
            <title>ADDED:
  -- supportedtools.tex, again to test the OC repo</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=virtex7_pcie_dma&amp;path=%2Fvirtex7_pcie_dma%2F&amp;rev=33</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 33 - aborga&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;ADDED:&lt;br /&gt;
  -- supportedtools.tex, again to test the OC repo&lt;/div&gt;+ /virtex7_pcie_dma/trunk/documentation/supportedtools.tex&lt;br /&gt;</description>
            <author>aborga</author>
            <pubDate>Mon, 02 May 2016 15:36:41 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=virtex7_pcie_dma&amp;path=%2Fvirtex7_pcie_dma%2F&amp;rev=33</guid>
        </item>
        <item>
            <title>MODIFIED:
 -- minor things just to test OC svn repo</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=virtex7_pcie_dma&amp;path=%2Fvirtex7_pcie_dma%2F&amp;rev=32</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 32 - aborga&lt;/strong&gt; (2 file(s) modified)&lt;/div&gt;&lt;div&gt;MODIFIED:&lt;br /&gt;
 -- minor things just to test OC svn repo&lt;/div&gt;~ /virtex7_pcie_dma/trunk/documentation/pcie_dma_core.pdf&lt;br /&gt;~ /virtex7_pcie_dma/trunk/documentation/pcie_dma_core.tex&lt;br /&gt;</description>
            <author>aborga</author>
            <pubDate>Mon, 02 May 2016 15:32:50 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=virtex7_pcie_dma&amp;path=%2Fvirtex7_pcie_dma%2F&amp;rev=32</guid>
        </item>
        <item>
            <title>Added example application documentation.</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=virtex7_pcie_dma&amp;path=%2Fvirtex7_pcie_dma%2F&amp;rev=31</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 31 - oussamak&lt;/strong&gt; (55 file(s) modified)&lt;/div&gt;&lt;div&gt;Added example application documentation.&lt;/div&gt;+ /virtex7_pcie_dma/trunk/documentation/example_application&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/example_application/appendix.tex&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/example_application/conclusion.tex&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/example_application/et_template&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/example_application/et_template/pictures&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/example_application/et_template/pictures/footer.png&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/example_application/et_template/pictures/NIKHEF.pdf&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/example_application/et_template/template.tex&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/example_application/et_template/titlepage.tex&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/example_application/figures&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/example_application/figures/benchmark_application.pdf&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/example_application/figures/blocksize_plot.pdf&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/example_application/figures/dma_core_structure.png&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/example_application/figures/fifos_full.pdf&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/example_application/figures/fifo_full_inverted.png&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/example_application/figures/full_application_structure.pdf&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/example_application/figures/generate_output_products.png&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/example_application/figures/gui_printscreen.jpg&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/example_application/figures/gui_printscreen_tb.PNG&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/example_application/figures/gui_screenshot.png&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/example_application/figures/ILA.png&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/example_application/figures/ila_inverted.png&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/example_application/figures/ila_inverted_scaled.png&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/example_application/figures/lfsr.pdf&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/example_application/figures/lfsr.png&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/example_application/figures/lfsr_mul_inverted.png&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/example_application/figures/LFSR_sim_inverted.png&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/example_application/figures/oclogo.jpg&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/example_application/figures/PG023.pdf&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/example_application/figures/pipeline_mul_2early.png&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/example_application/figures/pipeline_mul_2early_inverted.png&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/example_application/figures/random_wupper_orange.pdf&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/example_application/figures/sim_lfsr_output.pdf&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/example_application/figures/softwaretree.png&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/example_application/figures/TDAQ_block_diagram.png&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/example_application/figures/TDAQ_block_diagram_desaturated.png&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/example_application/figures/tools_and_workflow.pdf&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/example_application/figures/tree.pdf&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/example_application/figures/veriflow.pdf&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/example_application/figures/veriflow_draw.png&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/example_application/figures/wuppertool.pdf&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/example_application/figures/wupper_gui_threads.pdf&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/example_application/figures/wupper_gui_threads_overview.pdf&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/example_application/figures/wupper_package_simple.pdf&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/example_application/figures/wupper_package_simple.png&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/example_application/figures/wupper_structure.pdf&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/example_application/figures/wupper_tool.png&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/example_application/internship-wupper.pdf&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/example_application/internship-wupper.tex&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/example_application/introduction.tex&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/example_application/reference.tex&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/example_application/tableofcontents.tex&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/example_application/titlepage.tex&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/example_application/verification.tex&lt;br /&gt;+ /virtex7_pcie_dma/trunk/documentation/example_application/wupper.tex&lt;br /&gt;</description>
            <author>oussamak</author>
            <pubDate>Fri, 29 Jan 2016 13:42:46 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=virtex7_pcie_dma&amp;path=%2Fvirtex7_pcie_dma%2F&amp;rev=31</guid>
        </item>
        <item>
            <title>Added: 
  * Wupper GUI with speed test and ...</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=virtex7_pcie_dma&amp;path=%2Fvirtex7_pcie_dma%2F&amp;rev=30</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 30 - oussamak&lt;/strong&gt; (24 file(s) modified)&lt;/div&gt;&lt;div&gt;Added: &lt;br /&gt;
  * Wupper GUI with speed test and ...&lt;/div&gt;+ /virtex7_pcie_dma/trunk/hostSoftware/wupper_gui&lt;br /&gt;+ /virtex7_pcie_dma/trunk/hostSoftware/wupper_gui/chain-test.cpp&lt;br /&gt;+ /virtex7_pcie_dma/trunk/hostSoftware/wupper_gui/chaintest-thread.h&lt;br /&gt;+ /virtex7_pcie_dma/trunk/hostSoftware/wupper_gui/main.cpp&lt;br /&gt;+ /virtex7_pcie_dma/trunk/hostSoftware/wupper_gui/measure-throughput.cpp&lt;br /&gt;+ /virtex7_pcie_dma/trunk/hostSoftware/wupper_gui/qcustomplot.cpp&lt;br /&gt;+ /virtex7_pcie_dma/trunk/hostSoftware/wupper_gui/qcustomplot.h&lt;br /&gt;+ /virtex7_pcie_dma/trunk/hostSoftware/wupper_gui/throughput-thread.h&lt;br /&gt;+ /virtex7_pcie_dma/trunk/hostSoftware/wupper_gui/wupper_gui.cpp&lt;br /&gt;+ /virtex7_pcie_dma/trunk/hostSoftware/wupper_gui/wupper_gui.h&lt;br /&gt;+ /virtex7_pcie_dma/trunk/hostSoftware/wupper_gui/Wupper_gui.pro&lt;br /&gt;+ /virtex7_pcie_dma/trunk/hostSoftware/wupper_gui/Wupper_gui.ui&lt;br /&gt;~ /virtex7_pcie_dma/trunk/hostSoftware/wupper_tools/CMakeLists.txt&lt;br /&gt;~ /virtex7_pcie_dma/trunk/hostSoftware/wupper_tools/cmem.c&lt;br /&gt;~ /virtex7_pcie_dma/trunk/hostSoftware/wupper_tools/dma.c&lt;br /&gt;~ /virtex7_pcie_dma/trunk/hostSoftware/wupper_tools/registers.c&lt;br /&gt;+ /virtex7_pcie_dma/trunk/hostSoftware/wupper_tools/wupper-chaintest.c&lt;br /&gt;~ /virtex7_pcie_dma/trunk/hostSoftware/wupper_tools/wupper-dma-test.cpp&lt;br /&gt;+ /virtex7_pcie_dma/trunk/hostSoftware/wupper_tools/wupper-dma-transfer.c&lt;br /&gt;~ /virtex7_pcie_dma/trunk/hostSoftware/wupper_tools/wupper-info.c&lt;br /&gt;~ /virtex7_pcie_dma/trunk/hostSoftware/wupper_tools/wupper-reset.c&lt;br /&gt;~ /virtex7_pcie_dma/trunk/hostSoftware/wupper_tools/wupper-throughput.c&lt;br /&gt;+ /virtex7_pcie_dma/trunk/hostSoftware/wupper_tools/wupper-write.c&lt;br /&gt;~ /virtex7_pcie_dma/trunk/hostSoftware/wupper_tools/wupper.h&lt;br /&gt;</description>
            <author>oussamak</author>
            <pubDate>Fri, 29 Jan 2016 13:00:01 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=virtex7_pcie_dma&amp;path=%2Fvirtex7_pcie_dma%2F&amp;rev=30</guid>
        </item>
        <item>
            <title>Improved application to reflect both up and down transfers</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=virtex7_pcie_dma&amp;path=%2Fvirtex7_pcie_dma%2F&amp;rev=29</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 29 - fransschreuder&lt;/strong&gt; (14 file(s) modified)&lt;/div&gt;&lt;div&gt;Improved application to reflect both up and down transfers&lt;/div&gt;~ /virtex7_pcie_dma/trunk/firmware/scripts/Wupper/vivado_import.tcl&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/simulation/Wupper/project.do&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/simulation/Wupper/start.do&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/simulation/Wupper/VSim_Functional.tcl&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/simulation/Wupper/wave.do&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/sources/application/application.vhd&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/sources/application/fifo_256x256.xci&lt;br /&gt;+ /virtex7_pcie_dma/trunk/firmware/sources/application/fifo_256x512.xci&lt;br /&gt;+ /virtex7_pcie_dma/trunk/firmware/sources/application/LFSR.vhd&lt;br /&gt;+ /virtex7_pcie_dma/trunk/firmware/sources/application/multiplier.xci&lt;br /&gt;+ /virtex7_pcie_dma/trunk/firmware/sources/application/pcie_x8_gen3_3_0.xci&lt;br /&gt;+ /virtex7_pcie_dma/trunk/firmware/sources/application/xadc_wiz_0.xci&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/sources/packages/pcie_package.vhd&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/sources/pcie/dma_control.vhd&lt;br /&gt;</description>
            <author>fransschreuder</author>
            <pubDate>Fri, 18 Dec 2015 15:33:48 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=virtex7_pcie_dma&amp;path=%2Fvirtex7_pcie_dma%2F&amp;rev=29</guid>
        </item>
        <item>
            <title>Added registermap reset</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=virtex7_pcie_dma&amp;path=%2Fvirtex7_pcie_dma%2F&amp;rev=28</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 28 - fransschreuder&lt;/strong&gt; (2 file(s) modified)&lt;/div&gt;&lt;div&gt;Added registermap reset&lt;/div&gt;~ /virtex7_pcie_dma/trunk/firmware/sources/packages/pcie_package.vhd&lt;br /&gt;~ /virtex7_pcie_dma/trunk/firmware/sources/pcie/dma_control.vhd&lt;br /&gt;</description>
            <author>fransschreuder</author>
            <pubDate>Fri, 18 Dec 2015 13:06:08 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=virtex7_pcie_dma&amp;path=%2Fvirtex7_pcie_dma%2F&amp;rev=28</guid>
        </item>
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