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https://opencores.org/websvn//websvn/listing?repname=wbddr3&path=%2Fwbddr3%2Ftrunk%2F&
Fri, 02 Oct 2026 15:46:24 +0100FeedCreator 1.7.2Added formal verification properties
This core now passes formal verification.
https://opencores.org/websvn//websvn/revision?repname=wbddr3&path=%2Fwbddr3%2Ftrunk%2F&rev=21
<div><strong>Rev 21 - dgisselq</strong> (3 file(s) modified)</div><div>Added formal verification properties<br />
<br />
This core now passes formal verification.</div>~ /wbddr3/trunk/bench/cpp/Makefile<br />+ /wbddr3/trunk/README.md<br />~ /wbddr3/trunk/rtl/wbddrsdram.v<br />dgisselqFri, 23 Aug 2019 12:06:27 +0100https://opencores.org/websvn//websvn/revision?repname=wbddr3&path=%2Fwbddr3%2Ftrunk%2F&rev=21Made the bench/cpp Makefile independent of the Verilator root
https://opencores.org/websvn//websvn/revision?repname=wbddr3&path=%2Fwbddr3%2Ftrunk%2F&rev=20
<div><strong>Rev 20 - dgisselq</strong> (1 file(s) modified)</div><div>Made the bench/cpp Makefile independent of the Verilator root</div>~ /wbddr3/trunk/bench/cpp/Makefile<br />dgisselqMon, 17 Oct 2016 22:01:39 +0100https://opencores.org/websvn//websvn/revision?repname=wbddr3&path=%2Fwbddr3%2Ftrunk%2F&rev=20Cleaned up the controller, corrected comments, tried to make it ...
https://opencores.org/websvn//websvn/revision?repname=wbddr3&path=%2Fwbddr3%2Ftrunk%2F&rev=19
<div><strong>Rev 19 - dgisselq</strong> (1 file(s) modified)</div><div>Cleaned up the controller, corrected comments, tried to make it ...</div>~ /wbddr3/trunk/rtl/wbddrsdram.v<br />dgisselqMon, 17 Oct 2016 20:26:05 +0100https://opencores.org/websvn//websvn/revision?repname=wbddr3&path=%2Fwbddr3%2Ftrunk%2F&rev=19We now pass all tests again--this time for a 4:1 ...
https://opencores.org/websvn//websvn/revision?repname=wbddr3&path=%2Fwbddr3%2Ftrunk%2F&rev=18
<div><strong>Rev 18 - dgisselq</strong> (13 file(s) modified)</div><div>We now pass all tests again--this time for a 4:1 ...</div>~ /wbddr3/trunk/bench/cpp/ddrsdramsim.cpp<br />~ /wbddr3/trunk/bench/cpp/ddrsdramsim.h<br />~ /wbddr3/trunk/bench/cpp/ddrsdram_tb.cpp<br />~ /wbddr3/trunk/bench/cpp/pddrsim.cpp<br />~ /wbddr3/trunk/bench/cpp/pddrsim.h<br />~ /wbddr3/trunk/doc/gfx/refresh.eps<br />~ /wbddr3/trunk/doc/gfx/refresh.png<br />~ /wbddr3/trunk/doc/gfx/singleread.eps<br />~ /wbddr3/trunk/doc/gfx/singleread.png<br />~ /wbddr3/trunk/doc/gfx/singlewrite.eps<br />~ /wbddr3/trunk/doc/gfx/singlewrite.png<br />~ /wbddr3/trunk/Makefile<br />~ /wbddr3/trunk/rtl/wbddrsdram.v<br />dgisselqSat, 17 Sep 2016 02:46:19 +0100https://opencores.org/websvn//websvn/revision?repname=wbddr3&path=%2Fwbddr3%2Ftrunk%2F&rev=18Here are files from my current attempts to include the ...
https://opencores.org/websvn//websvn/revision?repname=wbddr3&path=%2Fwbddr3%2Ftrunk%2F&rev=17
<div><strong>Rev 17 - dgisselq</strong> (4 file(s) modified)</div><div>Here are files from my current attempts to include the ...</div>+ /wbddr3/trunk/rtl/ddr3insert.v<br />~ /wbddr3/trunk/rtl/wbddrsdram.v<br />+ /wbddr3/trunk/rtl/xioddrserdes.v<br />+ /wbddr3/trunk/rtl/xoddrserdes.v<br />dgisselqTue, 23 Aug 2016 21:01:36 +0100https://opencores.org/websvn//websvn/revision?repname=wbddr3&path=%2Fwbddr3%2Ftrunk%2F&rev=17New, modified code, now works in simulation!!
https://opencores.org/websvn//websvn/revision?repname=wbddr3&path=%2Fwbddr3%2Ftrunk%2F&rev=16
<div><strong>Rev 16 - dgisselq</strong> (7 file(s) modified)</div><div>New, modified code, now works in simulation!!</div>~ /wbddr3/trunk/bench/cpp/ddrsdramsim.cpp<br />~ /wbddr3/trunk/bench/cpp/ddrsdramsim.h<br />~ /wbddr3/trunk/bench/cpp/ddrsdram_tb.cpp<br />~ /wbddr3/trunk/bench/cpp/Makefile<br />+ /wbddr3/trunk/bench/cpp/pddrsim.cpp<br />+ /wbddr3/trunk/bench/cpp/pddrsim.h<br />~ /wbddr3/trunk/rtl/wbddrsdram.v<br />dgisselqFri, 19 Aug 2016 22:03:15 +0100https://opencores.org/websvn//websvn/revision?repname=wbddr3&path=%2Fwbddr3%2Ftrunk%2F&rev=16Some simple timing diagrams, illustrating how we can go about ...
https://opencores.org/websvn//websvn/revision?repname=wbddr3&path=%2Fwbddr3%2Ftrunk%2F&rev=15
<div><strong>Rev 15 - dgisselq</strong> (7 file(s) modified)</div><div>Some simple timing diagrams, illustrating how we can go about ...</div>+ /wbddr3/trunk/doc/gfx<br />+ /wbddr3/trunk/doc/gfx/refresh.eps<br />+ /wbddr3/trunk/doc/gfx/refresh.png<br />+ /wbddr3/trunk/doc/gfx/singleread.eps<br />+ /wbddr3/trunk/doc/gfx/singleread.png<br />+ /wbddr3/trunk/doc/gfx/singlewrite.eps<br />+ /wbddr3/trunk/doc/gfx/singlewrite.png<br />dgisselqTue, 16 Aug 2016 16:06:37 +0100https://opencores.org/websvn//websvn/revision?repname=wbddr3&path=%2Fwbddr3%2Ftrunk%2F&rev=15Lots of changes. Redesigned the refresh logic, and the ...
https://opencores.org/websvn//websvn/revision?repname=wbddr3&path=%2Fwbddr3%2Ftrunk%2F&rev=14
<div><strong>Rev 14 - dgisselq</strong> (4 file(s) modified)</div><div>Lots of changes. Redesigned the refresh logic, and the ...</div>~ /wbddr3/trunk/bench/cpp/ddrsdramsim.cpp<br />~ /wbddr3/trunk/bench/cpp/ddrsdramsim.h<br />~ /wbddr3/trunk/bench/cpp/ddrsdram_tb.cpp<br />~ /wbddr3/trunk/rtl/wbddrsdram.v<br />dgisselqThu, 04 Aug 2016 01:18:06 +0100https://opencores.org/websvn//websvn/revision?repname=wbddr3&path=%2Fwbddr3%2Ftrunk%2F&rev=14Cleanup, bug fixes--sadly, the code no longer works, so while ...
https://opencores.org/websvn//websvn/revision?repname=wbddr3&path=%2Fwbddr3%2Ftrunk%2F&rev=13
<div><strong>Rev 13 - dgisselq</strong> (8 file(s) modified)</div><div>Cleanup, bug fixes--sadly, the code no longer works, so while ...</div>~ /wbddr3/trunk/bench/cpp/ddrsdramsim.cpp<br />~ /wbddr3/trunk/bench/cpp/ddrsdramsim.h<br />~ /wbddr3/trunk/bench/cpp/ddrsdram_tb.cpp<br />~ /wbddr3/trunk/bench/cpp/Makefile<br />~ /wbddr3/trunk/doc/spec.pdf<br />~ /wbddr3/trunk/doc/src/spec.tex<br />~ /wbddr3/trunk/Makefile<br />~ /wbddr3/trunk/rtl/wbddrsdram.v<br />dgisselqWed, 03 Aug 2016 02:06:07 +0100https://opencores.org/websvn//websvn/revision?repname=wbddr3&path=%2Fwbddr3%2Ftrunk%2F&rev=13Added the write-read and write-precharge extra delays into both module ...
https://opencores.org/websvn//websvn/revision?repname=wbddr3&path=%2Fwbddr3%2Ftrunk%2F&rev=12
<div><strong>Rev 12 - dgisselq</strong> (4 file(s) modified)</div><div>Added the write-read and write-precharge extra delays into both module ...</div>~ /wbddr3/trunk/bench/cpp/ddrsdramsim.cpp<br />~ /wbddr3/trunk/bench/cpp/ddrsdramsim.h<br />~ /wbddr3/trunk/bench/cpp/ddrsdram_tb.cpp<br />~ /wbddr3/trunk/rtl/wbddrsdram.v<br />dgisselqMon, 01 Aug 2016 21:44:03 +0100https://opencores.org/websvn//websvn/revision?repname=wbddr3&path=%2Fwbddr3%2Ftrunk%2F&rev=12Fixed the bugs Xilinx's tools pointed out.
https://opencores.org/websvn//websvn/revision?repname=wbddr3&path=%2Fwbddr3%2Ftrunk%2F&rev=11
<div><strong>Rev 11 - dgisselq</strong> (1 file(s) modified)</div><div>Fixed the bugs Xilinx's tools pointed out.</div>~ /wbddr3/trunk/rtl/wbddrsdram.v<br />dgisselqMon, 01 Aug 2016 20:34:26 +0100https://opencores.org/websvn//websvn/revision?repname=wbddr3&path=%2Fwbddr3%2Ftrunk%2F&rev=11This might just work ... at least, it passes my ...
https://opencores.org/websvn//websvn/revision?repname=wbddr3&path=%2Fwbddr3%2Ftrunk%2F&rev=10
<div><strong>Rev 10 - dgisselq</strong> (2 file(s) modified)</div><div>This might just work ... at least, it passes my ...</div>~ /wbddr3/trunk/bench/cpp/ddrsdram_tb.cpp<br />~ /wbddr3/trunk/rtl/wbddrsdram.v<br />dgisselqMon, 01 Aug 2016 19:46:26 +0100https://opencores.org/websvn//websvn/revision?repname=wbddr3&path=%2Fwbddr3%2Ftrunk%2F&rev=10Making progress: The singular write and pipe read tests work. ...
https://opencores.org/websvn//websvn/revision?repname=wbddr3&path=%2Fwbddr3%2Ftrunk%2F&rev=9
<div><strong>Rev 9 - dgisselq</strong> (3 file(s) modified)</div><div>Making progress: The singular write and pipe read tests work. ...</div>~ /wbddr3/trunk/bench/cpp/ddrsdramsim.cpp<br />~ /wbddr3/trunk/bench/cpp/ddrsdram_tb.cpp<br />~ /wbddr3/trunk/rtl/wbddrsdram.v<br />dgisselqMon, 01 Aug 2016 19:23:35 +0100https://opencores.org/websvn//websvn/revision?repname=wbddr3&path=%2Fwbddr3%2Ftrunk%2F&rev=9Singular reads and writes now work (in the Verilator simulator)--just ...
https://opencores.org/websvn//websvn/revision?repname=wbddr3&path=%2Fwbddr3%2Ftrunk%2F&rev=8
<div><strong>Rev 8 - dgisselq</strong> (5 file(s) modified)</div><div>Singular reads and writes now work (in the Verilator simulator)--just ...</div>~ /wbddr3/trunk/bench/cpp/ddrsdramsim.cpp<br />~ /wbddr3/trunk/bench/cpp/ddrsdram_tb.cpp<br />~ /wbddr3/trunk/doc/spec.pdf<br />~ /wbddr3/trunk/doc/src/spec.tex<br />~ /wbddr3/trunk/rtl/wbddrsdram.v<br />dgisselqMon, 01 Aug 2016 10:50:35 +0100https://opencores.org/websvn//websvn/revision?repname=wbddr3&path=%2Fwbddr3%2Ftrunk%2F&rev=8Make lots of progress. Reset works, and refresh is ...
https://opencores.org/websvn//websvn/revision?repname=wbddr3&path=%2Fwbddr3%2Ftrunk%2F&rev=7
<div><strong>Rev 7 - dgisselq</strong> (3 file(s) modified)</div><div>Make lots of progress. Reset works, and refresh is ...</div>~ /wbddr3/trunk/bench/cpp/ddrsdramsim.cpp<br />~ /wbddr3/trunk/bench/cpp/ddrsdram_tb.cpp<br />~ /wbddr3/trunk/rtl/wbddrsdram.v<br />dgisselqSun, 31 Jul 2016 01:29:59 +0100https://opencores.org/websvn//websvn/revision?repname=wbddr3&path=%2Fwbddr3%2Ftrunk%2F&rev=7Lots of bug fixes. The controller now proceeds through ...
https://opencores.org/websvn//websvn/revision?repname=wbddr3&path=%2Fwbddr3%2Ftrunk%2F&rev=6
<div><strong>Rev 6 - dgisselq</strong> (4 file(s) modified)</div><div>Lots of bug fixes. The controller now proceeds through ...</div>~ /wbddr3/trunk/bench/cpp/ddrsdramsim.cpp<br />~ /wbddr3/trunk/bench/cpp/ddrsdramsim.h<br />~ /wbddr3/trunk/bench/cpp/ddrsdram_tb.cpp<br />~ /wbddr3/trunk/rtl/wbddrsdram.v<br />dgisselqSat, 30 Jul 2016 01:49:36 +0100https://opencores.org/websvn//websvn/revision?repname=wbddr3&path=%2Fwbddr3%2Ftrunk%2F&rev=6Under Verilator/simulation testing, the core now properly brings the device
up ...
https://opencores.org/websvn//websvn/revision?repname=wbddr3&path=%2Fwbddr3%2Ftrunk%2F&rev=5
<div><strong>Rev 5 - dgisselq</strong> (2 file(s) modified)</div><div>Under Verilator/simulation testing, the core now properly brings the device<br />
up ...</div>~ /wbddr3/trunk/bench/cpp/ddrsdramsim.cpp<br />~ /wbddr3/trunk/rtl/wbddrsdram.v<br />dgisselqFri, 29 Jul 2016 19:16:30 +0100https://opencores.org/websvn//websvn/revision?repname=wbddr3&path=%2Fwbddr3%2Ftrunk%2F&rev=5Work continues. A preliminary test-bench has been created. ...
https://opencores.org/websvn//websvn/revision?repname=wbddr3&path=%2Fwbddr3%2Ftrunk%2F&rev=4
<div><strong>Rev 4 - dgisselq</strong> (5 file(s) modified)</div><div>Work continues. A preliminary test-bench has been created. ...</div>+ /wbddr3/trunk/bench/cpp/ddrsdramsim.cpp<br />+ /wbddr3/trunk/bench/cpp/ddrsdramsim.h<br />+ /wbddr3/trunk/bench/cpp/ddrsdram_tb.cpp<br />+ /wbddr3/trunk/bench/cpp/Makefile<br />~ /wbddr3/trunk/rtl/wbddrsdram.v<br />dgisselqFri, 29 Jul 2016 03:35:54 +0100https://opencores.org/websvn//websvn/revision?repname=wbddr3&path=%2Fwbddr3%2Ftrunk%2F&rev=4Fixes some, not all, of the Verilator build/lint errors.
https://opencores.org/websvn//websvn/revision?repname=wbddr3&path=%2Fwbddr3%2Ftrunk%2F&rev=3
<div><strong>Rev 3 - dgisselq</strong> (1 file(s) modified)</div><div>Fixes some, not all, of the Verilator build/lint errors.</div>~ /wbddr3/trunk/rtl/wbddrsdram.v<br />dgisselqThu, 28 Jul 2016 11:53:34 +0100https://opencores.org/websvn//websvn/revision?repname=wbddr3&path=%2Fwbddr3%2Ftrunk%2F&rev=3Initial checkin. Pieces are not working yet, but the ...
https://opencores.org/websvn//websvn/revision?repname=wbddr3&path=%2Fwbddr3%2Ftrunk%2F&rev=2
<div><strong>Rev 2 - dgisselq</strong> (15 file(s) modified)</div><div>Initial checkin. Pieces are not working yet, but the ...</div>+ /wbddr3/trunk/bench<br />+ /wbddr3/trunk/bench/cpp<br />+ /wbddr3/trunk/doc<br />+ /wbddr3/trunk/doc/gpl-3.0.pdf<br />+ /wbddr3/trunk/doc/Makefile<br />+ /wbddr3/trunk/doc/spec.pdf<br />+ /wbddr3/trunk/doc/src<br />+ /wbddr3/trunk/doc/src/gpl-3.0.tex<br />+ /wbddr3/trunk/doc/src/gqtekspec.cls<br />+ /wbddr3/trunk/doc/src/GT.eps<br />+ /wbddr3/trunk/doc/src/spec.tex<br />+ /wbddr3/trunk/Makefile<br />+ /wbddr3/trunk/rtl<br />+ /wbddr3/trunk/rtl/Makefile<br />+ /wbddr3/trunk/rtl/wbddrsdram.v<br />dgisselqThu, 28 Jul 2016 10:32:09 +0100https://opencores.org/websvn//websvn/revision?repname=wbddr3&path=%2Fwbddr3%2Ftrunk%2F&rev=2
