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xucpu
WebSVN RSS feed - xucpu
https://opencores.org/websvn//websvn/listing?repname=xucpu&path=%2Fxucpu%2Ftrunk%2Fsrc%2Fcomponents%2F&
Wed, 10 Jun 2026 20:54:13 +0100
FeedCreator 1.7.2
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Merge remote-tracking branch 'origin.xucpu/master' into svn
https://opencores.org/websvn//websvn/revision?repname=xucpu&path=%2Fxucpu%2Ftrunk%2Fsrc%2Fcomponents%2F&rev=41
<div><strong>Rev 41 - lcdsgmtr</strong> (139 file(s) modified)</div><div>Merge remote-tracking branch 'origin.xucpu/master' into svn</div>+ /xucpu/trunk/dev<br />+ /xucpu/trunk/dev/bus<br />+ /xucpu/trunk/dev/bus/adresses.txt<br />+ /xucpu/trunk/dev/bus/contents.txt<br />+ /xucpu/trunk/dev/bus/main.vhdl<br />- /xucpu/trunk/ghdl/1k.mk<br />- /xucpu/trunk/ghdl/2k.mk<br />- /xucpu/trunk/ghdl/4k.mk<br />- /xucpu/trunk/ghdl/8k.mk<br />- /xucpu/trunk/ghdl/16k.mk<br />- /xucpu/trunk/ghdl/asm/boot1.asm<br />- /xucpu/trunk/ghdl/input_data.txt<br />- /xucpu/trunk/ghdl/Makefile<br />- /xucpu/trunk/ghdl/S2.make<br />- /xucpu/trunk/ghdl/startup_sim.gtkw<br />- /xucpu/trunk/ghdl/win.make<br />~ /xucpu/trunk/src/components/BRAM/ram_parts.vhdl<br />~ /xucpu/trunk/ss/arch/board.vhdl<br />+ /xucpu/trunk/target<br />+ /xucpu/trunk/target/ghdl<br />+ /xucpu/trunk/target/ghdl/1k.mk<br />+ /xucpu/trunk/target/ghdl/2k.mk<br />+ /xucpu/trunk/target/ghdl/4k.mk<br />+ /xucpu/trunk/target/ghdl/8k.mk<br />+ /xucpu/trunk/target/ghdl/16k.mk<br />+ /xucpu/trunk/target/ghdl/asm<br />+ /xucpu/trunk/target/ghdl/asm/boot1.asm<br />+ /xucpu/trunk/target/ghdl/input_data.txt<br />+ /xucpu/trunk/target/ghdl/Makefile<br />+ /xucpu/trunk/target/ghdl/S2.make<br />+ /xucpu/trunk/target/ghdl/startup_sim.gtkw<br />+ /xucpu/trunk/target/ghdl/win.make<br />+ /xucpu/trunk/target/Xilinx<br />+ /xucpu/trunk/target/Xilinx/1k<br />+ /xucpu/trunk/target/Xilinx/1k/functional.wcfg<br />+ /xucpu/trunk/target/Xilinx/1k/input_data.txt<br />+ /xucpu/trunk/target/Xilinx/1k/iseconfig<br />+ /xucpu/trunk/target/Xilinx/1k/iseconfig/system.xreport<br />+ /xucpu/trunk/target/Xilinx/1k/iseconfig/xucpu.projectmgr<br />+ /xucpu/trunk/target/Xilinx/1k/post_route.wcfg<br />+ /xucpu/trunk/target/Xilinx/1k/simulation.wcfg<br />+ /xucpu/trunk/target/Xilinx/1k/startup_sim.wcfg<br />+ /xucpu/trunk/target/Xilinx/1k/startup_sim_pr.wcfg<br />+ /xucpu/trunk/target/Xilinx/1k/system.ucf<br />+ /xucpu/trunk/target/Xilinx/1k/system.xdl<br />+ /xucpu/trunk/target/Xilinx/1k/system_guide.ncd<br />+ /xucpu/trunk/target/Xilinx/1k/xucpu.gise<br />+ /xucpu/trunk/target/Xilinx/1k/xucpu.xise<br />+ /xucpu/trunk/target/Xilinx/2k<br />+ /xucpu/trunk/target/Xilinx/2k/system_2k<br />+ /xucpu/trunk/target/Xilinx/2k/system_2k/iseconfig<br />+ /xucpu/trunk/target/Xilinx/2k/system_2k/iseconfig/system.xreport<br />+ /xucpu/trunk/target/Xilinx/2k/system_2k/iseconfig/system_2k.projectmgr<br />+ /xucpu/trunk/target/Xilinx/2k/system_2k/system.ucf<br />+ /xucpu/trunk/target/Xilinx/2k/system_2k/system.xdl<br />+ /xucpu/trunk/target/Xilinx/2k/system_2k/system_2k.gise<br />+ /xucpu/trunk/target/Xilinx/2k/system_2k/system_2k.xise<br />+ /xucpu/trunk/target/Xilinx/4k<br />+ /xucpu/trunk/target/Xilinx/4k/system_4k<br />+ /xucpu/trunk/target/Xilinx/4k/system_4k/iseconfig<br />+ /xucpu/trunk/target/Xilinx/4k/system_4k/iseconfig/system.xreport<br />+ /xucpu/trunk/target/Xilinx/4k/system_4k/iseconfig/system_4k.projectmgr<br />+ /xucpu/trunk/target/Xilinx/4k/system_4k/system.ucf<br />+ /xucpu/trunk/target/Xilinx/4k/system_4k/system_4k.gise<br />+ /xucpu/trunk/target/Xilinx/4k/system_4k/system_4k.xise<br />+ /xucpu/trunk/target/Xilinx/8k<br />+ /xucpu/trunk/target/Xilinx/8k/system_8k<br />+ /xucpu/trunk/target/Xilinx/8k/system_8k/iseconfig<br />+ /xucpu/trunk/target/Xilinx/8k/system_8k/iseconfig/system.xreport<br />+ /xucpu/trunk/target/Xilinx/8k/system_8k/iseconfig/system_8k.projectmgr<br />+ /xucpu/trunk/target/Xilinx/8k/system_8k/system.ucf<br />+ /xucpu/trunk/target/Xilinx/8k/system_8k/system_8k.gise<br />+ /xucpu/trunk/target/Xilinx/8k/system_8k/system_8k.xise<br />+ /xucpu/trunk/target/Xilinx/16k<br />+ /xucpu/trunk/target/Xilinx/16k/system_16k<br />+ /xucpu/trunk/target/Xilinx/16k/system_16k/iseconfig<br />+ /xucpu/trunk/target/Xilinx/16k/system_16k/iseconfig/system.xreport<br />+ /xucpu/trunk/target/Xilinx/16k/system_16k/system.ucf<br />+ /xucpu/trunk/target/Xilinx/16k/system_16k/system_16k.gise<br />+ /xucpu/trunk/target/Xilinx/16k/system_16k/system_16k.xise<br />+ /xucpu/trunk/target/Xilinx/32k<br />+ /xucpu/trunk/target/Xilinx/32k/iseconfig<br />+ /xucpu/trunk/target/Xilinx/32k/iseconfig/mem_32k_xucpu.projectmgr<br />+ /xucpu/trunk/target/Xilinx/32k/iseconfig/system.xreport<br />+ /xucpu/trunk/target/Xilinx/32k/mem_32k_xucpu.gise<br />+ /xucpu/trunk/target/Xilinx/32k/mem_32k_xucpu.xise<br />+ /xucpu/trunk/target/Xilinx/32k/planAhead_run_1<br />+ /xucpu/trunk/target/Xilinx/32k/planAhead_run_1/mem_32k_xucpu.data<br />+ /xucpu/trunk/target/Xilinx/32k/planAhead_run_1/mem_32k_xucpu.data/cache<br />+ /xucpu/trunk/target/Xilinx/32k/planAhead_run_1/mem_32k_xucpu.data/cache/system_ngc_c521e236.edif<br />+ /xucpu/trunk/target/Xilinx/32k/planAhead_run_1/mem_32k_xucpu.data/runs<br />+ /xucpu/trunk/target/Xilinx/32k/planAhead_run_1/mem_32k_xucpu.data/runs/impl_1.psg<br />+ /xucpu/trunk/target/Xilinx/32k/planAhead_run_1/mem_32k_xucpu.ppr<br />+ /xucpu/trunk/target/Xilinx/32k/planAhead_run_1/planAhead.jou<br />+ /xucpu/trunk/target/Xilinx/32k/system.ucf<br />+ /xucpu/trunk/target/Xilinx/32k/system.xdl<br />- /xucpu/trunk/Xilinx/1k/functional.wcfg<br />- /xucpu/trunk/Xilinx/1k/input_data.txt<br />- /xucpu/trunk/Xilinx/1k/iseconfig/system.xreport<br />- /xucpu/trunk/Xilinx/1k/iseconfig/xucpu.projectmgr<br />- /xucpu/trunk/Xilinx/1k/post_route.wcfg<br />- /xucpu/trunk/Xilinx/1k/simulation.wcfg<br />- /xucpu/trunk/Xilinx/1k/startup_sim.wcfg<br />- /xucpu/trunk/Xilinx/1k/startup_sim_pr.wcfg<br />- /xucpu/trunk/Xilinx/1k/system.ucf<br />- /xucpu/trunk/Xilinx/1k/system.xdl<br />- /xucpu/trunk/Xilinx/1k/system_guide.ncd<br />- /xucpu/trunk/Xilinx/1k/xucpu.gise<br />- /xucpu/trunk/Xilinx/1k/xucpu.xise<br />- /xucpu/trunk/Xilinx/2k/system_2k/iseconfig/system.xreport<br />- /xucpu/trunk/Xilinx/2k/system_2k/iseconfig/system_2k.projectmgr<br />- /xucpu/trunk/Xilinx/2k/system_2k/system.ucf<br />- /xucpu/trunk/Xilinx/2k/system_2k/system.xdl<br />- /xucpu/trunk/Xilinx/2k/system_2k/system_2k.gise<br />- /xucpu/trunk/Xilinx/2k/system_2k/system_2k.xise<br />- /xucpu/trunk/Xilinx/4k/system_4k/iseconfig/system.xreport<br />- /xucpu/trunk/Xilinx/4k/system_4k/iseconfig/system_4k.projectmgr<br />- /xucpu/trunk/Xilinx/4k/system_4k/system.ucf<br />- /xucpu/trunk/Xilinx/4k/system_4k/system_4k.gise<br />- /xucpu/trunk/Xilinx/4k/system_4k/system_4k.xise<br />- /xucpu/trunk/Xilinx/8k/system_8k/iseconfig/system.xreport<br />- /xucpu/trunk/Xilinx/8k/system_8k/iseconfig/system_8k.projectmgr<br />- /xucpu/trunk/Xilinx/8k/system_8k/system.ucf<br />- /xucpu/trunk/Xilinx/8k/system_8k/system_8k.gise<br />- /xucpu/trunk/Xilinx/8k/system_8k/system_8k.xise<br />- /xucpu/trunk/Xilinx/16k/system_16k/iseconfig/system.xreport<br />- /xucpu/trunk/Xilinx/16k/system_16k/system.ucf<br />- /xucpu/trunk/Xilinx/16k/system_16k/system_16k.gise<br />- /xucpu/trunk/Xilinx/16k/system_16k/system_16k.xise<br />- /xucpu/trunk/Xilinx/32k/iseconfig/mem_32k_xucpu.projectmgr<br />- /xucpu/trunk/Xilinx/32k/iseconfig/system.xreport<br />- /xucpu/trunk/Xilinx/32k/mem_32k_xucpu.gise<br />- /xucpu/trunk/Xilinx/32k/mem_32k_xucpu.xise<br />- /xucpu/trunk/Xilinx/32k/planAhead_run_1/mem_32k_xucpu.data/cache/system_ngc_c521e236.edif<br />- /xucpu/trunk/Xilinx/32k/planAhead_run_1/mem_32k_xucpu.data/runs/impl_1.psg<br />- /xucpu/trunk/Xilinx/32k/planAhead_run_1/mem_32k_xucpu.ppr<br />- /xucpu/trunk/Xilinx/32k/planAhead_run_1/planAhead.jou<br />- /xucpu/trunk/Xilinx/32k/system.ucf<br />- /xucpu/trunk/Xilinx/32k/system.xdl<br />
lcdsgmtr
Sun, 22 Jan 2017 18:33:37 +0100
https://opencores.org/websvn//websvn/revision?repname=xucpu&path=%2Fxucpu%2Ftrunk%2Fsrc%2Fcomponents%2F&rev=41
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First implementation of cache memory.
https://opencores.org/websvn//websvn/revision?repname=xucpu&path=%2Fxucpu%2Ftrunk%2Fsrc%2Fcomponents%2F&rev=30
<div><strong>Rev 30 - lcdsgmtr</strong> (3 file(s) modified)</div><div>First implementation of cache memory.</div>~ /xucpu/trunk<br />+ /xucpu/trunk/src/components/BRAM/cache.vhdl<br />+ /xucpu/trunk/src/components/BRAM/cache_block.vhdl<br />
lcdsgmtr
Thu, 10 Mar 2016 16:59:22 +0100
https://opencores.org/websvn//websvn/revision?repname=xucpu&path=%2Fxucpu%2Ftrunk%2Fsrc%2Fcomponents%2F&rev=30
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Added project files for different systems.
https://opencores.org/websvn//websvn/revision?repname=xucpu&path=%2Fxucpu%2Ftrunk%2Fsrc%2Fcomponents%2F&rev=28
<div><strong>Rev 28 - lcdsgmtr</strong> (34 file(s) modified)</div><div>Added project files for different systems.</div>~ /xucpu/trunk<br />~ /xucpu/trunk/src/components/BRAM/ram_parts.vhdl<br />~ /xucpu/trunk/src/components/components.vhdl<br />+ /xucpu/trunk/src/system/system_mem_32k.vhdl<br />~ /xucpu/trunk/Xilinx/1k/iseconfig/system.xreport<br />+ /xucpu/trunk/Xilinx/1k/iseconfig/xucpu.projectmgr<br />~ /xucpu/trunk/Xilinx/1k/xucpu.gise<br />+ /xucpu/trunk/Xilinx/2k/system_2k<br />+ /xucpu/trunk/Xilinx/2k/system_2k/system_2k.xise<br />+ /xucpu/trunk/Xilinx/4k/system_4k<br />+ /xucpu/trunk/Xilinx/4k/system_4k/system_4k.xise<br />+ /xucpu/trunk/Xilinx/8k/system_8k<br />+ /xucpu/trunk/Xilinx/8k/system_8k/system_8k.xise<br />+ /xucpu/trunk/Xilinx/16k/system_16k<br />+ /xucpu/trunk/Xilinx/16k/system_16k/system_16k.xise<br />+ /xucpu/trunk/Xilinx/32k<br />+ /xucpu/trunk/Xilinx/32k/iseconfig<br />+ /xucpu/trunk/Xilinx/32k/iseconfig/mem_32k_xucpu.projectmgr<br />+ /xucpu/trunk/Xilinx/32k/iseconfig/system.xreport<br />+ /xucpu/trunk/Xilinx/32k/mem_32k_xucpu.gise<br />+ /xucpu/trunk/Xilinx/32k/mem_32k_xucpu.xise<br />+ /xucpu/trunk/Xilinx/32k/planAhead_run_1<br />+ /xucpu/trunk/Xilinx/32k/planAhead_run_1/mem_32k_xucpu.data<br />+ /xucpu/trunk/Xilinx/32k/planAhead_run_1/mem_32k_xucpu.data/cache<br />+ /xucpu/trunk/Xilinx/32k/planAhead_run_1/mem_32k_xucpu.data/cache/system_ngc_c521e236.edif<br />+ /xucpu/trunk/Xilinx/32k/planAhead_run_1/mem_32k_xucpu.data/constrs_1<br />+ /xucpu/trunk/Xilinx/32k/planAhead_run_1/mem_32k_xucpu.data/runs<br />+ /xucpu/trunk/Xilinx/32k/planAhead_run_1/mem_32k_xucpu.data/runs/impl_1.psg<br />+ /xucpu/trunk/Xilinx/32k/planAhead_run_1/mem_32k_xucpu.data/sources_1<br />+ /xucpu/trunk/Xilinx/32k/planAhead_run_1/mem_32k_xucpu.data/wt<br />+ /xucpu/trunk/Xilinx/32k/planAhead_run_1/mem_32k_xucpu.ppr<br />+ /xucpu/trunk/Xilinx/32k/planAhead_run_1/planAhead.jou<br />+ /xucpu/trunk/Xilinx/32k/system.ucf<br />+ /xucpu/trunk/Xilinx/32k/system.xdl<br />
lcdsgmtr
Sat, 10 Oct 2015 15:46:45 +0100
https://opencores.org/websvn//websvn/revision?repname=xucpu&path=%2Fxucpu%2Ftrunk%2Fsrc%2Fcomponents%2F&rev=28
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Added test data for 32k memory.
Added GTKW configuration file.
https://opencores.org/websvn//websvn/revision?repname=xucpu&path=%2Fxucpu%2Ftrunk%2Fsrc%2Fcomponents%2F&rev=26
<div><strong>Rev 26 - lcdsgmtr</strong> (9 file(s) modified)</div><div>Added test data for 32k memory.<br />
Added GTKW configuration file.</div>~ /xucpu/trunk<br />+ /xucpu/trunk/src/components/BRAM/2.txt<br />+ /xucpu/trunk/src/components/BRAM/3.txt<br />+ /xucpu/trunk/src/components/BRAM/4.txt<br />+ /xucpu/trunk/src/components/BRAM/5.txt<br />+ /xucpu/trunk/src/components/BRAM/tb_generic_ram.gtkw<br />~ /xucpu/trunk/src/components/BRAM/tb_generic_ram.vhdl<br />~ /xucpu/trunk/src/components/BRAM/test_data.txt<br />+ /xucpu/trunk/src/components/BRAM/test_data.txt.old<br />
lcdsgmtr
Thu, 08 Oct 2015 17:13:20 +0100
https://opencores.org/websvn//websvn/revision?repname=xucpu&path=%2Fxucpu%2Ftrunk%2Fsrc%2Fcomponents%2F&rev=26
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Problem with memory: created conditional generate based upon data width
instead ...
https://opencores.org/websvn//websvn/revision?repname=xucpu&path=%2Fxucpu%2Ftrunk%2Fsrc%2Fcomponents%2F&rev=25
<div><strong>Rev 25 - lcdsgmtr</strong> (5 file(s) modified)</div><div>Problem with memory: created conditional generate based upon data width<br />
instead ...</div>~ /xucpu/trunk<br />~ /xucpu/trunk/src/components/BRAM/RAM.vhdl<br />~ /xucpu/trunk/src/components/BRAM/ram_parts.vhdl<br />~ /xucpu/trunk/src/components/BRAM/tb_generic_ram.vhdl<br />~ /xucpu/trunk/src/util/file/hexio.vhdl<br />
lcdsgmtr
Thu, 08 Oct 2015 17:13:08 +0100
https://opencores.org/websvn//websvn/revision?repname=xucpu&path=%2Fxucpu%2Ftrunk%2Fsrc%2Fcomponents%2F&rev=25
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Currently moved test bench to 10 bit address.
Created spreadsheet for ...
https://opencores.org/websvn//websvn/revision?repname=xucpu&path=%2Fxucpu%2Ftrunk%2Fsrc%2Fcomponents%2F&rev=23
<div><strong>Rev 23 - lcdsgmtr</strong> (6 file(s) modified)</div><div>Currently moved test bench to 10 bit address.<br />
Created spreadsheet for ...</div>~ /xucpu/trunk<br />~ /xucpu/trunk/.bzrignore<br />+ /xucpu/trunk/src/components/BRAM/HEX fill sheet.ods<br />~ /xucpu/trunk/src/components/BRAM/Makefile<br />~ /xucpu/trunk/src/components/BRAM/tb_generic_ram.vhdl<br />+ /xucpu/trunk/src/components/BRAM/test_data.txt<br />
lcdsgmtr
Thu, 08 Oct 2015 17:13:02 +0100
https://opencores.org/websvn//websvn/revision?repname=xucpu&path=%2Fxucpu%2Ftrunk%2Fsrc%2Fcomponents%2F&rev=23
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Update on makefile, because some parts are in other files.
https://opencores.org/websvn//websvn/revision?repname=xucpu&path=%2Fxucpu%2Ftrunk%2Fsrc%2Fcomponents%2F&rev=22
<div><strong>Rev 22 - lcdsgmtr</strong> (3 file(s) modified)</div><div>Update on makefile, because some parts are in other files.</div>~ /xucpu/trunk<br />~ /xucpu/trunk/src/components/BRAM/Makefile<br />~ /xucpu/trunk/src/components/BRAM/ram_parts.vhdl<br />
lcdsgmtr
Thu, 08 Oct 2015 17:12:58 +0100
https://opencores.org/websvn//websvn/revision?repname=xucpu&path=%2Fxucpu%2Ftrunk%2Fsrc%2Fcomponents%2F&rev=22
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Since all BRAM is unified in one component, this testbench ...
https://opencores.org/websvn//websvn/revision?repname=xucpu&path=%2Fxucpu%2Ftrunk%2Fsrc%2Fcomponents%2F&rev=21
<div><strong>Rev 21 - lcdsgmtr</strong> (2 file(s) modified)</div><div>Since all BRAM is unified in one component, this testbench ...</div>~ /xucpu/trunk<br />- /xucpu/trunk/src/components/BRAM/tb_large_ram.vhdl<br />
lcdsgmtr
Thu, 08 Oct 2015 17:12:56 +0100
https://opencores.org/websvn//websvn/revision?repname=xucpu&path=%2Fxucpu%2Ftrunk%2Fsrc%2Fcomponents%2F&rev=21
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Update RAM package to allow for 15-bit address.
Update test bench ...
https://opencores.org/websvn//websvn/revision?repname=xucpu&path=%2Fxucpu%2Ftrunk%2Fsrc%2Fcomponents%2F&rev=20
<div><strong>Rev 20 - lcdsgmtr</strong> (3 file(s) modified)</div><div>Update RAM package to allow for 15-bit address.<br />
Update test bench ...</div>~ /xucpu/trunk<br />~ /xucpu/trunk/src/components/BRAM/RAM.vhdl<br />~ /xucpu/trunk/src/components/BRAM/tb_generic_ram.vhdl<br />
lcdsgmtr
Thu, 08 Oct 2015 17:12:54 +0100
https://opencores.org/websvn//websvn/revision?repname=xucpu&path=%2Fxucpu%2Ftrunk%2Fsrc%2Fcomponents%2F&rev=20
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Makefile for building memory block testbench.
https://opencores.org/websvn//websvn/revision?repname=xucpu&path=%2Fxucpu%2Ftrunk%2Fsrc%2Fcomponents%2F&rev=19
<div><strong>Rev 19 - lcdsgmtr</strong> (3 file(s) modified)</div><div>Makefile for building memory block testbench.</div>~ /xucpu/trunk<br />~ /xucpu/trunk/.bzrignore<br />+ /xucpu/trunk/src/components/BRAM/Makefile<br />
lcdsgmtr
Thu, 08 Oct 2015 17:12:51 +0100
https://opencores.org/websvn//websvn/revision?repname=xucpu&path=%2Fxucpu%2Ftrunk%2Fsrc%2Fcomponents%2F&rev=19
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Moving the generic block ram component piece by piece to ...
https://opencores.org/websvn//websvn/revision?repname=xucpu&path=%2Fxucpu%2Ftrunk%2Fsrc%2Fcomponents%2F&rev=17
<div><strong>Rev 17 - lcdsgmtr</strong> (5 file(s) modified)</div><div>Moving the generic block ram component piece by piece to ...</div>~ /xucpu/trunk<br />~ /xucpu/trunk/src/components/BRAM/RAM.vhdl<br />~ /xucpu/trunk/src/components/BRAM/ram_parts.vhdl<br />~ /xucpu/trunk/src/components/BRAM/tb_generic_ram.vhdl<br />~ /xucpu/trunk/src/util/file/hexio.vhdl<br />
lcdsgmtr
Thu, 08 Oct 2015 17:12:46 +0100
https://opencores.org/websvn//websvn/revision?repname=xucpu&path=%2Fxucpu%2Ftrunk%2Fsrc%2Fcomponents%2F&rev=17
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Re-write of memory in function of initial array memory blocks.
https://opencores.org/websvn//websvn/revision?repname=xucpu&path=%2Fxucpu%2Ftrunk%2Fsrc%2Fcomponents%2F&rev=16
<div><strong>Rev 16 - lcdsgmtr</strong> (10 file(s) modified)</div><div>Re-write of memory in function of initial array memory blocks.</div>~ /xucpu/trunk<br />~ /xucpu/trunk/ghdl/2k.mk<br />+ /xucpu/trunk/src/components/BRAM/generic_memory_block.vhdl<br />+ /xucpu/trunk/src/components/BRAM/generic_ram.vhdl<br />~ /xucpu/trunk/src/components/BRAM/ram_parts.vhdl<br />+ /xucpu/trunk/src/system/system_2k.vhdl<br />- /xucpu/trunk/src/util/file/arrayio.vhdl<br />+ /xucpu/trunk/src/util/file/hexio.vhdl<br />~ /xucpu/trunk/src/util/file/proc_reader.vhdl<br />~ /xucpu/trunk/src/util/file/sign_reader.vhdl<br />
lcdsgmtr
Thu, 08 Oct 2015 17:12:42 +0100
https://opencores.org/websvn//websvn/revision?repname=xucpu&path=%2Fxucpu%2Ftrunk%2Fsrc%2Fcomponents%2F&rev=16
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Unification of all RAM parts into one interface.
https://opencores.org/websvn//websvn/revision?repname=xucpu&path=%2Fxucpu%2Ftrunk%2Fsrc%2Fcomponents%2F&rev=15
<div><strong>Rev 15 - lcdsgmtr</strong> (3 file(s) modified)</div><div>Unification of all RAM parts into one interface.</div>~ /xucpu/trunk<br />~ /xucpu/trunk/src/components/BRAM/RAM.vhdl<br />+ /xucpu/trunk/src/components/BRAM/ram_parts.vhdl<br />
lcdsgmtr
Thu, 08 Oct 2015 17:12:35 +0100
https://opencores.org/websvn//websvn/revision?repname=xucpu&path=%2Fxucpu%2Ftrunk%2Fsrc%2Fcomponents%2F&rev=15
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This makes sure that this GHDL configuration analyses correctly.
https://opencores.org/websvn//websvn/revision?repname=xucpu&path=%2Fxucpu%2Ftrunk%2Fsrc%2Fcomponents%2F&rev=9
<div><strong>Rev 9 - lcdsgmtr</strong> (4 file(s) modified)</div><div>This makes sure that this GHDL configuration analyses correctly.</div>~ /xucpu/trunk<br />~ /xucpu/trunk/ghdl/Makefile<br />~ /xucpu/trunk/src/components/components.vhdl<br />~ /xucpu/trunk/src/components/data_reg.vhdl<br />
lcdsgmtr
Fri, 29 May 2015 16:45:22 +0100
https://opencores.org/websvn//websvn/revision?repname=xucpu&path=%2Fxucpu%2Ftrunk%2Fsrc%2Fcomponents%2F&rev=9
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Rebuilding the configuration to build the first system using GHDL.
https://opencores.org/websvn//websvn/revision?repname=xucpu&path=%2Fxucpu%2Ftrunk%2Fsrc%2Fcomponents%2F&rev=8
<div><strong>Rev 8 - lcdsgmtr</strong> (7 file(s) modified)</div><div>Rebuilding the configuration to build the first system using GHDL.</div>~ /xucpu/trunk<br />+ /xucpu/trunk/.bzrignore<br />~ /xucpu/trunk/ghdl/Makefile<br />+ /xucpu/trunk/src/components/ALU/logic.vhdl<br />+ /xucpu/trunk/src/components/ALU/shift.vhdl<br />+ /xucpu/trunk/src/components/ALU/summation.vhdl<br />+ /xucpu/trunk/src/system/system.vhdl<br />
lcdsgmtr
Thu, 28 May 2015 18:14:21 +0100
https://opencores.org/websvn//websvn/revision?repname=xucpu&path=%2Fxucpu%2Ftrunk%2Fsrc%2Fcomponents%2F&rev=8
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Removed some unnecessary files and directories.
Moved other files to new ...
https://opencores.org/websvn//websvn/revision?repname=xucpu&path=%2Fxucpu%2Ftrunk%2Fsrc%2Fcomponents%2F&rev=6
<div><strong>Rev 6 - lcdsgmtr</strong> (14 file(s) modified)</div><div>Removed some unnecessary files and directories.<br />
Moved other files to new ...</div>~ /xucpu/trunk<br />- /xucpu/trunk/FPGA<br />+ /xucpu/trunk/src/components/ALU/alu.vhdl<br />- /xucpu/trunk/src/components/ALU/ALU.vhdl<br />+ /xucpu/trunk/src/components/ALU/alu2.vhdl<br />+ /xucpu/trunk/src/system/clock.vhdl<br />+ /xucpu/trunk/src/system/controllers.vhdl<br />+ /xucpu/trunk/src/system/decoder.vhdl<br />+ /xucpu/trunk/src/system/Makefile<br />+ /xucpu/trunk/src/system/sync_reset.vhdl<br />+ /xucpu/trunk/src/system/uctrl-init.vhdl<br />+ /xucpu/trunk/src/system/uctrl-main.vhdl<br />+ /xucpu/trunk/src/system/uctrl.vhdl<br />+ /xucpu/trunk/VHDL/ALU.vhdl<br />
lcdsgmtr
Thu, 28 May 2015 18:14:13 +0100
https://opencores.org/websvn//websvn/revision?repname=xucpu&path=%2Fxucpu%2Ftrunk%2Fsrc%2Fcomponents%2F&rev=6
-
Re-organisation of repository.
https://opencores.org/websvn//websvn/revision?repname=xucpu&path=%2Fxucpu%2Ftrunk%2Fsrc%2Fcomponents%2F&rev=5
<div><strong>Rev 5 - lcdsgmtr</strong> (55 file(s) modified)</div><div>Re-organisation of repository.</div>~ /xucpu/trunk<br />- /xucpu/trunk/FPGA/components.vhdl<br />- /xucpu/trunk/FPGA/data_reg.vhdl<br />- /xucpu/trunk/FPGA/gpio_in.vhdl<br />- /xucpu/trunk/FPGA/gpio_out.vhdl<br />- /xucpu/trunk/FPGA/incr.vhdl<br />- /xucpu/trunk/FPGA/regf.vhdl<br />- /xucpu/trunk/FPGA/startup_sim.vhdl<br />- /xucpu/trunk/FPGA/system.vhdl<br />- /xucpu/trunk/FPGA/system_package.vhdl<br />- /xucpu/trunk/FPGA/system_sim.vhdl<br />- /xucpu/trunk/FPGA/tty_in.vhdl<br />- /xucpu/trunk/FPGA/tty_out.vhdl<br />- /xucpu/trunk/FPGA/uart_clk.vhdl<br />- /xucpu/trunk/FPGA/zerof.vhdl<br />+ /xucpu/trunk/ghdl/1k.mk<br />+ /xucpu/trunk/ghdl/2k.mk<br />+ /xucpu/trunk/ghdl/4k.mk<br />+ /xucpu/trunk/ghdl/8k.mk<br />+ /xucpu/trunk/ghdl/16k.mk<br />+ /xucpu/trunk/src<br />+ /xucpu/trunk/src/components<br />+ /xucpu/trunk/src/components/ALU<br />/xucpu/trunk/src/components/ALU/ALU.vhdl<br />+ /xucpu/trunk/src/components/BRAM<br />/xucpu/trunk/src/components/BRAM/RAM.vhdl<br />/xucpu/trunk/src/components/BRAM/ram16x16_poc.vhdl<br />/xucpu/trunk/src/components/BRAM/tb_generic_ram.vhdl<br />/xucpu/trunk/src/components/BRAM/tb_large_ram.vhdl<br />+ /xucpu/trunk/src/components/components.vhdl<br />+ /xucpu/trunk/src/components/data_reg.vhdl<br />+ /xucpu/trunk/src/components/incr.vhdl<br />+ /xucpu/trunk/src/components/multiplexer<br />/xucpu/trunk/src/components/multiplexer/MUX.vhdl<br />+ /xucpu/trunk/src/components/regf.vhdl<br />+ /xucpu/trunk/src/components/zerof.vhdl<br />+ /xucpu/trunk/src/io<br />+ /xucpu/trunk/src/io/gpio_in.vhdl<br />+ /xucpu/trunk/src/io/gpio_out.vhdl<br />+ /xucpu/trunk/src/io/tty_in.vhdl<br />+ /xucpu/trunk/src/io/tty_out.vhdl<br />+ /xucpu/trunk/src/io/uart_clk.vhdl<br />+ /xucpu/trunk/src/system<br />+ /xucpu/trunk/src/system/1k<br />+ /xucpu/trunk/src/system/1k/system.vhdl<br />+ /xucpu/trunk/src/system/2k<br />+ /xucpu/trunk/src/system/4k<br />+ /xucpu/trunk/src/system/8k<br />+ /xucpu/trunk/src/system/16k<br />+ /xucpu/trunk/tb<br />+ /xucpu/trunk/tb/startup_sim.vhdl<br />+ /xucpu/trunk/tb/system_sim.vhdl<br />- /xucpu/trunk/VHDL/ALU<br />- /xucpu/trunk/VHDL/blockram<br />- /xucpu/trunk/VHDL/multiplexer<br />
lcdsgmtr
Wed, 27 May 2015 17:02:57 +0100
https://opencores.org/websvn//websvn/revision?repname=xucpu&path=%2Fxucpu%2Ftrunk%2Fsrc%2Fcomponents%2F&rev=5
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