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                    <strong style="padding-right: 4px;">URL</strong>
                    https://opencores.org/ocsvn/csa/csa/trunk
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        <item>
            <title>add the macro DEBUG_OUTPUT for the general debug information output</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=csa&amp;path=%2F&amp;rev=52</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 52 - simon111&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;add the macro DEBUG_OUTPUT for the general debug information output&lt;/div&gt;~ /csa/trunk/sw_sim/misc.h&lt;br /&gt;</description>
            <author>simon111</author>
            <pubDate>Tue, 20 Apr 2010 03:13:19 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=csa&amp;path=%2F&amp;rev=52</guid>
        </item>
        <item>
            <title>remove the using to iverilog and veriwell</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=csa&amp;path=%2F&amp;rev=51</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 51 - simon111&lt;/strong&gt; (3 file(s) modified)&lt;/div&gt;&lt;div&gt;remove the using to iverilog and veriwell&lt;/div&gt;~ /csa/trunk/bench/makefile&lt;br /&gt;~ /csa/trunk/makefile&lt;br /&gt;~ /csa/trunk/rtl/makefile&lt;br /&gt;</description>
            <author>simon111</author>
            <pubDate>Tue, 05 May 2009 01:40:45 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=csa&amp;path=%2F&amp;rev=51</guid>
        </item>
        <item>
            <title>add some documents</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=csa&amp;path=%2F&amp;rev=50</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 50 - simon111&lt;/strong&gt; (3 file(s) modified)&lt;/div&gt;&lt;div&gt;add some documents&lt;/div&gt;~ /csa/trunk/doc/readme&lt;br /&gt;~ /csa/trunk/makefile&lt;br /&gt;+ /csa/trunk/README&lt;br /&gt;</description>
            <author>simon111</author>
            <pubDate>Mon, 04 May 2009 10:14:36 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=csa&amp;path=%2F&amp;rev=50</guid>
        </item>
        <item>
            <title>group_decrypt module simulate success</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=csa&amp;path=%2F&amp;rev=49</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 49 - simon111&lt;/strong&gt; (12 file(s) modified)&lt;/div&gt;&lt;div&gt;group_decrypt module simulate success&lt;/div&gt;+ /csa/trunk/bench/group_decrypt_tb.v&lt;br /&gt;~ /csa/trunk/bench/timescale.v&lt;br /&gt;+ /csa/trunk/modelsim6.2b/group_decrypt.do&lt;br /&gt;~ /csa/trunk/modelsim6.2b/stream_cypher.do&lt;br /&gt;~ /csa/trunk/rtl/decrypt.v&lt;br /&gt;~ /csa/trunk/rtl/group_decrypt.v&lt;br /&gt;~ /csa/trunk/rtl/key_schedule.v&lt;br /&gt;~ /csa/trunk/rtl/makefile&lt;br /&gt;~ /csa/trunk/rtl/stream_cypher.v&lt;br /&gt;~ /csa/trunk/sw_sim/csa.c&lt;br /&gt;+ /csa/trunk/sw_sim/group_decrypt.c&lt;br /&gt;~ /csa/trunk/sw_sim/makefile&lt;br /&gt;</description>
            <author>simon111</author>
            <pubDate>Tue, 28 Apr 2009 13:09:52 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=csa&amp;path=%2F&amp;rev=49</guid>
        </item>
        <item>
            <title>improve key_schedule module</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=csa&amp;path=%2F&amp;rev=48</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 48 - simon111&lt;/strong&gt; (5 file(s) modified)&lt;/div&gt;&lt;div&gt;improve key_schedule module&lt;/div&gt;~ /csa/trunk/bench/key_schedule_tb.v&lt;br /&gt;~ /csa/trunk/makefile&lt;br /&gt;~ /csa/trunk/rtl/key_cnt.v&lt;br /&gt;~ /csa/trunk/rtl/key_schedule.v&lt;br /&gt;~ /csa/trunk/sw_sim/key_schedule.c&lt;br /&gt;</description>
            <author>simon111</author>
            <pubDate>Thu, 23 Apr 2009 13:24:18 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=csa&amp;path=%2F&amp;rev=48</guid>
        </item>
        <item>
            <title>add bin prepare function</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=csa&amp;path=%2F&amp;rev=47</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 47 - simon111&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;add bin prepare function&lt;/div&gt;~ /csa/trunk/makefile&lt;br /&gt;</description>
            <author>simon111</author>
            <pubDate>Thu, 23 Apr 2009 10:12:14 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=csa&amp;path=%2F&amp;rev=47</guid>
        </item>
        <item>
            <title>delete key_comupter module and testbench</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=csa&amp;path=%2F&amp;rev=46</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 46 - simon111&lt;/strong&gt; (2 file(s) modified)&lt;/div&gt;&lt;div&gt;delete key_comupter module and testbench&lt;/div&gt;- /csa/trunk/bench/key_computer_tb.v&lt;br /&gt;- /csa/trunk/rtl/key_computer.v&lt;br /&gt;</description>
            <author>simon111</author>
            <pubDate>Thu, 23 Apr 2009 03:20:45 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=csa&amp;path=%2F&amp;rev=46</guid>
        </item>
        <item>
            <title>improve makefile</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=csa&amp;path=%2F&amp;rev=45</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 45 - simon111&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;improve makefile&lt;/div&gt;~ /csa/trunk/rtl/makefile&lt;br /&gt;</description>
            <author>simon111</author>
            <pubDate>Tue, 21 Apr 2009 08:48:21 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=csa&amp;path=%2F&amp;rev=45</guid>
        </item>
        <item>
            <title>improve some module , strip warnings</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=csa&amp;path=%2F&amp;rev=44</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 44 - simon111&lt;/strong&gt; (7 file(s) modified)&lt;/div&gt;&lt;div&gt;improve some module , strip warnings&lt;/div&gt;~ /csa/trunk/quartus10/csa.qsf&lt;br /&gt;~ /csa/trunk/quartus10/csa_fpga.v&lt;br /&gt;~ /csa/trunk/rtl/group_decrypt.v&lt;br /&gt;~ /csa/trunk/rtl/stream_8bytes.v&lt;br /&gt;~ /csa/trunk/rtl/stream_byte.v&lt;br /&gt;~ /csa/trunk/rtl/stream_cypher.v&lt;br /&gt;~ /csa/trunk/rtl/ts_sync.v&lt;br /&gt;</description>
            <author>simon111</author>
            <pubDate>Sun, 19 Apr 2009 13:30:11 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=csa&amp;path=%2F&amp;rev=44</guid>
        </item>
        <item>
            <title>improve group_decrypt module</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=csa&amp;path=%2F&amp;rev=43</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 43 - simon111&lt;/strong&gt; (2 file(s) modified)&lt;/div&gt;&lt;div&gt;improve group_decrypt module&lt;/div&gt;~ /csa/trunk/rtl/group_decrypt.v&lt;br /&gt;~ /csa/trunk/sw_sim/csa.c&lt;br /&gt;</description>
            <author>simon111</author>
            <pubDate>Sun, 19 Apr 2009 11:37:39 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=csa&amp;path=%2F&amp;rev=43</guid>
        </item>
        <item>
            <title>add group_decrypt module</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=csa&amp;path=%2F&amp;rev=42</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 42 - simon111&lt;/strong&gt; (5 file(s) modified)&lt;/div&gt;&lt;div&gt;add group_decrypt module&lt;/div&gt;~ /csa/trunk/bench/decrypt_tb.v&lt;br /&gt;~ /csa/trunk/rtl/decrypt.v&lt;br /&gt;+ /csa/trunk/rtl/group_decrypt.v&lt;br /&gt;~ /csa/trunk/rtl/ts_sync.v&lt;br /&gt;~ /csa/trunk/sw_sim/csa.c&lt;br /&gt;</description>
            <author>simon111</author>
            <pubDate>Sun, 19 Apr 2009 05:23:32 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=csa&amp;path=%2F&amp;rev=42</guid>
        </item>
        <item>
            <title>add three moudule   ts_serial_out ts_sync key_cnt</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=csa&amp;path=%2F&amp;rev=41</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 41 - simon111&lt;/strong&gt; (8 file(s) modified)&lt;/div&gt;&lt;div&gt;add three moudule   ts_serial_out ts_sync key_cnt&lt;/div&gt;~ /csa/trunk/bench/csa_pli.c&lt;br /&gt;~ /csa/trunk/bench/decrypt_tb.v&lt;br /&gt;~ /csa/trunk/rtl/decrypt.v&lt;br /&gt;+ /csa/trunk/rtl/key_cnt.v&lt;br /&gt;~ /csa/trunk/rtl/makefile&lt;br /&gt;+ /csa/trunk/rtl/ts_serial_out.v&lt;br /&gt;+ /csa/trunk/rtl/ts_sync.v&lt;br /&gt;~ /csa/trunk/sw_sim/csa.c&lt;br /&gt;</description>
            <author>simon111</author>
            <pubDate>Sat, 18 Apr 2009 16:26:11 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=csa&amp;path=%2F&amp;rev=41</guid>
        </item>
        <item>
            <title>add timescale.v file and fix a bug in key_schedule module</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=csa&amp;path=%2F&amp;rev=40</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 40 - simon111&lt;/strong&gt; (26 file(s) modified)&lt;/div&gt;&lt;div&gt;add timescale.v file and fix a bug in key_schedule module&lt;/div&gt;~ /csa/trunk/bench/csa_pli.c&lt;br /&gt;~ /csa/trunk/bench/decrypt_tb.v&lt;br /&gt;~ /csa/trunk/bench/makefile&lt;br /&gt;+ /csa/trunk/bench/timescale.v&lt;br /&gt;~ /csa/trunk/modelsim6.2b/csa.mpf&lt;br /&gt;~ /csa/trunk/rtl/block_decypher.v&lt;br /&gt;~ /csa/trunk/rtl/block_perm.v&lt;br /&gt;~ /csa/trunk/rtl/block_sbox.v&lt;br /&gt;~ /csa/trunk/rtl/decrypt.v&lt;br /&gt;~ /csa/trunk/rtl/key_computer.v&lt;br /&gt;~ /csa/trunk/rtl/key_perm.v&lt;br /&gt;~ /csa/trunk/rtl/key_schedule.v&lt;br /&gt;~ /csa/trunk/rtl/sbox1.v&lt;br /&gt;~ /csa/trunk/rtl/sbox2.v&lt;br /&gt;~ /csa/trunk/rtl/sbox3.v&lt;br /&gt;~ /csa/trunk/rtl/sbox4.v&lt;br /&gt;~ /csa/trunk/rtl/sbox5.v&lt;br /&gt;~ /csa/trunk/rtl/sbox6.v&lt;br /&gt;~ /csa/trunk/rtl/sbox7.v&lt;br /&gt;~ /csa/trunk/rtl/sboxes.v&lt;br /&gt;~ /csa/trunk/rtl/stream_8bytes.v&lt;br /&gt;~ /csa/trunk/rtl/stream_byte.v&lt;br /&gt;~ /csa/trunk/rtl/stream_cypher.v&lt;br /&gt;~ /csa/trunk/rtl/stream_iteration.v&lt;br /&gt;~ /csa/trunk/sw_sim/csa.c&lt;br /&gt;~ /csa/trunk/sw_sim/misc.h&lt;br /&gt;</description>
            <author>simon111</author>
            <pubDate>Sat, 18 Apr 2009 12:20:23 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=csa&amp;path=%2F&amp;rev=40</guid>
        </item>
        <item>
            <title>add usb controler module</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=csa&amp;path=%2F&amp;rev=39</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 39 - simon111&lt;/strong&gt; (4 file(s) modified)&lt;/div&gt;&lt;div&gt;add usb controler module&lt;/div&gt;~ /csa/trunk/pc/csa_test.c&lt;br /&gt;~ /csa/trunk/quartus10/csa.qsf&lt;br /&gt;~ /csa/trunk/quartus10/csa_fpga.v&lt;br /&gt;+ /csa/trunk/quartus10/usb_cnt.v&lt;br /&gt;</description>
            <author>simon111</author>
            <pubDate>Sat, 18 Apr 2009 08:51:52 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=csa&amp;path=%2F&amp;rev=39</guid>
        </item>
        <item>
            <title>improve the ledseg control module 
     ...</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=csa&amp;path=%2F&amp;rev=38</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 38 - simon111&lt;/strong&gt; (6 file(s) modified)&lt;/div&gt;&lt;div&gt;improve the ledseg control module &lt;br /&gt;
     ...&lt;/div&gt;~ /csa/trunk/pc/csa_test.c&lt;br /&gt;~ /csa/trunk/pc/imgdev.c&lt;br /&gt;~ /csa/trunk/pc/misc.h&lt;br /&gt;~ /csa/trunk/quartus10/csa_fpga.v&lt;br /&gt;~ /csa/trunk/quartus10/hex2seg.v&lt;br /&gt;~ /csa/trunk/quartus10/ledseg_cnt.v&lt;br /&gt;</description>
            <author>simon111</author>
            <pubDate>Fri, 17 Apr 2009 14:52:08 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=csa&amp;path=%2F&amp;rev=38</guid>
        </item>
        <item>
            <title>improve write_data systemcall,</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=csa&amp;path=%2F&amp;rev=37</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 37 - simon111&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;improve write_data systemcall,&lt;/div&gt;~ /csa/trunk/bench/csa_pli.c&lt;br /&gt;</description>
            <author>simon111</author>
            <pubDate>Fri, 17 Apr 2009 09:32:52 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=csa&amp;path=%2F&amp;rev=37</guid>
        </item>
        <item>
            <title>improve read_date vpi sytemcall, add offset and size argument</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=csa&amp;path=%2F&amp;rev=36</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 36 - simon111&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;improve read_date vpi sytemcall, add offset and size argument&lt;/div&gt;~ /csa/trunk/bench/csa_pli.c&lt;br /&gt;</description>
            <author>simon111</author>
            <pubDate>Fri, 17 Apr 2009 07:54:53 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=csa&amp;path=%2F&amp;rev=36</guid>
        </item>
        <item>
            <title>csa cli support binary test data</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=csa&amp;path=%2F&amp;rev=35</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 35 - simon111&lt;/strong&gt; (2 file(s) modified)&lt;/div&gt;&lt;div&gt;csa cli support binary test data&lt;/div&gt;~ /csa/trunk/bench/csa_pli.c&lt;br /&gt;~ /csa/trunk/bench/decrypt_tb.v&lt;br /&gt;</description>
            <author>simon111</author>
            <pubDate>Fri, 17 Apr 2009 03:46:57 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=csa&amp;path=%2F&amp;rev=35</guid>
        </item>
        <item>
            <title>add binary test date (only sw_sim now )</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=csa&amp;path=%2F&amp;rev=34</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 34 - simon111&lt;/strong&gt; (5 file(s) modified)&lt;/div&gt;&lt;div&gt;add binary test date (only sw_sim now )&lt;/div&gt;~ /csa/trunk/decrypted&lt;br /&gt;~ /csa/trunk/sw_sim/decrypt.c&lt;br /&gt;~ /csa/trunk/sw_sim/makefile&lt;br /&gt;~ /csa/trunk/sw_sim/misc.h&lt;br /&gt;+ /csa/trunk/test_dat/decrypt.in&lt;br /&gt;</description>
            <author>simon111</author>
            <pubDate>Fri, 17 Apr 2009 01:24:55 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=csa&amp;path=%2F&amp;rev=34</guid>
        </item>
        <item>
            <title>improve ledseg controler module</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=csa&amp;path=%2F&amp;rev=33</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 33 - simon111&lt;/strong&gt; (4 file(s) modified)&lt;/div&gt;&lt;div&gt;improve ledseg controler module&lt;/div&gt;~ /csa/trunk/quartus10/csa_fpga.v&lt;br /&gt;+ /csa/trunk/quartus10/hex2seg.v&lt;br /&gt;+ /csa/trunk/quartus10/ledseg_cnt.v&lt;br /&gt;+ /csa/trunk/quartus10/led_cnt.v&lt;br /&gt;</description>
            <author>simon111</author>
            <pubDate>Thu, 16 Apr 2009 13:46:53 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=csa&amp;path=%2F&amp;rev=33</guid>
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