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ethmac
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https://opencores.org/websvn//websvn/listing?repname=ethmac&path=&
Sun, 03 May 2026 22:28:26 +0100
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dbg_dat0 only exist when `DEBUG_WISHBONE is set
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2F&rev=368
<div><strong>Rev 368 - olof</strong> (1 file(s) modified)</div><div>dbg_dat0 only exist when `DEBUG_WISHBONE is set</div>~ /ethmac/trunk/rtl/verilog/eth_wishbone.v<br />
olof
Tue, 14 Feb 2012 18:48:05 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2F&rev=368
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Remove Wishbone B3 define. For classic wishbone, these ports can ...
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2F&rev=367
<div><strong>Rev 367 - olof</strong> (3 file(s) modified)</div><div>Remove Wishbone B3 define. For classic wishbone, these ports can ...</div>~ /ethmac/trunk/rtl/verilog/ethmac.v<br />~ /ethmac/trunk/rtl/verilog/ethmac_defines.v<br />~ /ethmac/trunk/rtl/verilog/eth_wishbone.v<br />
olof
Tue, 13 Dec 2011 21:33:02 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2F&rev=367
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Readded eth_top.v with a deprecation warning
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2F&rev=366
<div><strong>Rev 366 - olof</strong> (1 file(s) modified)</div><div>Readded eth_top.v with a deprecation warning</div>+ /ethmac/trunk/rtl/verilog/eth_top.v<br />
olof
Thu, 11 Aug 2011 17:36:52 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2F&rev=366
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Whitespace cleanup
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2F&rev=365
<div><strong>Rev 365 - olof</strong> (2 file(s) modified)</div><div>Whitespace cleanup</div>~ /ethmac/trunk/rtl/verilog/ethmac.v<br />~ /ethmac/trunk/rtl/verilog/eth_fifo.v<br />
olof
Wed, 10 Aug 2011 18:19:07 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2F&rev=365
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Renamed eth_top.v to ethmac.v to fit better into OpenCores structure
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2F&rev=364
<div><strong>Rev 364 - olof</strong> (12 file(s) modified)</div><div>Renamed eth_top.v to ethmac.v to fit better into OpenCores structure</div>~ /ethmac/trunk/bench/verilog/tb_ethernet.v<br />~ /ethmac/trunk/bench/verilog/tb_ethernet_with_cop.v<br />~ /ethmac/trunk/bench/verilog/tb_eth_top.v<br />+ /ethmac/trunk/rtl/verilog/ethmac.v<br />- /ethmac/trunk/rtl/verilog/eth_top.v<br />~ /ethmac/trunk/sim/rtl_sim/bin/rtl_file_list.lst<br />~ /ethmac/trunk/sim/rtl_sim/modelsim_sim/bin/ethernet.mpf<br />~ /ethmac/trunk/sim/rtl_sim/modelsim_sim/bin/eth_wave.do<br />~ /ethmac/trunk/sim/rtl_sim/modelsim_sim/run/tb_eth.do<br />~ /ethmac/trunk/sim/rtl_sim/ncsim_sim/bin/rtl_file_list.lst<br />~ /ethmac/trunk/sim/rtl_sim/ncsim_sim/run/top_groups.do<br />~ /ethmac/trunk/sim/rtl_sim/run/top_groups.do<br />
olof
Tue, 09 Aug 2011 20:49:44 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2F&rev=364
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quartus project files
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2F&rev=363
<div><strong>Rev 363 - unneback</strong> (6 file(s) modified)</div><div>quartus project files</div>~ /ethmac/branches/unneback/Makefile<br />~ /ethmac/branches/unneback/rtl/verilog/Makefile<br />+ /ethmac/branches/unneback/syn<br />+ /ethmac/branches/unneback/syn/altera<br />+ /ethmac/branches/unneback/syn/altera/ethmac.qpf<br />+ /ethmac/branches/unneback/syn/altera/ethmac.qsf<br />
unneback
Tue, 09 Aug 2011 12:14:34 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2F&rev=363
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added Makefiles to build project
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2F&rev=362
<div><strong>Rev 362 - unneback</strong> (2 file(s) modified)</div><div>added Makefiles to build project</div>+ /ethmac/branches/unneback/Makefile<br />+ /ethmac/branches/unneback/rtl/verilog/Makefile<br />
unneback
Tue, 09 Aug 2011 11:57:23 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2F&rev=362
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created branch unneback
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2F&rev=361
<div><strong>Rev 361 - unneback</strong> (1 file(s) modified)</div><div>created branch unneback</div>+ /ethmac/branches/unneback<br />
unneback
Tue, 09 Aug 2011 11:48:59 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2F&rev=361
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Added partial implementation of the debug register from ORPSoC
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2F&rev=360
<div><strong>Rev 360 - olof</strong> (4 file(s) modified)</div><div>Added partial implementation of the debug register from ORPSoC</div>~ /ethmac/trunk/rtl/verilog/ethmac_defines.v<br />~ /ethmac/trunk/rtl/verilog/eth_registers.v<br />~ /ethmac/trunk/rtl/verilog/eth_top.v<br />~ /ethmac/trunk/rtl/verilog/eth_wishbone.v<br />
olof
Mon, 08 Aug 2011 13:14:09 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2F&rev=360
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Verilator linting fixes
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2F&rev=359
<div><strong>Rev 359 - olof</strong> (1 file(s) modified)</div><div>Verilator linting fixes</div>~ /ethmac/trunk/rtl/verilog/eth_wishbone.v<br />
olof
Sat, 06 Aug 2011 11:01:31 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2F&rev=359
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Rename do to dato to avoid conflict with SystemVerilog (inherited ...
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2F&rev=358
<div><strong>Rev 358 - olof</strong> (2 file(s) modified)</div><div>Rename do to dato to avoid conflict with SystemVerilog (inherited ...</div>~ /ethmac/trunk/rtl/verilog/eth_spram_256x32.v<br />~ /ethmac/trunk/rtl/verilog/eth_wishbone.v<br />
olof
Thu, 04 Aug 2011 21:00:38 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2F&rev=358
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Bit width, assignment and white space fixes by Julius Baxter, ...
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2F&rev=357
<div><strong>Rev 357 - olof</strong> (3 file(s) modified)</div><div>Bit width, assignment and white space fixes by Julius Baxter, ...</div>~ /ethmac/trunk/rtl/verilog/eth_fifo.v<br />~ /ethmac/trunk/rtl/verilog/eth_registers.v<br />~ /ethmac/trunk/rtl/verilog/eth_spram_256x32.v<br />
olof
Thu, 04 Aug 2011 20:49:05 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2F&rev=357
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Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project ...
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2F&rev=356
<div><strong>Rev 356 - olof</strong> (14 file(s) modified)</div><div>Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project ...</div>~ /ethmac/trunk/bench/verilog/tb_ethernet.v<br />~ /ethmac/trunk/bench/verilog/tb_ethernet_with_cop.v<br />~ /ethmac/trunk/bench/verilog/tb_eth_top.v<br />+ /ethmac/trunk/rtl/verilog/ethmac_defines.v<br />- /ethmac/trunk/rtl/verilog/eth_defines.v<br />~ /ethmac/trunk/rtl/verilog/eth_fifo.v<br />~ /ethmac/trunk/rtl/verilog/eth_registers.v<br />~ /ethmac/trunk/rtl/verilog/eth_spram_256x32.v<br />~ /ethmac/trunk/rtl/verilog/eth_top.v<br />~ /ethmac/trunk/rtl/verilog/eth_wishbone.v<br />~ /ethmac/trunk/sim/rtl_sim/bin/rtl_file_list.lst<br />~ /ethmac/trunk/sim/rtl_sim/modelsim_sim/bin/ethernet.mpf<br />~ /ethmac/trunk/sim/rtl_sim/modelsim_sim/run/tb_eth.do<br />~ /ethmac/trunk/sim/rtl_sim/ncsim_sim/bin/rtl_file_list.lst<br />
olof
Thu, 04 Aug 2011 19:02:14 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2F&rev=356
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Import Julius Baxter's verilator hints from ORPSoC
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2F&rev=355
<div><strong>Rev 355 - olof</strong> (2 file(s) modified)</div><div>Import Julius Baxter's verilator hints from ORPSoC</div>~ /ethmac/trunk/rtl/verilog/eth_shiftreg.v<br />~ /ethmac/trunk/rtl/verilog/eth_wishbone.v<br />
olof
Thu, 04 Aug 2011 18:13:12 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2F&rev=355
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Whitespace cleanup
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2F&rev=354
<div><strong>Rev 354 - olof</strong> (10 file(s) modified)</div><div>Whitespace cleanup</div>~ /ethmac/trunk/rtl/verilog/eth_fifo.v<br />~ /ethmac/trunk/rtl/verilog/eth_miim.v<br />~ /ethmac/trunk/rtl/verilog/eth_receivecontrol.v<br />~ /ethmac/trunk/rtl/verilog/eth_registers.v<br />~ /ethmac/trunk/rtl/verilog/eth_rxaddrcheck.v<br />~ /ethmac/trunk/rtl/verilog/eth_rxcounters.v<br />~ /ethmac/trunk/rtl/verilog/eth_rxethmac.v<br />~ /ethmac/trunk/rtl/verilog/eth_rxstatem.v<br />~ /ethmac/trunk/rtl/verilog/eth_spram_256x32.v<br />~ /ethmac/trunk/rtl/verilog/eth_wishbone.v<br />
olof
Thu, 04 Aug 2011 17:51:00 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2F&rev=354
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Inherit fixes for bit width of constants from ORPSoC
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2F&rev=353
<div><strong>Rev 353 - olof</strong> (6 file(s) modified)</div><div>Inherit fixes for bit width of constants from ORPSoC</div>~ /ethmac/trunk/rtl/verilog/eth_clockgen.v<br />~ /ethmac/trunk/rtl/verilog/eth_receivecontrol.v<br />~ /ethmac/trunk/rtl/verilog/eth_rxcounters.v<br />~ /ethmac/trunk/rtl/verilog/eth_transmitcontrol.v<br />~ /ethmac/trunk/rtl/verilog/eth_txcounters.v<br />~ /ethmac/trunk/rtl/verilog/eth_txethmac.v<br />
olof
Tue, 02 Aug 2011 16:18:46 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2F&rev=353
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Removed delayed assignments from rtl code
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2F&rev=352
<div><strong>Rev 352 - olof</strong> (24 file(s) modified)</div><div>Removed delayed assignments from rtl code</div>~ /ethmac/trunk/rtl/verilog/eth_clockgen.v<br />~ /ethmac/trunk/rtl/verilog/eth_cop.v<br />~ /ethmac/trunk/rtl/verilog/eth_crc.v<br />~ /ethmac/trunk/rtl/verilog/eth_fifo.v<br />~ /ethmac/trunk/rtl/verilog/eth_maccontrol.v<br />~ /ethmac/trunk/rtl/verilog/eth_macstatus.v<br />~ /ethmac/trunk/rtl/verilog/eth_miim.v<br />~ /ethmac/trunk/rtl/verilog/eth_outputcontrol.v<br />~ /ethmac/trunk/rtl/verilog/eth_random.v<br />~ /ethmac/trunk/rtl/verilog/eth_receivecontrol.v<br />~ /ethmac/trunk/rtl/verilog/eth_register.v<br />~ /ethmac/trunk/rtl/verilog/eth_registers.v<br />~ /ethmac/trunk/rtl/verilog/eth_rxaddrcheck.v<br />~ /ethmac/trunk/rtl/verilog/eth_rxcounters.v<br />~ /ethmac/trunk/rtl/verilog/eth_rxethmac.v<br />~ /ethmac/trunk/rtl/verilog/eth_rxstatem.v<br />~ /ethmac/trunk/rtl/verilog/eth_shiftreg.v<br />~ /ethmac/trunk/rtl/verilog/eth_spram_256x32.v<br />~ /ethmac/trunk/rtl/verilog/eth_top.v<br />~ /ethmac/trunk/rtl/verilog/eth_transmitcontrol.v<br />~ /ethmac/trunk/rtl/verilog/eth_txcounters.v<br />~ /ethmac/trunk/rtl/verilog/eth_txethmac.v<br />~ /ethmac/trunk/rtl/verilog/eth_txstatem.v<br />~ /ethmac/trunk/rtl/verilog/eth_wishbone.v<br />
olof
Fri, 29 Jul 2011 10:25:44 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2F&rev=352
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Turn defines into parameters in eth_cop
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2F&rev=351
<div><strong>Rev 351 - olof</strong> (2 file(s) modified)</div><div>Turn defines into parameters in eth_cop</div>~ /ethmac/trunk/rtl/verilog/eth_cop.v<br />~ /ethmac/trunk/rtl/verilog/eth_defines.v<br />
olof
Wed, 20 Jul 2011 20:35:36 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2F&rev=351
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Turn M[1-2]_ADDRESSED_S[1-2] defines into wires
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2F&rev=350
<div><strong>Rev 350 - olof</strong> (2 file(s) modified)</div><div>Turn M[1-2]_ADDRESSED_S[1-2] defines into wires</div>~ /ethmac/trunk/rtl/verilog/eth_cop.v<br />~ /ethmac/trunk/rtl/verilog/eth_defines.v<br />
olof
Wed, 20 Jul 2011 20:00:37 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2F&rev=350
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Make all parameters configurable from top level
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2F&rev=349
<div><strong>Rev 349 - olof</strong> (6 file(s) modified)</div><div>Make all parameters configurable from top level</div>~ /ethmac/trunk/rtl/verilog/eth_maccontrol.v<br />~ /ethmac/trunk/rtl/verilog/eth_miim.v<br />~ /ethmac/trunk/rtl/verilog/eth_rxethmac.v<br />~ /ethmac/trunk/rtl/verilog/eth_top.v<br />~ /ethmac/trunk/rtl/verilog/eth_txethmac.v<br />~ /ethmac/trunk/rtl/verilog/eth_wishbone.v<br />
olof
Tue, 19 Jul 2011 19:22:42 +0100
https://opencores.org/websvn//websvn/revision?repname=ethmac&path=%2F&rev=349
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