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mem_ctrl
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https://opencores.org/websvn//websvn/listing?repname=mem_ctrl&path=&
Mon, 24 Aug 2026 20:52:36 +0100
FeedCreator 1.7.2
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Added old uploaded documents to new repository.
https://opencores.org/websvn//websvn/revision?repname=mem_ctrl&path=%2F&rev=30
<div><strong>Rev 30 - root</strong> (6 file(s) modified)</div><div>Added old uploaded documents to new repository.</div>+ /mem_ctrl/web_uploads/index.shtml<br />- /mem_ctrl/web_uploads/oc_checkin.sh<br />- /mem_ctrl/web_uploads/oc_cvs_checkin.sh<br />- /mem_ctrl/web_uploads/svn_checkin.log<br />- /mem_ctrl/web_uploads/svn_checkin.sh<br />- /mem_ctrl/web_uploads/temp.sh<br />
root
Tue, 10 Mar 2009 14:08:29 +0100
https://opencores.org/websvn//websvn/revision?repname=mem_ctrl&path=%2F&rev=30
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Added old uploaded documents to new repository.
https://opencores.org/websvn//websvn/revision?repname=mem_ctrl&path=%2F&rev=29
<div><strong>Rev 29 - root</strong> (5 file(s) modified)</div><div>Added old uploaded documents to new repository.</div>+ /mem_ctrl/web_uploads/oc_checkin.sh<br />+ /mem_ctrl/web_uploads/oc_cvs_checkin.sh<br />+ /mem_ctrl/web_uploads/svn_checkin.log<br />+ /mem_ctrl/web_uploads/svn_checkin.sh<br />+ /mem_ctrl/web_uploads/temp.sh<br />
root
Tue, 10 Mar 2009 01:09:31 +0100
https://opencores.org/websvn//websvn/revision?repname=mem_ctrl&path=%2F&rev=29
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New directory structure.
https://opencores.org/websvn//websvn/revision?repname=mem_ctrl&path=%2F&rev=28
<div><strong>Rev 28 - root</strong> (8 file(s) modified)</div><div>New directory structure.</div>- /branches<br />+ /mem_ctrl<br />+ /mem_ctrl/branches<br />+ /mem_ctrl/tags<br />+ /mem_ctrl/trunk<br />+ /mem_ctrl/web_uploads<br />- /tags<br />- /trunk<br />
root
Tue, 10 Mar 2009 01:08:35 +0100
https://opencores.org/websvn//websvn/revision?repname=mem_ctrl&path=%2F&rev=28
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Initial release
https://opencores.org/websvn//websvn/revision?repname=mem_ctrl&path=%2F&rev=27
<div><strong>Rev 27 - rherveille</strong> (3 file(s) modified)</div><div>Initial release</div>+ /trunk/sim/rtl_sim/richard<br />+ /trunk/sim/rtl_sim/richard/run<br />+ /trunk/sim/rtl_sim/richard/run/run<br />
rherveille
Wed, 06 Mar 2002 15:22:47 +0100
https://opencores.org/websvn//websvn/revision?repname=mem_ctrl&path=%2F&rev=27
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Initial release
https://opencores.org/websvn//websvn/revision?repname=mem_ctrl&path=%2F&rev=26
<div><strong>Rev 26 - rherveille</strong> (4 file(s) modified)</div><div>Initial release</div>+ /trunk/bench/richard/verilog/models<br />+ /trunk/bench/richard/verilog/models/m8kx8.v<br />+ /trunk/bench/richard/verilog/models/mt48lc16m16a2.v<br />+ /trunk/bench/richard/verilog/models/mt58l1my18d.v<br />
rherveille
Wed, 06 Mar 2002 15:15:35 +0100
https://opencores.org/websvn//websvn/revision?repname=mem_ctrl&path=%2F&rev=26
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Initial release
https://opencores.org/websvn//websvn/revision?repname=mem_ctrl&path=%2F&rev=25
<div><strong>Rev 25 - rherveille</strong> (11 file(s) modified)</div><div>Initial release</div>+ /trunk/bench/richard<br />+ /trunk/bench/richard/verilog<br />+ /trunk/bench/richard/verilog/bench.v<br />+ /trunk/bench/richard/verilog/checkers.v<br />+ /trunk/bench/richard/verilog/mc_defines.v<br />+ /trunk/bench/richard/verilog/timescale.v<br />+ /trunk/bench/richard/verilog/tst_asram.v<br />+ /trunk/bench/richard/verilog/tst_multi_mem.v<br />+ /trunk/bench/richard/verilog/tst_sdram.v<br />+ /trunk/bench/richard/verilog/tst_ssram.v<br />+ /trunk/bench/richard/verilog/wb_master_model.v<br />
rherveille
Wed, 06 Mar 2002 15:10:34 +0100
https://opencores.org/websvn//websvn/revision?repname=mem_ctrl&path=%2F&rev=25
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*** empty log message ***
https://opencores.org/websvn//websvn/revision?repname=mem_ctrl&path=%2F&rev=24
<div><strong>Rev 24 - rudi</strong> (1 file(s) modified)</div><div>*** empty log message ***</div>~ /trunk/doc/mc_doc.pdf<br />
rudi
Mon, 21 Jan 2002 13:20:36 +0100
https://opencores.org/websvn//websvn/revision?repname=mem_ctrl&path=%2F&rev=24
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*** empty log message ***
https://opencores.org/websvn//websvn/revision?repname=mem_ctrl&path=%2F&rev=23
<div><strong>Rev 23 - rudi</strong> (4 file(s) modified)</div><div>*** empty log message ***</div>~ /trunk/bench/verilog/sram_models/MicronSRAM/mt58l1my18d.v<br />~ /trunk/bench/verilog/tests.v<br />~ /trunk/bench/verilog/test_bench_top.v<br />~ /trunk/bench/verilog/test_lib.v<br />
rudi
Mon, 21 Jan 2002 13:10:37 +0100
https://opencores.org/websvn//websvn/revision?repname=mem_ctrl&path=%2F&rev=23
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Fixed several minor bugs, cleaned up the code further ...
https://opencores.org/websvn//websvn/revision?repname=mem_ctrl&path=%2F&rev=22
<div><strong>Rev 22 - rudi</strong> (14 file(s) modified)</div><div>Fixed several minor bugs, cleaned up the code further ...</div>~ /trunk/rtl/verilog/mc_adr_sel.v<br />~ /trunk/rtl/verilog/mc_cs_rf.v<br />~ /trunk/rtl/verilog/mc_defines.v<br />~ /trunk/rtl/verilog/mc_dp.v<br />~ /trunk/rtl/verilog/mc_incn_r.v<br />~ /trunk/rtl/verilog/mc_mem_if.v<br />~ /trunk/rtl/verilog/mc_obct.v<br />~ /trunk/rtl/verilog/mc_obct_top.v<br />~ /trunk/rtl/verilog/mc_rd_fifo.v<br />~ /trunk/rtl/verilog/mc_refresh.v<br />~ /trunk/rtl/verilog/mc_rf.v<br />~ /trunk/rtl/verilog/mc_timing.v<br />~ /trunk/rtl/verilog/mc_top.v<br />~ /trunk/rtl/verilog/mc_wb_if.v<br />
rudi
Mon, 21 Jan 2002 13:08:52 +0100
https://opencores.org/websvn//websvn/revision?repname=mem_ctrl&path=%2F&rev=22
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Updated Spec ...
https://opencores.org/websvn//websvn/revision?repname=mem_ctrl&path=%2F&rev=21
<div><strong>Rev 21 - rudi</strong> (1 file(s) modified)</div><div>Updated Spec ...</div>~ /trunk/doc/mc_doc.pdf<br />
rudi
Tue, 15 Jan 2002 01:10:32 +0100
https://opencores.org/websvn//websvn/revision?repname=mem_ctrl&path=%2F&rev=21
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- Fixed combinatorial loops in synthesis
- Fixed byte select bug
https://opencores.org/websvn//websvn/revision?repname=mem_ctrl&path=%2F&rev=20
<div><strong>Rev 20 - rudi</strong> (5 file(s) modified)</div><div>- Fixed combinatorial loops in synthesis<br />
- Fixed byte select bug</div>~ /trunk/rtl/verilog/mc_mem_if.v<br />~ /trunk/rtl/verilog/mc_obct_top.v<br />~ /trunk/rtl/verilog/mc_rf.v<br />~ /trunk/rtl/verilog/mc_timing.v<br />~ /trunk/rtl/verilog/mc_top.v<br />
rudi
Fri, 21 Dec 2001 05:09:30 +0100
https://opencores.org/websvn//websvn/revision?repname=mem_ctrl&path=%2F&rev=20
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*** empty log message ***
https://opencores.org/websvn//websvn/revision?repname=mem_ctrl&path=%2F&rev=19
<div><strong>Rev 19 - rudi</strong> (1 file(s) modified)</div><div>*** empty log message ***</div>~ /trunk/rtl/verilog/mc_defines.v<br />
rudi
Wed, 12 Dec 2001 06:35:15 +0100
https://opencores.org/websvn//websvn/revision?repname=mem_ctrl&path=%2F&rev=19
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- Made some changes not to expect clock during reset ...
https://opencores.org/websvn//websvn/revision?repname=mem_ctrl&path=%2F&rev=18
<div><strong>Rev 18 - rudi</strong> (8 file(s) modified)</div><div>- Made some changes not to expect clock during reset ...</div>~ /trunk/rtl/verilog/mc_cs_rf.v<br />~ /trunk/rtl/verilog/mc_defines.v<br />~ /trunk/rtl/verilog/mc_dp.v<br />~ /trunk/rtl/verilog/mc_rd_fifo.v<br />~ /trunk/rtl/verilog/mc_refresh.v<br />~ /trunk/rtl/verilog/mc_rf.v<br />~ /trunk/rtl/verilog/mc_timing.v<br />~ /trunk/rtl/verilog/mc_wb_if.v<br />
rudi
Tue, 11 Dec 2001 02:47:19 +0100
https://opencores.org/websvn//websvn/revision?repname=mem_ctrl&path=%2F&rev=18
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- Updated Documentation
- More Synthesis cleanup, mostly for speed
- Several ...
https://opencores.org/websvn//websvn/revision?repname=mem_ctrl&path=%2F&rev=17
<div><strong>Rev 17 - rudi</strong> (2 file(s) modified)</div><div>- Updated Documentation<br />
- More Synthesis cleanup, mostly for speed<br />
- Several ...</div>~ /trunk/doc/mc_doc.pdf<br />~ /trunk/doc/STATUS.txt<br />
rudi
Thu, 29 Nov 2001 02:21:07 +0100
https://opencores.org/websvn//websvn/revision?repname=mem_ctrl&path=%2F&rev=17
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- More Synthesis cleanup, mostly for speed
- Several bug fixes
- ...
https://opencores.org/websvn//websvn/revision?repname=mem_ctrl&path=%2F&rev=16
<div><strong>Rev 16 - rudi</strong> (16 file(s) modified)</div><div>- More Synthesis cleanup, mostly for speed<br />
- Several bug fixes<br />
- ...</div>~ /trunk/bench/verilog/160b3ver/adv_bb.v<br />~ /trunk/bench/verilog/sdram_models/16Mx16/mt48lc16m16a2.v<br />~ /trunk/bench/verilog/tests.v<br />~ /trunk/bench/verilog/test_bench_top.v<br />~ /trunk/bench/verilog/wb_mast_model.v<br />~ /trunk/rtl/verilog/mc_adr_sel.v<br />~ /trunk/rtl/verilog/mc_cs_rf.v<br />~ /trunk/rtl/verilog/mc_defines.v<br />~ /trunk/rtl/verilog/mc_dp.v<br />~ /trunk/rtl/verilog/mc_mem_if.v<br />~ /trunk/rtl/verilog/mc_obct.v<br />~ /trunk/rtl/verilog/mc_rd_fifo.v<br />~ /trunk/rtl/verilog/mc_rf.v<br />~ /trunk/rtl/verilog/mc_timing.v<br />~ /trunk/rtl/verilog/mc_top.v<br />~ /trunk/rtl/verilog/mc_wb_if.v<br />
rudi
Thu, 29 Nov 2001 02:17:37 +0100
https://opencores.org/websvn//websvn/revision?repname=mem_ctrl&path=%2F&rev=16
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Just minor test bench update, syncing all the files.
https://opencores.org/websvn//websvn/revision?repname=mem_ctrl&path=%2F&rev=15
<div><strong>Rev 15 - rudi</strong> (3 file(s) modified)</div><div>Just minor test bench update, syncing all the files.</div>~ /trunk/bench/verilog/sdram_models/16Mx16/mt48lc16m16a2.v<br />~ /trunk/bench/verilog/tests.v<br />~ /trunk/bench/verilog/test_bench_top.v<br />
rudi
Tue, 13 Nov 2001 00:45:27 +0100
https://opencores.org/websvn//websvn/revision?repname=mem_ctrl&path=%2F&rev=15
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Minor fixes to testbench ...
https://opencores.org/websvn//websvn/revision?repname=mem_ctrl&path=%2F&rev=14
<div><strong>Rev 14 - rudi</strong> (4 file(s) modified)</div><div>Minor fixes to testbench ...</div>~ /trunk/bench/verilog/tests.v<br />~ /trunk/bench/verilog/test_bench_top.v<br />~ /trunk/bench/verilog/test_lib.v<br />~ /trunk/bench/verilog/wb_mast_model.v<br />
rudi
Sun, 11 Nov 2001 01:52:03 +0100
https://opencores.org/websvn//websvn/revision?repname=mem_ctrl&path=%2F&rev=14
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Fixed Register reads
Tightened up timing for register rd/wr
https://opencores.org/websvn//websvn/revision?repname=mem_ctrl&path=%2F&rev=13
<div><strong>Rev 13 - rudi</strong> (1 file(s) modified)</div><div>Fixed Register reads<br />
Tightened up timing for register rd/wr</div>~ /trunk/rtl/verilog/mc_rf.v<br />
rudi
Thu, 04 Oct 2001 03:19:37 +0100
https://opencores.org/websvn//websvn/revision?repname=mem_ctrl&path=%2F&rev=13
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Changed Reset to be active high and async.
https://opencores.org/websvn//websvn/revision?repname=mem_ctrl&path=%2F&rev=12
<div><strong>Rev 12 - rudi</strong> (8 file(s) modified)</div><div>Changed Reset to be active high and async.</div>~ /trunk/rtl/verilog/mc_cs_rf.v<br />~ /trunk/rtl/verilog/mc_dp.v<br />~ /trunk/rtl/verilog/mc_mem_if.v<br />~ /trunk/rtl/verilog/mc_obct.v<br />~ /trunk/rtl/verilog/mc_refresh.v<br />~ /trunk/rtl/verilog/mc_rf.v<br />~ /trunk/rtl/verilog/mc_timing.v<br />~ /trunk/rtl/verilog/mc_wb_if.v<br />
rudi
Mon, 24 Sep 2001 00:38:21 +0100
https://opencores.org/websvn//websvn/revision?repname=mem_ctrl&path=%2F&rev=12
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*** empty log message ***
https://opencores.org/websvn//websvn/revision?repname=mem_ctrl&path=%2F&rev=11
<div><strong>Rev 11 - rudi</strong> (2 file(s) modified)</div><div>*** empty log message ***</div>~ /trunk/rtl/verilog/mc_defines.v<br />~ /trunk/rtl/verilog/mc_top.v<br />
rudi
Mon, 10 Sep 2001 13:44:17 +0100
https://opencores.org/websvn//websvn/revision?repname=mem_ctrl&path=%2F&rev=11
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