OpenCores

URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Error creating feed file, please check write permissions.
openrisc WebSVN RSS feed - openrisc https://opencores.org/websvn//websvn/listing?repname=openrisc&path=& Sun, 03 May 2026 12:47:48 +0100 FeedCreator 1.7.2 Declare du_flush_pipe in or1200_top Signed-off-by: Olof Kindgren <olof at opencores. ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2F&rev=868 <div><strong>Rev 868 - olof</strong> (1 file(s) modified)</div><div>Declare du_flush_pipe in or1200_top<br /> <br /> Signed-off-by: Olof Kindgren <olof at opencores.org></div>~ /openrisc/trunk/or1200/rtl/verilog/or1200_top.v<br /> olof Tue, 16 Sep 2014 07:12:10 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2F&rev=868 Publish OR1K 1.1 architecture spec Changelog: - Add atomicity chapter. - Add l.lwa ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2F&rev=867 <div><strong>Rev 867 - stekern</strong> (2 file(s) modified)</div><div>Publish OR1K 1.1 architecture spec<br /> <br /> Changelog:<br /> - Add atomicity chapter.<br /> - Add l.lwa ...</div>+ /openrisc/trunk/docs/openrisc-arch-1.1-rev0.odt<br />+ /openrisc/trunk/docs/openrisc-arch-1.1-rev0.pdf<br /> stekern Mon, 12 May 2014 10:33:07 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2F&rev=867 orpsocv2: correct build/par issue on Atlys board From patch submission e-mail: The ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2F&rev=866 <div><strong>Rev 866 - stekern</strong> (1 file(s) modified)</div><div>orpsocv2: correct build/par issue on Atlys board<br /> <br /> From patch submission e-mail:<br /> <br /> The ...</div>~ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/backend/par/bin/Makefile<br /> stekern Tue, 22 Apr 2014 05:19:09 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2F&rev=866 Raise illegal instruction exception when l.ror is not implemented Instead of ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2F&rev=865 <div><strong>Rev 865 - olof</strong> (1 file(s) modified)</div><div>Raise illegal instruction exception when l.ror is not implemented<br /> <br /> Instead of ...</div>~ /openrisc/trunk/or1200/rtl/verilog/or1200_ctrl.v<br /> olof Sun, 20 Oct 2013 09:06:44 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2F&rev=865 ORPSoC: Merge display_arch_state tasks or1200-monitor contains the tasks display_arch_state ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2F&rev=864 <div><strong>Rev 864 - olof</strong> (1 file(s) modified)</div><div>ORPSoC: Merge display_arch_state tasks<br /> <br /> or1200-monitor contains the tasks display_arch_state and display_arch_state_except ...</div>~ /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v<br /> olof Fri, 19 Jul 2013 22:40:01 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2F&rev=864 ORPSoC: Add paramers to or1200-monitor for setting name and path ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2F&rev=863 <div><strong>Rev 863 - olof</strong> (2 file(s) modified)</div><div>ORPSoC: Add paramers to or1200-monitor for setting name and path ...</div>~ /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v<br />~ /openrisc/trunk/orpsocv2/bench/verilog/orpsoc_testbench.v<br /> olof Sat, 13 Jul 2013 18:51:39 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2F&rev=863 sysc: avoid using orpsoc internal classes directly The problem with using ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2F&rev=862 <div><strong>Rev 862 - stekern</strong> (2 file(s) modified)</div><div>sysc: avoid using orpsoc internal classes directly<br /> <br /> The problem with using ...</div>~ /openrisc/trunk/orpsocv2/bench/sysc/include/OrpsocAccess.h<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocAccess.cpp<br /> stekern Wed, 03 Jul 2013 02:46:44 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2F&rev=862 sysc: include unistd.h write, read, pipe et al are declared in ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2F&rev=861 <div><strong>Rev 861 - stekern</strong> (4 file(s) modified)</div><div>sysc: include unistd.h<br /> <br /> write, read, pipe et al are declared in ...</div>~ /openrisc/trunk/orpsocv2/bench/sysc/src/GdbServerSC.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/RspConnection.cpp<br />~ /openrisc/trunk/orpsocv2/bench/sysc/src/UartSC.cpp<br /> stekern Wed, 03 Jul 2013 02:46:42 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2F&rev=861 or1200_monitor.v: Remove trailing whitespace https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2F&rev=860 <div><strong>Rev 860 - olof</strong> (1 file(s) modified)</div><div>or1200_monitor.v: Remove trailing whitespace</div>~ /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v<br /> olof Fri, 28 Jun 2013 21:15:06 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2F&rev=860 Execute trapped instruction after breakpoint is removed Closes bug #104 When the ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2F&rev=859 <div><strong>Rev 859 - olof</strong> (5 file(s) modified)</div><div>Execute trapped instruction after breakpoint is removed<br /> <br /> Closes bug #104<br /> <br /> When the ...</div>~ /openrisc/trunk/or1200/rtl/verilog/or1200_cpu.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_ctrl.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_du.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_genpc.v<br />~ /openrisc/trunk/or1200/rtl/verilog/or1200_top.v<br /> olof Fri, 28 Jun 2013 19:35:01 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2F&rev=859 orpsoc/tests: Fix or1200-dsxinsn when caches are not present This test would ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2F&rev=858 <div><strong>Rev 858 - stekern</strong> (1 file(s) modified)</div><div>orpsoc/tests: Fix or1200-dsxinsn when caches are not present<br /> <br /> This test would ...</div>~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-dsxinsn.S<br /> stekern Wed, 20 Mar 2013 13:57:15 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2F&rev=858 orpsocv2: remove reference to r32 in context save/restore https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2F&rev=857 <div><strong>Rev 857 - julius</strong> (1 file(s) modified)</div><div>orpsocv2: remove reference to r32 in context save/restore</div>~ /openrisc/trunk/orpsocv2/sw/drivers/or1200/crt0.S<br /> julius Sun, 10 Mar 2013 23:43:14 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2F&rev=857 Fixed rounding of UART divisor https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2F&rev=856 <div><strong>Rev 856 - skrzyp</strong> (1 file(s) modified)</div><div>Fixed rounding of UART divisor</div>~ /openrisc/trunk/rtos/ecos-3.0/packages/hal/openrisc/orpsoc/current/src/hal_diag.c<br /> skrzyp Fri, 25 Jan 2013 20:46:05 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2F&rev=856 Publish OR1K 1.0 architecture spec https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2F&rev=855 <div><strong>Rev 855 - julius</strong> (9 file(s) modified)</div><div>Publish OR1K 1.0 architecture spec</div>+ /openrisc/trunk/docs/archive<br />+ /openrisc/trunk/docs/archive/openrisc_arch.doc<br />+ /openrisc/trunk/docs/archive/openrisc_arch.pdf<br />+ /openrisc/trunk/docs/archive/openrisc_arch_draft.odt<br />+ /openrisc/trunk/docs/openrisc-arch-1.0-rev0.odt<br />+ /openrisc/trunk/docs/openrisc-arch-1.0-rev0.pdf<br />- /openrisc/trunk/docs/openrisc_arch.doc<br />- /openrisc/trunk/docs/openrisc_arch.pdf<br />- /openrisc/trunk/docs/openrisc_arch_draft.odt<br /> julius Thu, 13 Dec 2012 21:49:54 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2F&rev=855 Add OR1200_OR32_LWS define to board specific or1200_defines.v https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2F&rev=854 <div><strong>Rev 854 - stekern</strong> (4 file(s) modified)</div><div>Add OR1200_OR32_LWS define to board specific or1200_defines.v</div>~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include/or1200_defines.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/atlys/rtl/verilog/include/or1200_defines.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/include/or1200_defines.v<br />~ /openrisc/trunk/orpsocv2/boards/xilinx/s3adsp1800/rtl/verilog/include/or1200_defines.v<br /> stekern Tue, 04 Dec 2012 04:27:31 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2F&rev=854 Declare pcreg_boot before usage When things were moved around in rev ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2F&rev=853 <div><strong>Rev 853 - olof</strong> (1 file(s) modified)</div><div>Declare pcreg_boot before usage<br /> <br /> When things were moved around in rev ...</div>~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_genpc.v<br /> olof Thu, 08 Nov 2012 19:17:37 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2F&rev=853 Declare pcreg_boot before usage When things were moved around in rev ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2F&rev=852 <div><strong>Rev 852 - olof</strong> (1 file(s) modified)</div><div>Declare pcreg_boot before usage<br /> <br /> When things were moved around in rev ...</div>~ /openrisc/trunk/or1200/rtl/verilog/or1200_genpc.v<br /> olof Thu, 08 Nov 2012 19:08:55 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2F&rev=852 changed branch delay flags https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2F&rev=851 <div><strong>Rev 851 - skrzyp</strong> (1 file(s) modified)</div><div>changed branch delay flags</div>~ /openrisc/trunk/rtos/ecos-3.0/packages/hal/openrisc/orpsoc/current/cdl/hal_openrisc_orpsoc.cdl<br /> skrzyp Mon, 05 Nov 2012 19:34:29 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2F&rev=851 or1200_genpc: fix ipcu_cycstb_o generation In some circumstances the CPU is still ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2F&rev=850 <div><strong>Rev 850 - stekern</strong> (2 file(s) modified)</div><div>or1200_genpc: fix ipcu_cycstb_o generation<br /> <br /> In some circumstances the CPU is still ...</div>~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_cpu.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_genpc.v<br /> stekern Thu, 25 Oct 2012 03:30:22 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2F&rev=850 or1200: Fix for cache bug related to first_{hit|miss}_ack Under certain circumstances, ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2F&rev=849 <div><strong>Rev 849 - stekern</strong> (2 file(s) modified)</div><div>or1200: Fix for cache bug related to first_{hit|miss}_ack<br /> <br /> Under certain circumstances, ...</div>~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_dc_fsm.v<br />~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_ic_fsm.v<br /> stekern Thu, 25 Oct 2012 03:30:20 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2F&rev=849

Browse

Tools