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rise
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https://opencores.org/websvn//websvn/listing?repname=rise&path=&
Thu, 10 Sep 2026 09:29:27 +0100
FeedCreator 1.7.2
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Started to include generic VHDL description of memories.
https://opencores.org/websvn//websvn/revision?repname=rise&path=%2F&rev=151
<div><strong>Rev 151 - jlechner</strong> (3 file(s) modified)</div><div>Started to include generic VHDL description of memories.</div>- /rise/trunk/vhdl/dmem.vhd<br />+ /rise/trunk/vhdl/memctrl.vhd<br />~ /rise/trunk/vhdl/rise_pack.vhd<br />
jlechner
Tue, 09 Feb 2010 20:05:39 +0100
https://opencores.org/websvn//websvn/revision?repname=rise&path=%2F&rev=151
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Added old uploaded documents to new repository.
https://opencores.org/websvn//websvn/revision?repname=rise&path=%2F&rev=150
<div><strong>Rev 150 - root</strong> (5 file(s) modified)</div><div>Added old uploaded documents to new repository.</div>- /rise/web_uploads/oc_checkin.sh<br />- /rise/web_uploads/oc_cvs_checkin.sh<br />- /rise/web_uploads/svn_checkin.log<br />- /rise/web_uploads/svn_checkin.sh<br />- /rise/web_uploads/temp.sh<br />
root
Tue, 10 Mar 2009 15:16:01 +0100
https://opencores.org/websvn//websvn/revision?repname=rise&path=%2F&rev=150
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Added old uploaded documents to new repository.
https://opencores.org/websvn//websvn/revision?repname=rise&path=%2F&rev=149
<div><strong>Rev 149 - root</strong> (5 file(s) modified)</div><div>Added old uploaded documents to new repository.</div>+ /rise/web_uploads/oc_checkin.sh<br />+ /rise/web_uploads/oc_cvs_checkin.sh<br />+ /rise/web_uploads/svn_checkin.log<br />+ /rise/web_uploads/svn_checkin.sh<br />+ /rise/web_uploads/temp.sh<br />
root
Tue, 10 Mar 2009 09:00:27 +0100
https://opencores.org/websvn//websvn/revision?repname=rise&path=%2F&rev=149
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New directory structure.
https://opencores.org/websvn//websvn/revision?repname=rise&path=%2F&rev=148
<div><strong>Rev 148 - root</strong> (8 file(s) modified)</div><div>New directory structure.</div>- /branches<br />+ /rise<br />+ /rise/branches<br />+ /rise/tags<br />+ /rise/trunk<br />+ /rise/web_uploads<br />- /tags<br />- /trunk<br />
root
Tue, 10 Mar 2009 08:59:58 +0100
https://opencores.org/websvn//websvn/revision?repname=rise&path=%2F&rev=148
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- Updated to use current example.
https://opencores.org/websvn//websvn/revision?repname=rise&path=%2F&rev=147
<div><strong>Rev 147 - cwalter</strong> (1 file(s) modified)</div><div>- Updated to use current example.</div>~ /trunk/simulation/rise.mpf<br />
cwalter
Fri, 26 Jan 2007 01:02:38 +0100
https://opencores.org/websvn//websvn/revision?repname=rise&path=%2F&rev=147
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- Changed to compile UART example.
https://opencores.org/websvn//websvn/revision?repname=rise&path=%2F&rev=146
<div><strong>Rev 146 - cwalter</strong> (1 file(s) modified)</div><div>- Changed to compile UART example.</div>~ /trunk/examples/Makefile.simple<br />
cwalter
Thu, 25 Jan 2007 22:52:58 +0100
https://opencores.org/websvn//websvn/revision?repname=rise&path=%2F&rev=146
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- Added more VHDL files to project.
https://opencores.org/websvn//websvn/revision?repname=rise&path=%2F&rev=145
<div><strong>Rev 145 - cwalter</strong> (1 file(s) modified)</div><div>- Added more VHDL files to project.</div>~ /trunk/simulation/rise.mpf<br />
cwalter
Thu, 25 Jan 2007 22:50:12 +0100
https://opencores.org/websvn//websvn/revision?repname=rise&path=%2F&rev=145
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- IF stage now uses autogenerated VHDL files.
https://opencores.org/websvn//websvn/revision?repname=rise&path=%2F&rev=144
<div><strong>Rev 144 - cwalter</strong> (1 file(s) modified)</div><div>- IF stage now uses autogenerated VHDL files.</div>~ /trunk/vhdl/if_stage.vhd<br />
cwalter
Thu, 25 Jan 2007 22:48:46 +0100
https://opencores.org/websvn//websvn/revision?repname=rise&path=%2F&rev=144
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- Added more complex UART example.
https://opencores.org/websvn//websvn/revision?repname=rise&path=%2F&rev=143
<div><strong>Rev 143 - cwalter</strong> (1 file(s) modified)</div><div>- Added more complex UART example.</div>+ /trunk/examples/uart_complex.s<br />
cwalter
Thu, 25 Jan 2007 22:31:12 +0100
https://opencores.org/websvn//websvn/revision?repname=rise&path=%2F&rev=143
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- Added gap between characters sent and changed last character ...
https://opencores.org/websvn//websvn/revision?repname=rise&path=%2F&rev=142
<div><strong>Rev 142 - cwalter</strong> (1 file(s) modified)</div><div>- Added gap between characters sent and changed last character ...</div>~ /trunk/vhdl/tb_rise_uart.vhd<br />
cwalter
Thu, 25 Jan 2007 22:25:30 +0100
https://opencores.org/websvn//websvn/revision?repname=rise&path=%2F&rev=142
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- Added delay between characters.
https://opencores.org/websvn//websvn/revision?repname=rise&path=%2F&rev=141
<div><strong>Rev 141 - cwalter</strong> (1 file(s) modified)</div><div>- Added delay between characters.</div>~ /trunk/vhdl/tb_rise_uart.vhd<br />
cwalter
Thu, 25 Jan 2007 22:06:41 +0100
https://opencores.org/websvn//websvn/revision?repname=rise&path=%2F&rev=141
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- Test bench for RISE with UART.
https://opencores.org/websvn//websvn/revision?repname=rise&path=%2F&rev=140
<div><strong>Rev 140 - cwalter</strong> (1 file(s) modified)</div><div>- Test bench for RISE with UART.</div>+ /trunk/vhdl/tb_rise_uart.vhd<br />
cwalter
Thu, 25 Jan 2007 22:01:31 +0100
https://opencores.org/websvn//websvn/revision?repname=rise&path=%2F&rev=140
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- Added makefile example to improve design flow.
- Added ...
https://opencores.org/websvn//websvn/revision?repname=rise&path=%2F&rev=139
<div><strong>Rev 139 - cwalter</strong> (3 file(s) modified)</div><div>- Added makefile example to improve design flow.<br />
- Added ...</div>~ /trunk/examples/Makefile<br />+ /trunk/examples/Makefile.simple<br />~ /trunk/examples/subroutine.s<br />
cwalter
Thu, 25 Jan 2007 21:20:06 +0100
https://opencores.org/websvn//websvn/revision?repname=rise&path=%2F&rev=139
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- Fixed binary to VHDL converter.
https://opencores.org/websvn//websvn/revision?repname=rise&path=%2F&rev=138
<div><strong>Rev 138 - cwalter</strong> (2 file(s) modified)</div><div>- Fixed binary to VHDL converter.</div>~ /trunk/tools/bin2vhd.c<br />~ /trunk/tools/bin2vhd.exe<br />
cwalter
Thu, 25 Jan 2007 21:08:25 +0100
https://opencores.org/websvn//websvn/revision?repname=rise&path=%2F&rev=138
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- Added binary to VHDL converter.
https://opencores.org/websvn//websvn/revision?repname=rise&path=%2F&rev=137
<div><strong>Rev 137 - cwalter</strong> (2 file(s) modified)</div><div>- Added binary to VHDL converter.</div>+ /trunk/tools/bin2vhd.c<br />+ /trunk/tools/bin2vhd.exe<br />
cwalter
Thu, 25 Jan 2007 20:32:30 +0100
https://opencores.org/websvn//websvn/revision?repname=rise&path=%2F&rev=137
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- Added makefile example to improve design flow.
- Added ...
https://opencores.org/websvn//websvn/revision?repname=rise&path=%2F&rev=136
<div><strong>Rev 136 - cwalter</strong> (2 file(s) modified)</div><div>- Added makefile example to improve design flow.<br />
- Added ...</div>+ /trunk/examples/Makefile<br />+ /trunk/examples/subroutine.s<br />
cwalter
Thu, 25 Jan 2007 20:32:15 +0100
https://opencores.org/websvn//websvn/revision?repname=rise&path=%2F&rev=136
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uart_address_0 was a latch -> changed
https://opencores.org/websvn//websvn/revision?repname=rise&path=%2F&rev=135
<div><strong>Rev 135 - ustadler</strong> (1 file(s) modified)</div><div>uart_address_0 was a latch -> changed</div>~ /trunk/vhdl/dmem.vhd<br />
ustadler
Thu, 25 Jan 2007 00:25:27 +0100
https://opencores.org/websvn//websvn/revision?repname=rise&path=%2F&rev=135
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Added second test program for testing uart.
https://opencores.org/websvn//websvn/revision?repname=rise&path=%2F&rev=134
<div><strong>Rev 134 - jlechner</strong> (1 file(s) modified)</div><div>Added second test program for testing uart.</div>~ /trunk/vhdl/if_stage.vhd<br />
jlechner
Thu, 25 Jan 2007 00:19:40 +0100
https://opencores.org/websvn//websvn/revision?repname=rise&path=%2F&rev=134
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- Fixed bug with ST opcodes.
https://opencores.org/websvn//websvn/revision?repname=rise&path=%2F&rev=133
<div><strong>Rev 133 - cwalter</strong> (1 file(s) modified)</div><div>- Fixed bug with ST opcodes.</div>+ /trunk/tools/patch-rise-1.8<br />
cwalter
Wed, 24 Jan 2007 22:36:46 +0100
https://opencores.org/websvn//websvn/revision?repname=rise&path=%2F&rev=133
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Added test program for testing uart.
https://opencores.org/websvn//websvn/revision?repname=rise&path=%2F&rev=132
<div><strong>Rev 132 - jlechner</strong> (1 file(s) modified)</div><div>Added test program for testing uart.</div>~ /trunk/vhdl/if_stage.vhd<br />
jlechner
Wed, 24 Jan 2007 22:21:16 +0100
https://opencores.org/websvn//websvn/revision?repname=rise&path=%2F&rev=132
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