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            <description>&lt;div&gt;&lt;strong&gt;Rev 61 - root&lt;/strong&gt; (6 file(s) modified)&lt;/div&gt;&lt;div&gt;Added old uploaded documents to new repository.&lt;/div&gt;- /sxp/web_uploads/oc_checkin.sh&lt;br /&gt;- /sxp/web_uploads/oc_cvs_checkin.sh&lt;br /&gt;- /sxp/web_uploads/svn_checkin.log&lt;br /&gt;- /sxp/web_uploads/svn_checkin.sh&lt;br /&gt;+ /sxp/web_uploads/sxp_block.gif&lt;br /&gt;- /sxp/web_uploads/temp.sh&lt;br /&gt;</description>
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            <title>Added old uploaded documents to new repository.</title>
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            <description>&lt;div&gt;&lt;strong&gt;Rev 60 - root&lt;/strong&gt; (5 file(s) modified)&lt;/div&gt;&lt;div&gt;Added old uploaded documents to new repository.&lt;/div&gt;+ /sxp/web_uploads/oc_checkin.sh&lt;br /&gt;+ /sxp/web_uploads/oc_cvs_checkin.sh&lt;br /&gt;+ /sxp/web_uploads/svn_checkin.log&lt;br /&gt;+ /sxp/web_uploads/svn_checkin.sh&lt;br /&gt;+ /sxp/web_uploads/temp.sh&lt;br /&gt;</description>
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            <title>New directory structure.</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=sxp&amp;path=%2F&amp;rev=59</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 59 - root&lt;/strong&gt; (8 file(s) modified)&lt;/div&gt;&lt;div&gt;New directory structure.&lt;/div&gt;- /branches&lt;br /&gt;+ /sxp&lt;br /&gt;+ /sxp/branches&lt;br /&gt;+ /sxp/tags&lt;br /&gt;+ /sxp/trunk&lt;br /&gt;+ /sxp/web_uploads&lt;br /&gt;- /tags&lt;br /&gt;- /trunk&lt;br /&gt;</description>
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            <pubDate>Tue, 10 Mar 2009 09:40:22 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=sxp&amp;path=%2F&amp;rev=59</guid>
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            <title>removed safe_switch from module (not needed)</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=sxp&amp;path=%2F&amp;rev=58</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 58 - samg&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;removed safe_switch from module (not needed)&lt;/div&gt;~ /trunk/int_cont/src/int_cont.v&lt;br /&gt;</description>
            <author>samg</author>
            <pubDate>Fri, 14 Dec 2001 17:04:52 +0100</pubDate>
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            <title>removed saf_switch from int_cont module</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=sxp&amp;path=%2F&amp;rev=57</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 57 - samg&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;removed saf_switch from int_cont module&lt;/div&gt;~ /trunk/src/sxp.v&lt;br /&gt;</description>
            <author>samg</author>
            <pubDate>Fri, 14 Dec 2001 17:04:06 +0100</pubDate>
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            <title>rewrite with one less interface signal and simplification of verilog ...</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=sxp&amp;path=%2F&amp;rev=56</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 56 - samg&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;rewrite with one less interface signal and simplification of verilog ...&lt;/div&gt;~ /trunk/regf/src/regf_status.v&lt;br /&gt;</description>
            <author>samg</author>
            <pubDate>Fri, 14 Dec 2001 16:57:32 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=sxp&amp;path=%2F&amp;rev=56</guid>
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            <title>simplified regf_status interface</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=sxp&amp;path=%2F&amp;rev=55</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 55 - samg&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;simplified regf_status interface&lt;/div&gt;~ /trunk/src/sxp.v&lt;br /&gt;</description>
            <author>samg</author>
            <pubDate>Fri, 14 Dec 2001 16:53:12 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=sxp&amp;path=%2F&amp;rev=55</guid>
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        <item>
            <title>fixed case statement, sensitivity list</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=sxp&amp;path=%2F&amp;rev=54</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 54 - samg&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;fixed case statement, sensitivity list&lt;/div&gt;~ /trunk/src/sxp.v&lt;br /&gt;</description>
            <author>samg</author>
            <pubDate>Wed, 12 Dec 2001 02:07:25 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=sxp&amp;path=%2F&amp;rev=54</guid>
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            <title>comment spelling fix</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=sxp&amp;path=%2F&amp;rev=53</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 53 - samg&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;comment spelling fix&lt;/div&gt;~ /trunk/fetch/src/fetch.v&lt;br /&gt;</description>
            <author>samg</author>
            <pubDate>Wed, 12 Dec 2001 02:02:21 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=sxp&amp;path=%2F&amp;rev=53</guid>
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            <title>minor expression rewrite in 4th stage</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=sxp&amp;path=%2F&amp;rev=52</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 52 - samg&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;minor expression rewrite in 4th stage&lt;/div&gt;~ /trunk/src/sxp.v&lt;br /&gt;</description>
            <author>samg</author>
            <pubDate>Thu, 06 Dec 2001 16:12:06 +0100</pubDate>
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            <title>Rewrote verilog for write enable signals for different destinations in ...</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=sxp&amp;path=%2F&amp;rev=51</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 51 - samg&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;Rewrote verilog for write enable signals for different destinations in ...&lt;/div&gt;~ /trunk/src/sxp.v&lt;br /&gt;</description>
            <author>samg</author>
            <pubDate>Wed, 05 Dec 2001 18:12:08 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=sxp&amp;path=%2F&amp;rev=51</guid>
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            <title>fixed sensitivity list error in last pipeline stage</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=sxp&amp;path=%2F&amp;rev=50</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 50 - samg&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;fixed sensitivity list error in last pipeline stage&lt;/div&gt;~ /trunk/src/sxp.v&lt;br /&gt;</description>
            <author>samg</author>
            <pubDate>Wed, 05 Dec 2001 05:58:10 +0100</pubDate>
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            <title>changed run script name and added instructions</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=sxp&amp;path=%2F&amp;rev=49</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 49 - samg&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;changed run script name and added instructions&lt;/div&gt;~ /trunk/sim/i_runtest&lt;br /&gt;</description>
            <author>samg</author>
            <pubDate>Wed, 05 Dec 2001 05:56:31 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=sxp&amp;path=%2F&amp;rev=49</guid>
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            <title>fixed neg edge event trigger</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=sxp&amp;path=%2F&amp;rev=48</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 48 - samg&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;fixed neg edge event trigger&lt;/div&gt;~ /trunk/dpmem/src/dpmem.v&lt;br /&gt;</description>
            <author>samg</author>
            <pubDate>Wed, 05 Dec 2001 05:46:00 +0100</pubDate>
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            <title>changed prefix from ~| to ! (same thing)</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=sxp&amp;path=%2F&amp;rev=47</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 47 - samg&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;changed prefix from ~| to ! (same thing)&lt;/div&gt;~ /trunk/int_cont/src/int_cont.v&lt;br /&gt;</description>
            <author>samg</author>
            <pubDate>Wed, 05 Dec 2001 05:44:26 +0100</pubDate>
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            <title>vcd dumpvar captures all levels</title>
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            <description>&lt;div&gt;&lt;strong&gt;Rev 46 - samg&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;vcd dumpvar captures all levels&lt;/div&gt;~ /trunk/sim/test_sxp.v&lt;br /&gt;</description>
            <author>samg</author>
            <pubDate>Sun, 02 Dec 2001 19:13:03 +0100</pubDate>
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            <title>Fixed bug in 16 bit data swap instruction.
The instructions were ...</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=sxp&amp;path=%2F&amp;rev=45</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 45 - samg&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;Fixed bug in 16 bit data swap instruction.&lt;br /&gt;
The instructions were ...&lt;/div&gt;~ /trunk/sim/test.sxp&lt;br /&gt;</description>
            <author>samg</author>
            <pubDate>Sun, 02 Dec 2001 19:10:56 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=sxp&amp;path=%2F&amp;rev=45</guid>
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            <title>- Removed #1 delay (was originally put in for debug)
- ...</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=sxp&amp;path=%2F&amp;rev=44</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 44 - samg&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;- Removed #1 delay (was originally put in for debug)&lt;br /&gt;
- ...&lt;/div&gt;~ /trunk/regf/src/regf_status.v&lt;br /&gt;</description>
            <author>samg</author>
            <pubDate>Sun, 02 Dec 2001 19:05:47 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=sxp&amp;path=%2F&amp;rev=44</guid>
        </item>
        <item>
            <title>integrated common rams into processor</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=sxp&amp;path=%2F&amp;rev=43</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 43 - samg&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;integrated common rams into processor&lt;/div&gt;~ /trunk/src/sxp.v&lt;br /&gt;</description>
            <author>samg</author>
            <pubDate>Fri, 09 Nov 2001 00:45:59 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=sxp&amp;path=%2F&amp;rev=43</guid>
        </item>
        <item>
            <title>minor header correction</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=sxp&amp;path=%2F&amp;rev=42</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 42 - samg&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;minor header correction&lt;/div&gt;~ /trunk/sim/test_sxp.v&lt;br /&gt;</description>
            <author>samg</author>
            <pubDate>Fri, 09 Nov 2001 00:38:10 +0100</pubDate>
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