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            <description>&lt;div&gt;&lt;strong&gt;Rev 49 - root&lt;/strong&gt; (5 file(s) modified)&lt;/div&gt;&lt;div&gt;Added old uploaded documents to new repository.&lt;/div&gt;- /t80/web_uploads/oc_checkin.sh&lt;br /&gt;- /t80/web_uploads/oc_cvs_checkin.sh&lt;br /&gt;- /t80/web_uploads/svn_checkin.log&lt;br /&gt;- /t80/web_uploads/svn_checkin.sh&lt;br /&gt;- /t80/web_uploads/temp.sh&lt;br /&gt;</description>
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            <description>&lt;div&gt;&lt;strong&gt;Rev 48 - root&lt;/strong&gt; (5 file(s) modified)&lt;/div&gt;&lt;div&gt;Added old uploaded documents to new repository.&lt;/div&gt;+ /t80/web_uploads/oc_checkin.sh&lt;br /&gt;+ /t80/web_uploads/oc_cvs_checkin.sh&lt;br /&gt;+ /t80/web_uploads/svn_checkin.log&lt;br /&gt;+ /t80/web_uploads/svn_checkin.sh&lt;br /&gt;+ /t80/web_uploads/temp.sh&lt;br /&gt;</description>
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            <description>&lt;div&gt;&lt;strong&gt;Rev 46 - andreas&lt;/strong&gt; (3 file(s) modified)&lt;/div&gt;&lt;div&gt;Made some bugfixes&lt;/div&gt;~ /trunk/rtl/vhdl/SSRAM.vhd&lt;br /&gt;~ /trunk/rtl/vhdl/SSRAM2.vhd&lt;br /&gt;~ /trunk/rtl/vhdl/SSRAMX.vhd&lt;br /&gt;</description>
            <author>andreas</author>
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            <description>&lt;div&gt;&lt;strong&gt;Rev 45 - jesus&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;Fixed loopback break generation&lt;/div&gt;~ /trunk/rtl/vhdl/T16450.vhd&lt;br /&gt;</description>
            <author>jesus</author>
            <pubDate>Tue, 03 Dec 2002 14:44:51 +0100</pubDate>
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            <description>&lt;div&gt;&lt;strong&gt;Rev 44 - jesus&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;Added some missing features and fixed baud rate generator&lt;/div&gt;~ /trunk/rtl/vhdl/T16450.vhd&lt;br /&gt;</description>
            <author>jesus</author>
            <pubDate>Tue, 03 Dec 2002 01:32:24 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=t80&amp;path=%2F&amp;rev=44</guid>
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            <description>&lt;div&gt;&lt;strong&gt;Rev 43 - jesus&lt;/strong&gt; (5 file(s) modified)&lt;/div&gt;&lt;div&gt;*** empty log message ***&lt;/div&gt;~ /trunk/bench/vhdl/SRAM.vhd&lt;br /&gt;~ /trunk/sim/rtl_sim/bin/compile.do&lt;br /&gt;~ /trunk/syn/xilinx/bin/t80.tcl&lt;br /&gt;~ /trunk/syn/xilinx/bin/t80debug.tcl&lt;br /&gt;~ /trunk/syn/xilinx/bin/t80debugxr.tcl&lt;br /&gt;</description>
            <author>jesus</author>
            <pubDate>Sun, 24 Nov 2002 13:58:31 +0100</pubDate>
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            <title>Fixed bus req/ack cycle</title>
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            <description>&lt;div&gt;&lt;strong&gt;Rev 42 - jesus&lt;/strong&gt; (2 file(s) modified)&lt;/div&gt;&lt;div&gt;Fixed bus req/ack cycle&lt;/div&gt;~ /trunk/rtl/vhdl/T80.vhd&lt;br /&gt;~ /trunk/rtl/vhdl/T80a.vhd&lt;br /&gt;</description>
            <author>jesus</author>
            <pubDate>Sun, 24 Nov 2002 13:51:28 +0100</pubDate>
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            <title>Removed UNISIM library</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=t80&amp;path=%2F&amp;rev=41</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 41 - jesus&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;Removed UNISIM library&lt;/div&gt;~ /trunk/rtl/vhdl/SSRAMX.vhd&lt;br /&gt;</description>
            <author>jesus</author>
            <pubDate>Sun, 24 Nov 2002 13:50:30 +0100</pubDate>
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            <description>&lt;div&gt;&lt;strong&gt;Rev 40 - jesus&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;Cleanup&lt;/div&gt;~ /trunk/rtl/vhdl/T80_ALU.vhd&lt;br /&gt;</description>
            <author>jesus</author>
            <pubDate>Sun, 24 Nov 2002 13:43:51 +0100</pubDate>
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            <link>https://opencores.org/websvn//websvn/revision?repname=t80&amp;path=%2F&amp;rev=39</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 39 - jesus&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;Added -n option and component declaration&lt;/div&gt;~ /trunk/sw/xrom.cpp&lt;br /&gt;</description>
            <author>jesus</author>
            <pubDate>Sun, 27 Oct 2002 16:28:25 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=t80&amp;path=%2F&amp;rev=39</guid>
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            <title>Added Leonardo .ucf generation</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=t80&amp;path=%2F&amp;rev=38</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 38 - jesus&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;Added Leonardo .ucf generation&lt;/div&gt;~ /trunk/sw/hex2rom.cpp&lt;br /&gt;</description>
            <author>jesus</author>
            <pubDate>Sun, 27 Oct 2002 16:27:21 +0100</pubDate>
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            <link>https://opencores.org/websvn//websvn/revision?repname=t80&amp;path=%2F&amp;rev=37</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 37 - jesus&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;Changed to single register file&lt;/div&gt;~ /trunk/rtl/vhdl/T80_Reg.vhd&lt;br /&gt;</description>
            <author>jesus</author>
            <pubDate>Sun, 27 Oct 2002 13:31:15 +0100</pubDate>
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            <title>Added component declaration</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=t80&amp;path=%2F&amp;rev=36</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 36 - jesus&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;Added component declaration&lt;/div&gt;~ /trunk/rtl/vhdl/T80_RegX.vhd&lt;br /&gt;</description>
            <author>jesus</author>
            <pubDate>Sun, 27 Oct 2002 13:27:07 +0100</pubDate>
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            <description>&lt;div&gt;&lt;strong&gt;Rev 35 - jesus&lt;/strong&gt; (22 file(s) modified)&lt;/div&gt;&lt;div&gt;Release 0242&lt;/div&gt;~ /trunk/rtl/vhdl/DebugSystem.vhd&lt;br /&gt;~ /trunk/rtl/vhdl/DebugSystemXR.vhd&lt;br /&gt;~ /trunk/rtl/vhdl/T80.vhd&lt;br /&gt;~ /trunk/rtl/vhdl/T80a.vhd&lt;br /&gt;~ /trunk/rtl/vhdl/T80s.vhd&lt;br /&gt;~ /trunk/rtl/vhdl/T80se.vhd&lt;br /&gt;~ /trunk/rtl/vhdl/T80_ALU.vhd&lt;br /&gt;~ /trunk/rtl/vhdl/T80_MCode.vhd&lt;br /&gt;~ /trunk/rtl/vhdl/T80_Pack.vhd&lt;br /&gt;+ /trunk/rtl/vhdl/T80_Reg.vhd&lt;br /&gt;+ /trunk/rtl/vhdl/T80_RegX.vhd&lt;br /&gt;~ /trunk/rtl/vhdl/T8080se.vhd&lt;br /&gt;~ /trunk/sim/rtl_sim/bin/compile.do&lt;br /&gt;~ /trunk/syn/xilinx/bin/t80.prj&lt;br /&gt;~ /trunk/syn/xilinx/bin/t80.tcl&lt;br /&gt;~ /trunk/syn/xilinx/bin/t80debug.prj&lt;br /&gt;~ /trunk/syn/xilinx/bin/t80debug.tcl&lt;br /&gt;~ /trunk/syn/xilinx/bin/t80debugxr.prj&lt;br /&gt;~ /trunk/syn/xilinx/bin/t80debugxr.tcl&lt;br /&gt;~ /trunk/syn/xilinx/run/t80.bat&lt;br /&gt;~ /trunk/syn/xilinx/run/t80debug.bat&lt;br /&gt;~ /trunk/syn/xilinx/run/t80debugxr.bat&lt;br /&gt;</description>
            <author>jesus</author>
            <pubDate>Mon, 21 Oct 2002 01:36:55 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=t80&amp;path=%2F&amp;rev=35</guid>
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        <item>
            <title>Updated for ISE 5.1</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=t80&amp;path=%2F&amp;rev=34</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 34 - jesus&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;Updated for ISE 5.1&lt;/div&gt;~ /trunk/rtl/vhdl/SSRAMX.vhd&lt;br /&gt;</description>
            <author>jesus</author>
            <pubDate>Sun, 20 Oct 2002 20:20:33 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=t80&amp;path=%2F&amp;rev=34</guid>
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        <item>
            <title>Fixed typo</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=t80&amp;path=%2F&amp;rev=33</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 33 - jesus&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;Fixed typo&lt;/div&gt;~ /trunk/sw/xrom.cpp&lt;br /&gt;</description>
            <author>jesus</author>
            <pubDate>Fri, 11 Oct 2002 04:29:14 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=t80&amp;path=%2F&amp;rev=33</guid>
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        <item>
            <title>Fixed for ISE 5.1</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=t80&amp;path=%2F&amp;rev=32</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 32 - jesus&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;Fixed for ISE 5.1&lt;/div&gt;~ /trunk/sw/xrom.cpp&lt;br /&gt;</description>
            <author>jesus</author>
            <pubDate>Fri, 11 Oct 2002 04:27:30 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=t80&amp;path=%2F&amp;rev=32</guid>
        </item>
        <item>
            <title>Fixed generic name error</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=t80&amp;path=%2F&amp;rev=31</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 31 - jesus&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;Fixed generic name error&lt;/div&gt;~ /trunk/bench/vhdl/SRAM.vhd&lt;br /&gt;</description>
            <author>jesus</author>
            <pubDate>Tue, 08 Oct 2002 02:32:39 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=t80&amp;path=%2F&amp;rev=31</guid>
        </item>
        <item>
            <title>Changed to xilinx specific RAM</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=t80&amp;path=%2F&amp;rev=30</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 30 - jesus&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;Changed to xilinx specific RAM&lt;/div&gt;~ /trunk/syn/xilinx/bin/t80debug.prj&lt;br /&gt;</description>
            <author>jesus</author>
            <pubDate>Wed, 02 Oct 2002 02:46:08 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=t80&amp;path=%2F&amp;rev=30</guid>
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