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8051 WebSVN RSS feed - 8051 https://opencores.org/websvn//websvn/listing?repname=8051&path=%2F8051%2Ftrunk%2Frtl%2Fverilog%2Foc8051_divide.v& Sun, 28 Jun 2026 20:11:56 +0100 FeedCreator 1.7.2 ... https://opencores.org/websvn//websvn/revision?repname=8051&path=%2F8051%2Ftrunk%2Frtl%2Fverilog%2F&rev=186 <div>Rev 186 - root (2 file(s) modified)</div><div>...</div>+ /8051 - /oc8051 root Tue, 05 May 2009 15:18:06 +0100 https://opencores.org/websvn//websvn/revision?repname=8051&path=%2F8051%2Ftrunk%2Frtl%2Fverilog%2F&rev=186 ... https://opencores.org/websvn//websvn/revision?repname=8051&path=%2F8051%2Ftrunk%2Frtl%2Fverilog%2F&rev=185 <div>Rev 185 - root (9 file(s) modified)</div><div>...</div>- /branches + /oc8051 + /oc8051/branches + /oc8051/tags + /oc8051/trunk + /oc8051/web_uploads + /oc8051/web_uploads/interface.jpg - /tags - /trunk root Tue, 10 Mar 2009 14:04:21 +0100 https://opencores.org/websvn//websvn/revision?repname=8051&path=%2F8051%2Ftrunk%2Frtl%2Fverilog%2F&rev=185 updating... https://opencores.org/websvn//websvn/revision?repname=8051&path=%2F8051%2Ftrunk%2Frtl%2Fverilog%2F&rev=95 <div>Rev 95 - simont (5 file(s) modified)</div><div>updating...</div>~ /trunk/rtl/verilog/oc8051_comp.v ~ /trunk/rtl/verilog/oc8051_cy_select.v ~ /trunk/rtl/verilog/oc8051_divide.v ~ /trunk/rtl/verilog/oc8051_multiply.v ~ /trunk/rtl/verilog/oc8051_ram_top.v simont Wed, 02 Apr 2003 11:26:21 +0100 https://opencores.org/websvn//websvn/revision?repname=8051&path=%2F8051%2Ftrunk%2Frtl%2Fverilog%2F&rev=95 prepared header https://opencores.org/websvn//websvn/revision?repname=8051&path=%2F8051%2Ftrunk%2Frtl%2Fverilog%2F&rev=45 <div>Rev 45 - simont (2 file(s) modified)</div><div>prepared header</div>~ /trunk/rtl/verilog/oc8051_divide.v ~ /trunk/rtl/verilog/oc8051_pc.v simont Mon, 30 Sep 2002 17:17:37 +0100 https://opencores.org/websvn//websvn/revision?repname=8051&path=%2F8051%2Ftrunk%2Frtl%2Fverilog%2F&rev=45 fix some bugs https://opencores.org/websvn//websvn/revision?repname=8051&path=%2F8051%2Ftrunk%2Frtl%2Fverilog%2F&rev=29 <div>Rev 29 - simont (1 file(s) modified)</div><div>fix some bugs</div>~ /trunk/rtl/verilog/oc8051_divide.v simont Fri, 23 Aug 2002 11:21:22 +0100 https://opencores.org/websvn//websvn/revision?repname=8051&path=%2F8051%2Ftrunk%2Frtl%2Fverilog%2F&rev=29 main divider logic was optimized not optimized by compiler, so ... https://opencores.org/websvn//websvn/revision?repname=8051&path=%2F8051%2Ftrunk%2Frtl%2Fverilog%2F&rev=26 <div>Rev 26 - markom (2 file(s) modified)</div><div>main divider logic was optimized not optimized by compiler, so ...</div>~ /trunk/rtl/verilog/oc8051_divide.v ~ /trunk/rtl/verilog/oc8051_top.v markom Fri, 23 Aug 2002 09:08:55 +0100 https://opencores.org/websvn//websvn/revision?repname=8051&path=%2F8051%2Ftrunk%2Frtl%2Fverilog%2F&rev=26 divider and multiplier pass test https://opencores.org/websvn//websvn/revision?repname=8051&path=%2F8051%2Ftrunk%2Frtl%2Fverilog%2F&rev=25 <div>Rev 25 - markom (2 file(s) modified)</div><div>divider and multiplier pass test</div>~ /trunk/rtl/verilog/oc8051_divide.v ~ /trunk/rtl/verilog/oc8051_multiply.v markom Thu, 22 Aug 2002 14:38:41 +0100 https://opencores.org/websvn//websvn/revision?repname=8051&path=%2F8051%2Ftrunk%2Frtl%2Fverilog%2F&rev=25 multiplier and divider changed so they complete in 4 cycles https://opencores.org/websvn//websvn/revision?repname=8051&path=%2F8051%2Ftrunk%2Frtl%2Fverilog%2F&rev=20 <div>Rev 20 - markom (3 file(s) modified)</div><div>multiplier and divider changed so they complete in 4 cycles</div>~ /trunk/rtl/verilog/oc8051_decoder.v ~ /trunk/rtl/verilog/oc8051_divide.v ~ /trunk/rtl/verilog/oc8051_multiply.v markom Wed, 21 Aug 2002 11:44:35 +0100 https://opencores.org/websvn//websvn/revision?repname=8051&path=%2F8051%2Ftrunk%2Frtl%2Fverilog%2F&rev=20 more linter corrections; 2 tests still fail https://opencores.org/websvn//websvn/revision?repname=8051&path=%2F8051%2Ftrunk%2Frtl%2Fverilog%2F&rev=5 <div>Rev 5 - markom (16 file(s) modified)</div><div>more linter corrections; 2 tests still fail</div>~ /trunk/rtl/verilog/oc8051_acc.v ~ /trunk/rtl/verilog/oc8051_alu.v ~ /trunk/rtl/verilog/oc8051_alu_src1_sel.v ~ /trunk/rtl/verilog/oc8051_b_register.v ~ /trunk/rtl/verilog/oc8051_decoder.v ~ /trunk/rtl/verilog/oc8051_divide.v ~ /trunk/rtl/verilog/oc8051_indi_addr.v ~ /trunk/rtl/verilog/oc8051_multiply.v ~ /trunk/rtl/verilog/oc8051_pc.v ~ /trunk/rtl/verilog/oc8051_ports.v ~ /trunk/rtl/verilog/oc8051_psw.v ~ /trunk/rtl/verilog/oc8051_ram_rd_sel.v ~ /trunk/rtl/verilog/oc8051_ram_sel.v ~ /trunk/rtl/verilog/oc8051_rom_addr_sel.v ~ /trunk/rtl/verilog/oc8051_top.v ~ /trunk/rtl/verilog/oc8051_uart.v markom Wed, 14 Aug 2002 12:57:13 +0100 https://opencores.org/websvn//websvn/revision?repname=8051&path=%2F8051%2Ftrunk%2Frtl%2Fverilog%2F&rev=5 Code repaired to satisfy the linter; testbech fails https://opencores.org/websvn//websvn/revision?repname=8051&path=%2F8051%2Ftrunk%2Frtl%2Fverilog%2F&rev=4 <div>Rev 4 - markom (51 file(s) modified)</div><div>Code repaired to satisfy the linter; testbech fails</div>~ /trunk/bench/verilog/oc8051_tb.v ~ /trunk/rtl/verilog/oc8051_acc.v ~ /trunk/rtl/verilog/oc8051_alu.v ~ /trunk/rtl/verilog/oc8051_alu_src1_sel.v ~ /trunk/rtl/verilog/oc8051_alu_src3_sel.v ~ /trunk/rtl/verilog/oc8051_b_register.v ~ /trunk/rtl/verilog/oc8051_decoder.v ~ /trunk/rtl/verilog/oc8051_divide.v ~ /trunk/rtl/verilog/oc8051_ext_addr_sel.v ~ /trunk/rtl/verilog/oc8051_indi_addr.v ~ /trunk/rtl/verilog/oc8051_int.v ~ /trunk/rtl/verilog/oc8051_multiply.v ~ /trunk/rtl/verilog/oc8051_op_select.v ~ /trunk/rtl/verilog/oc8051_pc.v ~ /trunk/rtl/verilog/oc8051_ports.v ~ /trunk/rtl/verilog/oc8051_psw.v ~ /trunk/rtl/verilog/oc8051_ram_rd_sel.v ~ /trunk/rtl/verilog/oc8051_ram_sel.v ~ /trunk/rtl/verilog/oc8051_ram_top.v ~ /trunk/rtl/verilog/oc8051_ram_wr_sel.v ~ /trunk/rtl/verilog/oc8051_reg1.v ~ /trunk/rtl/verilog/oc8051_reg2.v ~ /trunk/rtl/verilog/oc8051_reg3.v ~ /trunk/rtl/verilog/oc8051_reg4.v ~ /trunk/rtl/verilog/oc8051_reg8.v ~ /trunk/rtl/verilog/oc8051_rom_addr_sel.v ~ /trunk/rtl/verilog/oc8051_sp.v - /trunk/rtl/verilog/oc8051_tb.v ~ /trunk/rtl/verilog/oc8051_tc.v ~ /trunk/rtl/verilog/oc8051_top.v ~ /trunk/rtl/verilog/oc8051_uart.v ~ /trunk/sim/rtl_sim/out/cast.out ~ /trunk/sim/rtl_sim/out/counter_test.out ~ /trunk/sim/rtl_sim/out/div16u.out ~ /trunk/sim/rtl_sim/out/divmul.out ~ /trunk/sim/rtl_sim/out/fib.out ~ /trunk/sim/rtl_sim/out/gcd.out ~ /trunk/sim/rtl_sim/out/int2bin.out ~ /trunk/sim/rtl_sim/out/interrupt_test.out ~ /trunk/sim/rtl_sim/out/lcall.out ~ /trunk/sim/rtl_sim/out/ncelab.out ~ /trunk/sim/rtl_sim/out/negcnt.out ~ /trunk/sim/rtl_sim/out/r_bank.out ~ /trunk/sim/rtl_sim/out/serial_test.out ~ /trunk/sim/rtl_sim/out/sort.out ~ /trunk/sim/rtl_sim/out/sqroot.out ~ /trunk/sim/rtl_sim/out/testall.out ~ /trunk/sim/rtl_sim/out/timer_test.out ~ /trunk/sim/rtl_sim/out/xram_m.out ~ /trunk/sim/rtl_sim/run/verilog.log ~ /trunk/sim/rtl_sim/src/verilog/oc8051_uart_test.v markom Wed, 14 Aug 2002 11:16:20 +0100 https://opencores.org/websvn//websvn/revision?repname=8051&path=%2F8051%2Ftrunk%2Frtl%2Fverilog%2F&rev=4 Initial CVS import https://opencores.org/websvn//websvn/revision?repname=8051&path=%2F8051%2Ftrunk%2Frtl%2Fverilog%2F&rev=2 <div>Rev 2 - simont (239 file(s) modified)</div><div>Initial CVS import</div>+ /trunk/.nclaunch.dd + /trunk/asm + /trunk/asm/cast.c + /trunk/asm/counter_test.asm + /trunk/asm/DIV16U.asm + /trunk/asm/divmul.c + /trunk/asm/fib.c + /trunk/asm/gcd.c + /trunk/asm/hex + /trunk/asm/hex/cast.hex + /trunk/asm/hex/counter_test.hex + /trunk/asm/hex/div16u.hex + /trunk/asm/hex/divmul.hex + /trunk/asm/hex/fib.hex + /trunk/asm/hex/gcd.hex + /trunk/asm/hex/int2bin.hex + /trunk/asm/hex/interrupt_test.hex + /trunk/asm/hex/lcall.hex + /trunk/asm/hex/negcnt.hex + /trunk/asm/hex/r_bank.hex + /trunk/asm/hex/serial.hex + /trunk/asm/hex/serial_test.hex + /trunk/asm/hex/sort.hex + /trunk/asm/hex/sqroot.hex + /trunk/asm/hex/testall.hex + /trunk/asm/hex/timer.hex + /trunk/asm/hex/timer_test.hex + /trunk/asm/hex/xram.hex + /trunk/asm/hex/xram_m.ihx + /trunk/asm/in + /trunk/asm/in/cast.in + /trunk/asm/in/counter_test.in + /trunk/asm/in/div16u.in + /trunk/asm/in/divmul.in + /trunk/asm/in/fib.in + /trunk/asm/in/gcd.in + /trunk/asm/in/int2bin.in + /trunk/asm/in/interrupt_test.in + /trunk/asm/in/lcall.in + /trunk/asm/in/negcnt.in + /trunk/asm/in/r_bank.in + /trunk/asm/in/serial.in + /trunk/asm/in/serial_test.in + /trunk/asm/in/sort.in + /trunk/asm/in/sqroot.in + /trunk/asm/in/testall.in + /trunk/asm/in/timer.in + /trunk/asm/in/timer_test.in + /trunk/asm/in/xram.in + /trunk/asm/in/xram_m.in + /trunk/asm/int2bin.c + /trunk/asm/interrupt_test.asm + /trunk/asm/lcall.asm + /trunk/asm/negcnt.c + /trunk/asm/r_bank.asm + /trunk/asm/serial.asm + /trunk/asm/serial_test.asm + /trunk/asm/sort.c + /trunk/asm/sqroot.c + /trunk/asm/test.asm + /trunk/asm/testall.c + /trunk/asm/timer.asm + /trunk/asm/timer_test.asm + /trunk/asm/v + /trunk/asm/v/cast.v + /trunk/asm/v/counter_test.v + /trunk/asm/v/div16u.v + /trunk/asm/v/divmul.v + /trunk/asm/v/fib.v + /trunk/asm/v/gcd.v + /trunk/asm/v/int2bin.v + /trunk/asm/v/interrupt_test.v + /trunk/asm/v/lcall.v + /trunk/asm/v/negcnt.v + /trunk/asm/v/r_bank.v + /trunk/asm/v/serial.v + /trunk/asm/v/serial_test.v + /trunk/asm/v/sort.v + /trunk/asm/v/sqroot.v + /trunk/asm/v/testall.v + /trunk/asm/v/timer.v + /trunk/asm/v/timer_test.v + /trunk/asm/v/xram.v + /trunk/asm/v/xram_m.v + /trunk/asm/vec + /trunk/asm/vec/cast.vec + /trunk/asm/vec/counter_test.vec + /trunk/asm/vec/div16u.vec + /trunk/asm/vec/divmul.vec + /trunk/asm/vec/fib.vec + /trunk/asm/vec/gcd.vec + /trunk/asm/vec/int2bin.vec + /trunk/asm/vec/interrupt_test.vec + /trunk/asm/vec/lcall.vec + /trunk/asm/vec/negcnt.vec + /trunk/asm/vec/r_bank.vec + /trunk/asm/vec/serial.vec + /trunk/asm/vec/serial_test.vec + /trunk/asm/vec/sort.vec + /trunk/asm/vec/sqroot.vec + /trunk/asm/vec/testall.vec + /trunk/asm/vec/timer.vec + /trunk/asm/vec/timer_test.vec + /trunk/asm/vec/xram_m.vec + /trunk/asm/xram.c + /trunk/asm/xram_m.c + /trunk/bench + /trunk/bench/verilog + /trunk/bench/verilog/oc8051_fpga_tb.v + /trunk/bench/verilog/oc8051_tb.v + /trunk/bench/verilog/oc8051_timescale.v + /trunk/rtl + /trunk/rtl/verilog + /trunk/rtl/verilog/oc8051_acc.v + /trunk/rtl/verilog/oc8051_alu.v + /trunk/rtl/verilog/oc8051_alu_src1_sel.v + /trunk/rtl/verilog/oc8051_alu_src2_sel.v + /trunk/rtl/verilog/oc8051_alu_src3_sel.v + /trunk/rtl/verilog/oc8051_b_register.v + /trunk/rtl/verilog/oc8051_comp.v + /trunk/rtl/verilog/oc8051_cy_select.v + /trunk/rtl/verilog/oc8051_decoder.v + /trunk/rtl/verilog/oc8051_defines.v + /trunk/rtl/verilog/oc8051_divide.v + /trunk/rtl/verilog/oc8051_dptr.v + /trunk/rtl/verilog/oc8051_ext_addr_sel.v + /trunk/rtl/verilog/oc8051_fpga_top.v + /trunk/rtl/verilog/oc8051_immediate_sel.v + /trunk/rtl/verilog/oc8051_indi_addr.v + /trunk/rtl/verilog/oc8051_int.v + /trunk/rtl/verilog/oc8051_multiply.v + /trunk/rtl/verilog/oc8051_op_select.v + /trunk/rtl/verilog/oc8051_pc.v + /trunk/rtl/verilog/oc8051_ports.v + /trunk/rtl/verilog/oc8051_psw.v + /trunk/rtl/verilog/oc8051_ram_rd_sel.v + /trunk/rtl/verilog/oc8051_ram_sel.v + /trunk/rtl/verilog/oc8051_ram_top.v + /trunk/rtl/verilog/oc8051_ram_wr_sel.v + /trunk/rtl/verilog/oc8051_reg1.v + /trunk/rtl/verilog/oc8051_reg2.v + /trunk/rtl/verilog/oc8051_reg3.v + /trunk/rtl/verilog/oc8051_reg4.v + /trunk/rtl/verilog/oc8051_reg8.v + /trunk/rtl/verilog/oc8051_rom_addr_sel.v + /trunk/rtl/verilog/oc8051_sp.v + /trunk/rtl/verilog/oc8051_tb.v + /trunk/rtl/verilog/oc8051_tc.v + /trunk/rtl/verilog/oc8051_timescale.v + /trunk/rtl/verilog/oc8051_top.v + /trunk/rtl/verilog/oc8051_uart.v + /trunk/rtl/verilog/read.me + /trunk/sim + /trunk/sim/rtl_sim + /trunk/sim/rtl_sim/out + /trunk/sim/rtl_sim/out/cast.out + /trunk/sim/rtl_sim/out/counter_test.out + /trunk/sim/rtl_sim/out/div16u.out + /trunk/sim/rtl_sim/out/divmul.out + /trunk/sim/rtl_sim/out/fib.out + /trunk/sim/rtl_sim/out/gcd.out + /trunk/sim/rtl_sim/out/int2bin.out + /trunk/sim/rtl_sim/out/interrupt_test.out + /trunk/sim/rtl_sim/out/lcall.out + /trunk/sim/rtl_sim/out/ncelab.out + /trunk/sim/rtl_sim/out/ncprep.out + /trunk/sim/rtl_sim/out/ncvlog.out + /trunk/sim/rtl_sim/out/negcnt.out + /trunk/sim/rtl_sim/out/r_bank.out + /trunk/sim/rtl_sim/out/serial_test.out + /trunk/sim/rtl_sim/out/sort.out + /trunk/sim/rtl_sim/out/sqroot.out + /trunk/sim/rtl_sim/out/testall.out + /trunk/sim/rtl_sim/out/timer.out + /trunk/sim/rtl_sim/out/timer_test.out + /trunk/sim/rtl_sim/out/xram_m.out + /trunk/sim/rtl_sim/out/xrom_m.out + /trunk/sim/rtl_sim/run + /trunk/sim/rtl_sim/run/make + /trunk/sim/rtl_sim/run/make_fpga + /trunk/sim/rtl_sim/run/make_verilog + /trunk/sim/rtl_sim/run/oc8051_defines.v + /trunk/sim/rtl_sim/run/oc8051_timescale.v + /trunk/sim/rtl_sim/run/run + /trunk/sim/rtl_sim/run/verilog.log + /trunk/sim/rtl_sim/src + /trunk/sim/rtl_sim/src/cast.in + /trunk/sim/rtl_sim/src/cast.vec + /trunk/sim/rtl_sim/src/counter_test.in + /trunk/sim/rtl_sim/src/counter_test.vec + /trunk/sim/rtl_sim/src/div16u.in + /trunk/sim/rtl_sim/src/div16u.vec + /trunk/sim/rtl_sim/src/divmul.in + /trunk/sim/rtl_sim/src/divmul.vec + /trunk/sim/rtl_sim/src/fib.in + /trunk/sim/rtl_sim/src/fib.vec + /trunk/sim/rtl_sim/src/gcd.in + /trunk/sim/rtl_sim/src/gcd.vec + /trunk/sim/rtl_sim/src/int2bin.in + /trunk/sim/rtl_sim/src/int2bin.vec + /trunk/sim/rtl_sim/src/interrupt_test.asm + /trunk/sim/rtl_sim/src/interrupt_test.in + /trunk/sim/rtl_sim/src/interrupt_test.vec + /trunk/sim/rtl_sim/src/lcall.in + /trunk/sim/rtl_sim/src/lcall.vec + /trunk/sim/rtl_sim/src/negcnt.in + /trunk/sim/rtl_sim/src/negcnt.vec + /trunk/sim/rtl_sim/src/oc8051_rom.in + /trunk/sim/rtl_sim/src/oc8051_test.vec + /trunk/sim/rtl_sim/src/r_bank.in + /trunk/sim/rtl_sim/src/r_bank.vec + /trunk/sim/rtl_sim/src/serial.vec + /trunk/sim/rtl_sim/src/serial_test.in + /trunk/sim/rtl_sim/src/serial_test.vec + /trunk/sim/rtl_sim/src/sort.in + /trunk/sim/rtl_sim/src/sort.vec + /trunk/sim/rtl_sim/src/sqroot.in + /trunk/sim/rtl_sim/src/sqroot.vec + /trunk/sim/rtl_sim/src/testall.in + /trunk/sim/rtl_sim/src/testall.vec + /trunk/sim/rtl_sim/src/timer_test.in + /trunk/sim/rtl_sim/src/timer_test.vec + /trunk/sim/rtl_sim/src/verilog + /trunk/sim/rtl_sim/src/verilog/oc8051_ram.v + /trunk/sim/rtl_sim/src/verilog/oc8051_rom.v + /trunk/sim/rtl_sim/src/verilog/oc8051_rom_fpga.v + /trunk/sim/rtl_sim/src/verilog/oc8051_timescale.v + /trunk/sim/rtl_sim/src/verilog/oc8051_uart_test.v + /trunk/sim/rtl_sim/src/verilog/oc8051_xram.v + /trunk/sim/rtl_sim/src/xram_m.in + /trunk/sim/rtl_sim/src/xram_m.vec + /trunk/syn + /trunk/syn/src + /trunk/syn/src/verilog + /trunk/syn/src/verilog/disp.v + /trunk/syn/src/verilog/oc8051_fpga_top.v + /trunk/syn/src/verilog/oc8051_ram.v + /trunk/syn/src/verilog/oc8051_rom.v + /trunk/syn/src/verilog/read.me simont Mon, 29 Jul 2002 13:33:18 +0100 https://opencores.org/websvn//websvn/revision?repname=8051&path=%2F8051%2Ftrunk%2Frtl%2Fverilog%2F&rev=2

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