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ion WebSVN RSS feed - ion https://opencores.org/websvn//websvn/listing?repname=ion&path=%2Fion%2Ftrunk%2Fvhdl%2Fmips_cpu.vhdl& Sat, 26 Sep 2026 23:58:18 +0100 FeedCreator 1.7.2 CPU interrupt input changed to 8-bit vector Other modules changed accordingly Interrupts ... https://opencores.org/websvn//websvn/revision?repname=ion&path=%2Fion%2Ftrunk%2Fvhdl%2F&rev=200 <div><strong>Rev 200 - ja_rd</strong> (4 file(s) modified)</div><div>CPU interrupt input changed to 8-bit vector<br /> Other modules changed accordingly<br /> Interrupts ...</div>~ /ion/trunk/vhdl/demo/c2sb_demo.vhdl<br />~ /ion/trunk/vhdl/demo/mips_mpu.vhdl<br />~ /ion/trunk/vhdl/mips_cpu.vhdl<br />~ /ion/trunk/vhdl/tb/mips_tb.vhdl<br /> ja_rd Sun, 31 Jul 2011 13:22:58 +0100 https://opencores.org/websvn//websvn/revision?repname=ion&path=%2Fion%2Ftrunk%2Fvhdl%2F&rev=200 CPU bug fix: MFC0 instructions aborted by privilege trap should ... https://opencores.org/websvn//websvn/revision?repname=ion&path=%2Fion%2Ftrunk%2Fvhdl%2F&rev=171 <div><strong>Rev 171 - ja_rd</strong> (1 file(s) modified)</div><div>CPU bug fix: MFC0 instructions aborted by privilege trap should ...</div>~ /ion/trunk/vhdl/mips_cpu.vhdl<br /> ja_rd Thu, 16 Jun 2011 03:25:47 +0100 https://opencores.org/websvn//websvn/revision?repname=ion&path=%2Fion%2Ftrunk%2Fvhdl%2F&rev=171 Fixed stupid mistake in headers (date of project) https://opencores.org/websvn//websvn/revision?repname=ion&path=%2Fion%2Ftrunk%2Fvhdl%2F&rev=162 <div><strong>Rev 162 - ja_rd</strong> (12 file(s) modified)</div><div>Fixed stupid mistake in headers (date of project)</div>~ /ion/trunk/src/mips_mpu1_template.vhdl<br />~ /ion/trunk/src/mips_tb0_template.vhdl<br />~ /ion/trunk/src/mips_tb2_template.vhdl<br />~ /ion/trunk/vhdl/demo/c2sb_demo.vhdl<br />~ /ion/trunk/vhdl/demo/rs232_rx.vhdl<br />~ /ion/trunk/vhdl/demo/rs232_tx.vhdl<br />~ /ion/trunk/vhdl/mips_alu.vhdl<br />~ /ion/trunk/vhdl/mips_cache.vhdl<br />~ /ion/trunk/vhdl/mips_cpu.vhdl<br />~ /ion/trunk/vhdl/mips_pkg.vhdl<br />~ /ion/trunk/vhdl/mips_shifter.vhdl<br />~ /ion/trunk/vhdl/sdram_controller.vhdl<br /> ja_rd Thu, 09 Jun 2011 14:59:36 +0100 https://opencores.org/websvn//websvn/revision?repname=ion&path=%2Fion%2Ftrunk%2Fvhdl%2F&rev=162 Added GPL license info to the vhdl headers This project is ... https://opencores.org/websvn//websvn/revision?repname=ion&path=%2Fion%2Ftrunk%2Fvhdl%2F&rev=161 <div><strong>Rev 161 - ja_rd</strong> (12 file(s) modified)</div><div>Added GPL license info to the vhdl headers<br /> This project is ...</div>~ /ion/trunk/src/mips_mpu1_template.vhdl<br />~ /ion/trunk/src/mips_tb0_template.vhdl<br />~ /ion/trunk/src/mips_tb2_template.vhdl<br />~ /ion/trunk/vhdl/demo/c2sb_demo.vhdl<br />~ /ion/trunk/vhdl/demo/rs232_rx.vhdl<br />~ /ion/trunk/vhdl/demo/rs232_tx.vhdl<br />~ /ion/trunk/vhdl/mips_alu.vhdl<br />~ /ion/trunk/vhdl/mips_cache.vhdl<br />~ /ion/trunk/vhdl/mips_cpu.vhdl<br />~ /ion/trunk/vhdl/mips_pkg.vhdl<br />~ /ion/trunk/vhdl/mips_shifter.vhdl<br />~ /ion/trunk/vhdl/sdram_controller.vhdl<br /> ja_rd Thu, 09 Jun 2011 14:56:56 +0100 https://opencores.org/websvn//websvn/revision?repname=ion&path=%2Fion%2Ftrunk%2Fvhdl%2F&rev=161 bug detected but not fixed in cpu (1st instruction after entering ... https://opencores.org/websvn//websvn/revision?repname=ion&path=%2Fion%2Ftrunk%2Fvhdl%2F&rev=159 <div><strong>Rev 159 - ja_rd</strong> (1 file(s) modified)</div><div>bug detected but not fixed in cpu<br /> (1st instruction after entering ...</div>~ /ion/trunk/vhdl/mips_cpu.vhdl<br /> ja_rd Wed, 08 Jun 2011 06:14:34 +0100 https://opencores.org/websvn//websvn/revision?repname=ion&path=%2Fion%2Ftrunk%2Fvhdl%2F&rev=159 Bug fix in the missing coprocesor exception. The CPU was ... https://opencores.org/websvn//websvn/revision?repname=ion&path=%2Fion%2Ftrunk%2Fvhdl%2F&rev=157 <div><strong>Rev 157 - ja_rd</strong> (2 file(s) modified)</div><div>Bug fix in the missing coprocesor exception. <br /> The CPU was ...</div>~ /ion/trunk/vhdl/mips_cpu.vhdl<br />~ /ion/trunk/vhdl/tb/mips_tb_pkg.vhdl<br /> ja_rd Mon, 06 Jun 2011 20:20:07 +0100 https://opencores.org/websvn//websvn/revision?repname=ion&path=%2Fion%2Ftrunk%2Fvhdl%2F&rev=157 Added R3000 compatible support for kernel/user state: - Implemented KU/IE plus ... https://opencores.org/websvn//websvn/revision?repname=ion&path=%2Fion%2Ftrunk%2Fvhdl%2F&rev=153 <div><strong>Rev 153 - ja_rd</strong> (1 file(s) modified)</div><div>Added R3000 compatible support for kernel/user state:<br /> - Implemented KU/IE plus ...</div>~ /ion/trunk/vhdl/mips_cpu.vhdl<br /> ja_rd Mon, 06 Jun 2011 10:59:56 +0100 https://opencores.org/websvn//websvn/revision?repname=ion&path=%2Fion%2Ftrunk%2Fvhdl%2F&rev=153 BUG FIX in cpu: MTCx was using Rs as source ... https://opencores.org/websvn//websvn/revision?repname=ion&path=%2Fion%2Ftrunk%2Fvhdl%2F&rev=140 <div><strong>Rev 140 - ja_rd</strong> (1 file(s) modified)</div><div>BUG FIX in cpu: MTCx was using Rs as source ...</div>~ /ion/trunk/vhdl/mips_cpu.vhdl<br /> ja_rd Thu, 02 Jun 2011 06:51:11 +0100 https://opencores.org/websvn//websvn/revision?repname=ion&path=%2Fion%2Ftrunk%2Fvhdl%2F&rev=140 Fixed bug in stall logic (stall for back-to-back SW instructions was ... https://opencores.org/websvn//websvn/revision?repname=ion&path=%2Fion%2Ftrunk%2Fvhdl%2F&rev=132 <div><strong>Rev 132 - ja_rd</strong> (1 file(s) modified)</div><div>Fixed bug in stall logic<br /> (stall for back-to-back SW instructions was ...</div>~ /ion/trunk/vhdl/mips_cpu.vhdl<br /> ja_rd Sun, 29 May 2011 15:24:51 +0100 https://opencores.org/websvn//websvn/revision?repname=ion&path=%2Fion%2Ftrunk%2Fvhdl%2F&rev=132 CPU code reorganized a bit No new logic, just a few ... https://opencores.org/websvn//websvn/revision?repname=ion&path=%2Fion%2Ftrunk%2Fvhdl%2F&rev=121 <div><strong>Rev 121 - ja_rd</strong> (1 file(s) modified)</div><div>CPU code reorganized a bit<br /> No new logic, just a few ...</div>~ /ion/trunk/vhdl/mips_cpu.vhdl<br /> ja_rd Wed, 13 Apr 2011 15:22:10 +0100 https://opencores.org/websvn//websvn/revision?repname=ion&path=%2Fion%2Ftrunk%2Fvhdl%2F&rev=121 FIX: code_rd_vma asserted only after reset is done ADDED cache control ... https://opencores.org/websvn//websvn/revision?repname=ion&path=%2Fion%2Ftrunk%2Fvhdl%2F&rev=101 <div><strong>Rev 101 - ja_rd</strong> (1 file(s) modified)</div><div>FIX: code_rd_vma asserted only after reset is done<br /> ADDED cache control ...</div>~ /ion/trunk/vhdl/mips_cpu.vhdl<br /> ja_rd Sat, 26 Mar 2011 17:16:38 +0100 https://opencores.org/websvn//websvn/revision?repname=ion&path=%2Fion%2Ftrunk%2Fvhdl%2F&rev=101 CPU rd and wr data address buses unified https://opencores.org/websvn//websvn/revision?repname=ion&path=%2Fion%2Ftrunk%2Fvhdl%2F&rev=96 <div><strong>Rev 96 - ja_rd</strong> (3 file(s) modified)</div><div>CPU rd and wr data address buses unified</div>~ /ion/trunk/vhdl/mips_cache_stub.vhdl<br />~ /ion/trunk/vhdl/mips_cpu.vhdl<br />~ /ion/trunk/vhdl/tb/mips_tb_pkg.vhdl<br /> ja_rd Wed, 02 Mar 2011 08:03:42 +0100 https://opencores.org/websvn//websvn/revision?repname=ion&path=%2Fion%2Ftrunk%2Fvhdl%2F&rev=96 BUG FIX: LHU was not doing sign extension properly BUG FIX: ... https://opencores.org/websvn//websvn/revision?repname=ion&path=%2Fion%2Ftrunk%2Fvhdl%2F&rev=83 <div><strong>Rev 83 - ja_rd</strong> (1 file(s) modified)</div><div>BUG FIX: LHU was not doing sign extension properly<br /> BUG FIX: ...</div>~ /ion/trunk/vhdl/mips_cpu.vhdl<br /> ja_rd Sat, 19 Feb 2011 11:17:10 +0100 https://opencores.org/websvn//websvn/revision?repname=ion&path=%2Fion%2Ftrunk%2Fvhdl%2F&rev=83 CPU fixed: fixed bug in EPC load logic relative to mem_wait ... https://opencores.org/websvn//websvn/revision?repname=ion&path=%2Fion%2Ftrunk%2Fvhdl%2F&rev=62 <div><strong>Rev 62 - ja_rd</strong> (1 file(s) modified)</div><div>CPU fixed:<br /> fixed bug in EPC load logic relative to mem_wait ...</div>~ /ion/trunk/vhdl/mips_cpu.vhdl<br /> ja_rd Tue, 08 Feb 2011 21:20:48 +0100 https://opencores.org/websvn//websvn/revision?repname=ion&path=%2Fion%2Ftrunk%2Fvhdl%2F&rev=62 First version of cache: stub, 1-word cache Stub cache tested on ... https://opencores.org/websvn//websvn/revision?repname=ion&path=%2Fion%2Ftrunk%2Fvhdl%2F&rev=46 <div><strong>Rev 46 - ja_rd</strong> (4 file(s) modified)</div><div>First version of cache: stub, 1-word cache<br /> Stub cache tested on ...</div>~ /ion/trunk/vhdl/demo/c2sb_demo.vhdl<br />~ /ion/trunk/vhdl/demo/mips_mpu.vhdl<br />~ /ion/trunk/vhdl/mips_cache_stub.vhdl<br />~ /ion/trunk/vhdl/mips_cpu.vhdl<br /> ja_rd Sun, 06 Feb 2011 15:28:28 +0100 https://opencores.org/websvn//websvn/revision?repname=ion&path=%2Fion%2Ftrunk%2Fvhdl%2F&rev=46 CPU mem_wait logic updated to work with cache https://opencores.org/websvn//websvn/revision?repname=ion&path=%2Fion%2Ftrunk%2Fvhdl%2F&rev=35 <div><strong>Rev 35 - ja_rd</strong> (1 file(s) modified)</div><div>CPU mem_wait logic updated to work with cache</div>~ /ion/trunk/vhdl/mips_cpu.vhdl<br /> ja_rd Wed, 02 Feb 2011 12:09:49 +0100 https://opencores.org/websvn//websvn/revision?repname=ion&path=%2Fion%2Ftrunk%2Fvhdl%2F&rev=35 Completed decoding of instructions (to prevent side effects of invalid opcodes) https://opencores.org/websvn//websvn/revision?repname=ion&path=%2Fion%2Ftrunk%2Fvhdl%2F&rev=30 <div><strong>Rev 30 - ja_rd</strong> (1 file(s) modified)</div><div>Completed decoding of instructions<br /> (to prevent side effects of invalid opcodes)</div>~ /ion/trunk/vhdl/mips_cpu.vhdl<br /> ja_rd Mon, 31 Jan 2011 15:04:06 +0100 https://opencores.org/websvn//websvn/revision?repname=ion&path=%2Fion%2Ftrunk%2Fvhdl%2F&rev=30 Core updated: supports CP0 cause register and traps in delay ... https://opencores.org/websvn//websvn/revision?repname=ion&path=%2Fion%2Ftrunk%2Fvhdl%2F&rev=28 <div><strong>Rev 28 - ja_rd</strong> (1 file(s) modified)</div><div>Core updated: <br /> supports CP0 cause register and traps in delay ...</div>~ /ion/trunk/vhdl/mips_cpu.vhdl<br /> ja_rd Mon, 31 Jan 2011 13:49:29 +0100 https://opencores.org/websvn//websvn/revision?repname=ion&path=%2Fion%2Ftrunk%2Fvhdl%2F&rev=28 Unimplemented instruction are now trapped (barely tested) https://opencores.org/websvn//websvn/revision?repname=ion&path=%2Fion%2Ftrunk%2Fvhdl%2F&rev=23 <div><strong>Rev 23 - ja_rd</strong> (1 file(s) modified)</div><div>Unimplemented instruction are now trapped (barely tested)</div>~ /ion/trunk/vhdl/mips_cpu.vhdl<br /> ja_rd Mon, 31 Jan 2011 08:50:55 +0100 https://opencores.org/websvn//websvn/revision?repname=ion&path=%2Fion%2Ftrunk%2Fvhdl%2F&rev=23 FIXED killer bug in instruction decoder for beq & mfc0 Decoding ... https://opencores.org/websvn//websvn/revision?repname=ion&path=%2Fion%2Ftrunk%2Fvhdl%2F&rev=22 <div><strong>Rev 22 - ja_rd</strong> (1 file(s) modified)</div><div>FIXED killer bug in instruction decoder for beq & mfc0<br /> Decoding ...</div>~ /ion/trunk/vhdl/mips_cpu.vhdl<br /> ja_rd Sun, 30 Jan 2011 11:27:28 +0100 https://opencores.org/websvn//websvn/revision?repname=ion&path=%2Fion%2Ftrunk%2Fvhdl%2F&rev=22

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