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open8_urisc WebSVN RSS feed - open8_urisc https://opencores.org/websvn//websvn/listing?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2FOpen8_pkg.vhd& Mon, 18 May 2026 11:07:51 +0100 FeedCreator 1.7.2 Cleaned up comments, added back the OPEN8_NULLBUS constant, and added ... https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=191 <div><strong>Rev 191 - jshamlet</strong> (28 file(s) modified)</div><div>Cleaned up comments, added back the OPEN8_NULLBUS constant, and added ...</div>+ /open8_urisc/trunk/VHDL/button_db.vhd<br />~ /open8_urisc/trunk/VHDL/o8_alu16.vhd<br />~ /open8_urisc/trunk/VHDL/o8_btn_int.vhd<br />~ /open8_urisc/trunk/VHDL/o8_clk_detect.vhd<br />~ /open8_urisc/trunk/VHDL/o8_cpu.vhd<br />~ /open8_urisc/trunk/VHDL/o8_crc16_ccitt.vhd<br />~ /open8_urisc/trunk/VHDL/o8_datalatch.vhd<br />~ /open8_urisc/trunk/VHDL/o8_epoch_timer.vhd<br />~ /open8_urisc/trunk/VHDL/o8_gpin.vhd<br />~ /open8_urisc/trunk/VHDL/o8_gpio.vhd<br />~ /open8_urisc/trunk/VHDL/o8_gpout.vhd<br />~ /open8_urisc/trunk/VHDL/o8_hd44780_4b.vhd<br />~ /open8_urisc/trunk/VHDL/o8_hd44780_8b.vhd<br />+ /open8_urisc/trunk/VHDL/o8_ltc2355_2p.vhd<br />+ /open8_urisc/trunk/VHDL/o8_max7221.vhd<br />+ /open8_urisc/trunk/VHDL/o8_max7221_fifo.vhd<br />~ /open8_urisc/trunk/VHDL/o8_ram_1k.vhd<br />~ /open8_urisc/trunk/VHDL/o8_register.vhd<br />~ /open8_urisc/trunk/VHDL/o8_rom_32k.vhd<br />~ /open8_urisc/trunk/VHDL/o8_rtc.vhd<br />~ /open8_urisc/trunk/VHDL/o8_status_led.vhd<br />~ /open8_urisc/trunk/VHDL/o8_sys_timer.vhd<br />~ /open8_urisc/trunk/VHDL/o8_vdsm8.vhd<br />~ /open8_urisc/trunk/VHDL/o8_vdsm12.vhd<br />~ /open8_urisc/trunk/VHDL/Open8_pkg.vhd<br />+ /open8_urisc/trunk/VHDL/ram_1k_core.vhd<br />+ /open8_urisc/trunk/VHDL/rom_32k_core.vhd<br />+ /open8_urisc/trunk/VHDL/sdlc_crc16_ccitt.vhd<br /> jshamlet Tue, 31 Mar 2020 18:53:53 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=191 Merged changes from private repository, added ceil_log2 function to Open8_pkg, since ... https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=189 <div><strong>Rev 189 - jshamlet</strong> (11 file(s) modified)</div><div>Merged changes from private repository,<br /> added ceil_log2 function to Open8_pkg, since ...</div>~ /open8_urisc/trunk/VHDL/o8_btn_int.vhd<br />~ /open8_urisc/trunk/VHDL/o8_epoch_timer.vhd<br />~ /open8_urisc/trunk/VHDL/o8_gpin.vhd<br />~ /open8_urisc/trunk/VHDL/o8_hd44780_4b.vhd<br />~ /open8_urisc/trunk/VHDL/o8_hd44780_8b.vhd<br />~ /open8_urisc/trunk/VHDL/o8_rtc.vhd<br />~ /open8_urisc/trunk/VHDL/o8_status_led.vhd<br />~ /open8_urisc/trunk/VHDL/o8_sys_timer.vhd<br />~ /open8_urisc/trunk/VHDL/o8_vdsm8.vhd<br />~ /open8_urisc/trunk/VHDL/o8_vdsm12.vhd<br />~ /open8_urisc/trunk/VHDL/Open8_pkg.vhd<br /> jshamlet Wed, 18 Mar 2020 20:47:28 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=189 Added a generic to alter the behavior of RTI so ... https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=188 <div><strong>Rev 188 - jshamlet</strong> (2 file(s) modified)</div><div>Added a generic to alter the behavior of RTI so ...</div>~ /open8_urisc/trunk/VHDL/o8_cpu.vhd<br />~ /open8_urisc/trunk/VHDL/Open8_pkg.vhd<br /> jshamlet Wed, 18 Mar 2020 18:01:59 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=188 Added the CPU_Halt input, only now as an input to ... https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=187 <div><strong>Rev 187 - jshamlet</strong> (2 file(s) modified)</div><div>Added the CPU_Halt input, only now as an input to ...</div>~ /open8_urisc/trunk/VHDL/o8_cpu.vhd<br />~ /open8_urisc/trunk/VHDL/Open8_pkg.vhd<br /> jshamlet Mon, 16 Mar 2020 21:46:04 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=187 Merged the interrupt override logic into the case structure, simplifying ... https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=186 <div><strong>Rev 186 - jshamlet</strong> (2 file(s) modified)</div><div>Merged the interrupt override logic into the case structure, simplifying ...</div>~ /open8_urisc/trunk/VHDL/o8_cpu.vhd<br />~ /open8_urisc/trunk/VHDL/Open8_pkg.vhd<br /> jshamlet Fri, 13 Mar 2020 21:56:13 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=186 1) Fixed an apparently long-standing bug where the interrupt bit ... https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=185 <div><strong>Rev 185 - jshamlet</strong> (2 file(s) modified)</div><div>1) Fixed an apparently long-standing bug where the interrupt bit ...</div>~ /open8_urisc/trunk/VHDL/o8_cpu.vhd<br />~ /open8_urisc/trunk/VHDL/Open8_pkg.vhd<br /> jshamlet Fri, 13 Mar 2020 19:13:36 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=185 Renamed core to o8_cpu to match new naming scheme https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=183 <div><strong>Rev 183 - jshamlet</strong> (3 file(s) modified)</div><div>Renamed core to o8_cpu to match new naming scheme</div>+ /open8_urisc/trunk/VHDL/o8_cpu.vhd<br />- /open8_urisc/trunk/VHDL/Open8.vhd<br />~ /open8_urisc/trunk/VHDL/Open8_pkg.vhd<br /> jshamlet Wed, 11 Mar 2020 18:59:00 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=183 Simplified the address generation logic at the expense of making ... https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=182 <div><strong>Rev 182 - jshamlet</strong> (2 file(s) modified)</div><div>Simplified the address generation logic at the expense of making ...</div>~ /open8_urisc/trunk/VHDL/Open8.vhd<br />~ /open8_urisc/trunk/VHDL/Open8_pkg.vhd<br /> jshamlet Wed, 11 Mar 2020 18:56:40 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=182 Altered the RSP instruction to allow the stack pointed to ... https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=181 <div><strong>Rev 181 - jshamlet</strong> (2 file(s) modified)</div><div>Altered the RSP instruction to allow the stack pointed to ...</div>~ /open8_urisc/trunk/VHDL/Open8.vhd<br />~ /open8_urisc/trunk/VHDL/Open8_pkg.vhd<br /> jshamlet Tue, 10 Mar 2020 22:36:44 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=181 General code cleanup https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=172 <div><strong>Rev 172 - jshamlet</strong> (7 file(s) modified)</div><div>General code cleanup</div>~ /open8_urisc/trunk/VHDL/o8_alu16.vhd<br />~ /open8_urisc/trunk/VHDL/o8_etc.vhd<br />~ /open8_urisc/trunk/VHDL/o8_gpout.vhd<br />~ /open8_urisc/trunk/VHDL/o8_rtc.vhd<br />~ /open8_urisc/trunk/VHDL/o8_vdsm8.vhd<br />~ /open8_urisc/trunk/VHDL/Open8.vhd<br />~ /open8_urisc/trunk/VHDL/Open8_pkg.vhd<br /> jshamlet Thu, 07 Jan 2016 20:59:18 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=172 Corrected issue with CMP and SBC generating an inverted carry ... https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=169 <div><strong>Rev 169 - jshamlet</strong> (2 file(s) modified)</div><div>Corrected issue with CMP and SBC generating an inverted carry ...</div>~ /open8_urisc/trunk/VHDL/Open8.vhd<br />~ /open8_urisc/trunk/VHDL/Open8_pkg.vhd<br /> jshamlet Fri, 13 Nov 2015 20:09:09 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=169 Fixed bug in interrupt logic that caused stack pointer to ... https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=153 <div><strong>Rev 153 - jshamlet</strong> (2 file(s) modified)</div><div>Fixed bug in interrupt logic that caused stack pointer to ...</div>~ /open8_urisc/trunk/VHDL/Open8.vhd<br />~ /open8_urisc/trunk/VHDL/Open8_pkg.vhd<br /> jshamlet Sat, 25 Jun 2011 05:03:54 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=153 Fixed STO instruction and interrupt logic to avoid address bus ... https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=151 <div><strong>Rev 151 - jshamlet</strong> (2 file(s) modified)</div><div>Fixed STO instruction and interrupt logic to avoid address bus ...</div>~ /open8_urisc/trunk/VHDL/Open8.vhd<br />~ /open8_urisc/trunk/VHDL/Open8_pkg.vhd<br /> jshamlet Wed, 15 Jun 2011 01:59:05 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=151 corrected implementation for BTT to match V8/ARClite definition, changed sense ... https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=10 <div><strong>Rev 10 - khays</strong> (2 file(s) modified)</div><div>corrected implementation for BTT to match V8/ARClite definition, changed sense ...</div>~ /open8_urisc/trunk/VHDL/Open8.vhd<br />~ /open8_urisc/trunk/VHDL/Open8_pkg.vhd<br /> khays Mon, 24 Jan 2011 17:15:25 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=10 Need to learn SVN... https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=8 <div><strong>Rev 8 - jshamlet</strong> (2 file(s) modified)</div><div>Need to learn SVN...</div>- /open8_urisc/trunk/open8_urisc/VHDL<br />+ /open8_urisc/trunk/VHDL<br /> jshamlet Tue, 02 Mar 2010 05:57:45 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&rev=8 Initial Upload https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2Fopen8_urisc%2FVHDL%2F&rev=7 <div><strong>Rev 7 - jshamlet</strong> (4 file(s) modified)</div><div>Initial Upload</div>+ /open8_urisc/trunk/open8_urisc<br />+ /open8_urisc/trunk/open8_urisc/VHDL<br />+ /open8_urisc/trunk/open8_urisc/VHDL/Open8.vhd<br />+ /open8_urisc/trunk/open8_urisc/VHDL/Open8_pkg.vhd<br /> jshamlet Tue, 02 Mar 2010 05:56:49 +0100 https://opencores.org/websvn//websvn/revision?repname=open8_urisc&path=%2Fopen8_urisc%2Ftrunk%2Fopen8_urisc%2FVHDL%2F&rev=7

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