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        <link>https://opencores.org/websvn//websvn/listing?repname=open8_urisc&amp;path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2FOpen8_pkg.vhd&amp;</link>
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        <item>
            <title>Added RAM write fault detection, which can be used to ...</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=open8_urisc&amp;path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&amp;rev=251</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 251 - jshamlet&lt;/strong&gt; (4 file(s) modified)&lt;/div&gt;&lt;div&gt;Added RAM write fault detection, which can be used to ...&lt;/div&gt;~ /open8_urisc/trunk/VHDL/o8_ram_1k.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_ram_4k.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/Open8_pkg.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/status_led.vhd&lt;br /&gt;</description>
            <author>jshamlet</author>
            <pubDate>Tue, 09 Jun 2020 23:37:42 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=open8_urisc&amp;path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&amp;rev=251</guid>
        </item>
        <item>
            <title>Added an initialization constant for the OPEN8_BUS_TYPE record.</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=open8_urisc&amp;path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&amp;rev=228</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 228 - jshamlet&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;Added an initialization constant for the OPEN8_BUS_TYPE record.&lt;/div&gt;~ /open8_urisc/trunk/VHDL/Open8_pkg.vhd&lt;br /&gt;</description>
            <author>jshamlet</author>
            <pubDate>Fri, 17 Apr 2020 03:57:24 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=open8_urisc&amp;path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&amp;rev=228</guid>
        </item>
        <item>
            <title>Added a demonstration Open8_cfg.vhd file, which is used to configure ...</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=open8_urisc&amp;path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&amp;rev=227</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 227 - jshamlet&lt;/strong&gt; (3 file(s) modified)&lt;/div&gt;&lt;div&gt;Added a demonstration Open8_cfg.vhd file, which is used to configure ...&lt;/div&gt;~ /open8_urisc/trunk/VHDL/o8_cpu.vhd&lt;br /&gt;+ /open8_urisc/trunk/VHDL/Open8_cfg.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/Open8_pkg.vhd&lt;br /&gt;</description>
            <author>jshamlet</author>
            <pubDate>Thu, 16 Apr 2020 20:51:37 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=open8_urisc&amp;path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&amp;rev=227</guid>
        </item>
        <item>
            <title>Forgot the updated package file...</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=open8_urisc&amp;path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&amp;rev=226</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 226 - jshamlet&lt;/strong&gt; (1 file(s) modified)&lt;/div&gt;&lt;div&gt;Forgot the updated package file...&lt;/div&gt;~ /open8_urisc/trunk/VHDL/Open8_pkg.vhd&lt;br /&gt;</description>
            <author>jshamlet</author>
            <pubDate>Thu, 16 Apr 2020 17:20:17 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=open8_urisc&amp;path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&amp;rev=226</guid>
        </item>
        <item>
            <title>Finished new Open8 bus record, which now includes the clock, ...</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=open8_urisc&amp;path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&amp;rev=224</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 224 - jshamlet&lt;/strong&gt; (29 file(s) modified)&lt;/div&gt;&lt;div&gt;Finished new Open8 bus record, which now includes the clock, ...&lt;/div&gt;~ /open8_urisc/trunk/VHDL/o8_alu16.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_async_serial.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_btn_int.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_clk_detect.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_cpu.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_crc16_ccitt.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_datalatch.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_epoch_timer.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_epoch_timer_ii.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_gpin.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_gpio.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_gpout.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_hd44780_4b.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_hd44780_8b.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_lfsr32.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_ltc2355_2p.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_max7221.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_pwm16.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_ram_1k.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_ram_4k.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_register.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_rom_32k.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_rtc.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_sdlc_if.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_status_led.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_sys_timer.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_vdsm8.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_vdsm12.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/Open8_pkg.vhd&lt;br /&gt;</description>
            <author>jshamlet</author>
            <pubDate>Thu, 16 Apr 2020 15:20:57 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=open8_urisc&amp;path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&amp;rev=224</guid>
        </item>
        <item>
            <title>Added an OPEN8_BUS_TYPE record to simplify connection to Open8 modules. ...</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=open8_urisc&amp;path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&amp;rev=223</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 223 - jshamlet&lt;/strong&gt; (29 file(s) modified)&lt;/div&gt;&lt;div&gt;Added an OPEN8_BUS_TYPE record to simplify connection to Open8 modules. ...&lt;/div&gt;~ /open8_urisc/trunk/VHDL/o8_alu16.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_async_serial.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_btn_int.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_clk_detect.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_cpu.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_crc16_ccitt.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_datalatch.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_epoch_timer.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_epoch_timer_ii.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_gpin.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_gpio.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_gpout.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_hd44780_4b.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_hd44780_8b.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_lfsr32.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_ltc2355_2p.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_max7221.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_pwm16.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_ram_1k.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_ram_4k.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_register.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_rom_32k.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_rtc.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_sdlc_if.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_status_led.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_sys_timer.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_vdsm8.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_vdsm12.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/Open8_pkg.vhd&lt;br /&gt;</description>
            <author>jshamlet</author>
            <pubDate>Wed, 15 Apr 2020 22:12:24 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=open8_urisc&amp;path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&amp;rev=223</guid>
        </item>
        <item>
            <title>More revision sections added</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=open8_urisc&amp;path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&amp;rev=220</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 220 - jshamlet&lt;/strong&gt; (11 file(s) modified)&lt;/div&gt;&lt;div&gt;More revision sections added&lt;/div&gt;~ /open8_urisc/trunk/VHDL/async_ser_rx.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/async_ser_tx.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_ltc2355_2p.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/Open8_pkg.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/sdlc_crc16_ccitt.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/sdlc_serial_arbfsm.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/sdlc_serial_clk.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/sdlc_serial_frame.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/sdlc_serial_pkg.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/sdlc_serial_rx.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/vdsm8.vhd&lt;br /&gt;</description>
            <author>jshamlet</author>
            <pubDate>Tue, 14 Apr 2020 21:56:18 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=open8_urisc&amp;path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&amp;rev=220</guid>
        </item>
        <item>
            <title>Modified the timers to reset on new interval write. This ...</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=open8_urisc&amp;path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&amp;rev=210</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 210 - jshamlet&lt;/strong&gt; (4 file(s) modified)&lt;/div&gt;&lt;div&gt;Modified the timers to reset on new interval write. This ...&lt;/div&gt;~ /open8_urisc/trunk/VHDL/o8_cpu.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_rtc.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_sys_timer.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/Open8_pkg.vhd&lt;br /&gt;</description>
            <author>jshamlet</author>
            <pubDate>Thu, 09 Apr 2020 14:27:42 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=open8_urisc&amp;path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&amp;rev=210</guid>
        </item>
        <item>
            <title>Cleaned up comments, added back the OPEN8_NULLBUS constant, and added ...</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=open8_urisc&amp;path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&amp;rev=191</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 191 - jshamlet&lt;/strong&gt; (28 file(s) modified)&lt;/div&gt;&lt;div&gt;Cleaned up comments, added back the OPEN8_NULLBUS constant, and added ...&lt;/div&gt;+ /open8_urisc/trunk/VHDL/button_db.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_alu16.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_btn_int.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_clk_detect.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_cpu.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_crc16_ccitt.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_datalatch.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_epoch_timer.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_gpin.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_gpio.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_gpout.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_hd44780_4b.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_hd44780_8b.vhd&lt;br /&gt;+ /open8_urisc/trunk/VHDL/o8_ltc2355_2p.vhd&lt;br /&gt;+ /open8_urisc/trunk/VHDL/o8_max7221.vhd&lt;br /&gt;+ /open8_urisc/trunk/VHDL/o8_max7221_fifo.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_ram_1k.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_register.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_rom_32k.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_rtc.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_status_led.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_sys_timer.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_vdsm8.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_vdsm12.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/Open8_pkg.vhd&lt;br /&gt;+ /open8_urisc/trunk/VHDL/ram_1k_core.vhd&lt;br /&gt;+ /open8_urisc/trunk/VHDL/rom_32k_core.vhd&lt;br /&gt;+ /open8_urisc/trunk/VHDL/sdlc_crc16_ccitt.vhd&lt;br /&gt;</description>
            <author>jshamlet</author>
            <pubDate>Tue, 31 Mar 2020 18:53:53 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=open8_urisc&amp;path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&amp;rev=191</guid>
        </item>
        <item>
            <title>Merged changes from private repository,
added ceil_log2 function to Open8_pkg, since ...</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=open8_urisc&amp;path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&amp;rev=189</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 189 - jshamlet&lt;/strong&gt; (11 file(s) modified)&lt;/div&gt;&lt;div&gt;Merged changes from private repository,&lt;br /&gt;
added ceil_log2 function to Open8_pkg, since ...&lt;/div&gt;~ /open8_urisc/trunk/VHDL/o8_btn_int.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_epoch_timer.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_gpin.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_hd44780_4b.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_hd44780_8b.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_rtc.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_status_led.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_sys_timer.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_vdsm8.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_vdsm12.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/Open8_pkg.vhd&lt;br /&gt;</description>
            <author>jshamlet</author>
            <pubDate>Wed, 18 Mar 2020 20:47:28 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=open8_urisc&amp;path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&amp;rev=189</guid>
        </item>
        <item>
            <title>Added a generic to alter the behavior of RTI so ...</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=open8_urisc&amp;path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&amp;rev=188</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 188 - jshamlet&lt;/strong&gt; (2 file(s) modified)&lt;/div&gt;&lt;div&gt;Added a generic to alter the behavior of RTI so ...&lt;/div&gt;~ /open8_urisc/trunk/VHDL/o8_cpu.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/Open8_pkg.vhd&lt;br /&gt;</description>
            <author>jshamlet</author>
            <pubDate>Wed, 18 Mar 2020 18:01:59 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=open8_urisc&amp;path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&amp;rev=188</guid>
        </item>
        <item>
            <title>Added the CPU_Halt input, only now as an input to ...</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=open8_urisc&amp;path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&amp;rev=187</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 187 - jshamlet&lt;/strong&gt; (2 file(s) modified)&lt;/div&gt;&lt;div&gt;Added the CPU_Halt input, only now as an input to ...&lt;/div&gt;~ /open8_urisc/trunk/VHDL/o8_cpu.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/Open8_pkg.vhd&lt;br /&gt;</description>
            <author>jshamlet</author>
            <pubDate>Mon, 16 Mar 2020 21:46:04 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=open8_urisc&amp;path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&amp;rev=187</guid>
        </item>
        <item>
            <title>Merged the interrupt override logic into the case structure, simplifying ...</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=open8_urisc&amp;path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&amp;rev=186</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 186 - jshamlet&lt;/strong&gt; (2 file(s) modified)&lt;/div&gt;&lt;div&gt;Merged the interrupt override logic into the case structure, simplifying ...&lt;/div&gt;~ /open8_urisc/trunk/VHDL/o8_cpu.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/Open8_pkg.vhd&lt;br /&gt;</description>
            <author>jshamlet</author>
            <pubDate>Fri, 13 Mar 2020 21:56:13 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=open8_urisc&amp;path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&amp;rev=186</guid>
        </item>
        <item>
            <title>1) Fixed an apparently long-standing bug where the interrupt bit ...</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=open8_urisc&amp;path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&amp;rev=185</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 185 - jshamlet&lt;/strong&gt; (2 file(s) modified)&lt;/div&gt;&lt;div&gt;1) Fixed an apparently long-standing bug where the interrupt bit ...&lt;/div&gt;~ /open8_urisc/trunk/VHDL/o8_cpu.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/Open8_pkg.vhd&lt;br /&gt;</description>
            <author>jshamlet</author>
            <pubDate>Fri, 13 Mar 2020 19:13:36 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=open8_urisc&amp;path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&amp;rev=185</guid>
        </item>
        <item>
            <title>Renamed core to o8_cpu to match new naming scheme</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=open8_urisc&amp;path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&amp;rev=183</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 183 - jshamlet&lt;/strong&gt; (3 file(s) modified)&lt;/div&gt;&lt;div&gt;Renamed core to o8_cpu to match new naming scheme&lt;/div&gt;+ /open8_urisc/trunk/VHDL/o8_cpu.vhd&lt;br /&gt;- /open8_urisc/trunk/VHDL/Open8.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/Open8_pkg.vhd&lt;br /&gt;</description>
            <author>jshamlet</author>
            <pubDate>Wed, 11 Mar 2020 18:59:00 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=open8_urisc&amp;path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&amp;rev=183</guid>
        </item>
        <item>
            <title>Simplified the address generation logic at the expense of making ...</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=open8_urisc&amp;path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&amp;rev=182</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 182 - jshamlet&lt;/strong&gt; (2 file(s) modified)&lt;/div&gt;&lt;div&gt;Simplified the address generation logic at the expense of making ...&lt;/div&gt;~ /open8_urisc/trunk/VHDL/Open8.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/Open8_pkg.vhd&lt;br /&gt;</description>
            <author>jshamlet</author>
            <pubDate>Wed, 11 Mar 2020 18:56:40 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=open8_urisc&amp;path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&amp;rev=182</guid>
        </item>
        <item>
            <title>Altered the RSP instruction to allow the stack pointed to ...</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=open8_urisc&amp;path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&amp;rev=181</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 181 - jshamlet&lt;/strong&gt; (2 file(s) modified)&lt;/div&gt;&lt;div&gt;Altered the RSP instruction to allow the stack pointed to ...&lt;/div&gt;~ /open8_urisc/trunk/VHDL/Open8.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/Open8_pkg.vhd&lt;br /&gt;</description>
            <author>jshamlet</author>
            <pubDate>Tue, 10 Mar 2020 22:36:44 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=open8_urisc&amp;path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&amp;rev=181</guid>
        </item>
        <item>
            <title>General code cleanup</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=open8_urisc&amp;path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&amp;rev=172</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 172 - jshamlet&lt;/strong&gt; (7 file(s) modified)&lt;/div&gt;&lt;div&gt;General code cleanup&lt;/div&gt;~ /open8_urisc/trunk/VHDL/o8_alu16.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_etc.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_gpout.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_rtc.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/o8_vdsm8.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/Open8.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/Open8_pkg.vhd&lt;br /&gt;</description>
            <author>jshamlet</author>
            <pubDate>Thu, 07 Jan 2016 20:59:18 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=open8_urisc&amp;path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&amp;rev=172</guid>
        </item>
        <item>
            <title>Corrected issue with CMP and SBC generating an inverted carry ...</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=open8_urisc&amp;path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&amp;rev=169</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 169 - jshamlet&lt;/strong&gt; (2 file(s) modified)&lt;/div&gt;&lt;div&gt;Corrected issue with CMP and SBC generating an inverted carry ...&lt;/div&gt;~ /open8_urisc/trunk/VHDL/Open8.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/Open8_pkg.vhd&lt;br /&gt;</description>
            <author>jshamlet</author>
            <pubDate>Fri, 13 Nov 2015 20:09:09 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=open8_urisc&amp;path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&amp;rev=169</guid>
        </item>
        <item>
            <title>Fixed bug in interrupt logic that caused stack pointer to ...</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=open8_urisc&amp;path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&amp;rev=153</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 153 - jshamlet&lt;/strong&gt; (2 file(s) modified)&lt;/div&gt;&lt;div&gt;Fixed bug in interrupt logic that caused stack pointer to ...&lt;/div&gt;~ /open8_urisc/trunk/VHDL/Open8.vhd&lt;br /&gt;~ /open8_urisc/trunk/VHDL/Open8_pkg.vhd&lt;br /&gt;</description>
            <author>jshamlet</author>
            <pubDate>Sat, 25 Jun 2011 05:03:54 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=open8_urisc&amp;path=%2Fopen8_urisc%2Ftrunk%2FVHDL%2F&amp;rev=153</guid>
        </item>
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