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openmsp430 WebSVN RSS feed - openmsp430 https://opencores.org/websvn//websvn/listing?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fdoc%2Fhtml%2Foverview.html& Tue, 14 Apr 2026 09:27:15 +0100 FeedCreator 1.7.2 Add DMA interface support + LINT cleanup https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fdoc%2Fhtml%2F&rev=202 <div>Rev 202 - olivier.girard (254 file(s) modified)</div><div>Add DMA interface support + LINT cleanup</div>+ /openmsp430/trunk/core/bench/verilog/dma_tasks.v ~ /openmsp430/trunk/core/bench/verilog/tb_openMSP430.v + /openmsp430/trunk/core/rtl/verilog/filelist.f ~ /openmsp430/trunk/core/rtl/verilog/omsp_alu.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_and_gate.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_clock_gate.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_clock_module.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_clock_mux.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_dbg.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_dbg_hwbrk.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_dbg_i2c.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_dbg_uart.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_execution_unit.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_frontend.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_mem_backbone.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_multiplier.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_register_file.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_scan_mux.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_sfr.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_sync_cell.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_sync_reset.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_wakeup_cell.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_watchdog.v ~ /openmsp430/trunk/core/rtl/verilog/openMSP430.v ~ /openmsp430/trunk/core/rtl/verilog/openMSP430_defines.v ~ /openmsp430/trunk/core/rtl/verilog/openMSP430_undefines.v ~ /openmsp430/trunk/core/sim/rtl_sim/bin/asm2ihex.sh ~ /openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim ~ /openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim_c ~ /openmsp430/trunk/core/sim/rtl_sim/bin/parse_results + /openmsp430/trunk/core/sim/rtl_sim/bin/parse_summaries ~ /openmsp430/trunk/core/sim/rtl_sim/bin/rtlsim.sh ~ /openmsp430/trunk/core/sim/rtl_sim/bin/template_defs.asm ~ /openmsp430/trunk/core/sim/rtl_sim/run/run ~ /openmsp430/trunk/core/sim/rtl_sim/run/run_all ~ /openmsp430/trunk/core/sim/rtl_sim/run/run_all_mpy ~ /openmsp430/trunk/core/sim/rtl_sim/run/run_c ~ /openmsp430/trunk/core/sim/rtl_sim/run/run_disassemble + /openmsp430/trunk/core/sim/rtl_sim/run/simvision.svcf ~ /openmsp430/trunk/core/sim/rtl_sim/src-c/coremark_v1.0/coremark_v1.0.v ~ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_4mcu/dhrystone_4mcu.v ~ /openmsp430/trunk/core/sim/rtl_sim/src-c/dhrystone_v2.1/dhrystone_v2.1.v ~ /openmsp430/trunk/core/sim/rtl_sim/src-c/sandbox/sandbox.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/clock_module.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic_lfxt.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic_mclk.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/clock_module_asic_smclk.v - /openmsp430/trunk/core/sim/rtl_sim/src/core.f ~ /openmsp430/trunk/core/sim/rtl_sim/src/cpu_startup_asic.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_cpu.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_halt_irq.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_hwbrk0.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_hwbrk1.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_hwbrk2.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_hwbrk3.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_mem.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_onoff.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_onoff_asic.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_rdwr.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_i2c_sync.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_cpu.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_halt_irq.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_hwbrk0.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_hwbrk1.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_hwbrk2.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_hwbrk3.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_mem.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_onoff.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_onoff_asic.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_rdwr.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_sync.v + /openmsp430/trunk/core/sim/rtl_sim/src/dma_dbg_arbiter.s43 + /openmsp430/trunk/core/sim/rtl_sim/src/dma_dbg_arbiter.v + /openmsp430/trunk/core/sim/rtl_sim/src/dma_lpm0_asic.s43 + /openmsp430/trunk/core/sim/rtl_sim/src/dma_lpm0_asic.v + /openmsp430/trunk/core/sim/rtl_sim/src/dma_lpm1_asic.s43 + /openmsp430/trunk/core/sim/rtl_sim/src/dma_lpm1_asic.v + /openmsp430/trunk/core/sim/rtl_sim/src/dma_lpm2_asic.s43 + /openmsp430/trunk/core/sim/rtl_sim/src/dma_lpm2_asic.v + /openmsp430/trunk/core/sim/rtl_sim/src/dma_lpm3_asic.s43 + /openmsp430/trunk/core/sim/rtl_sim/src/dma_lpm3_asic.v + /openmsp430/trunk/core/sim/rtl_sim/src/dma_lpm4_asic.s43 + /openmsp430/trunk/core/sim/rtl_sim/src/dma_lpm4_asic.v + /openmsp430/trunk/core/sim/rtl_sim/src/dma_rdwr_8b.s43 + /openmsp430/trunk/core/sim/rtl_sim/src/dma_rdwr_8b.v + /openmsp430/trunk/core/sim/rtl_sim/src/dma_rdwr_16b.s43 + /openmsp430/trunk/core/sim/rtl_sim/src/dma_rdwr_16b.v + /openmsp430/trunk/core/sim/rtl_sim/src/dma_resp.s43 + /openmsp430/trunk/core/sim/rtl_sim/src/dma_resp.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/irq32.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/irq64.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/lp_modes_asic.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/lp_modes_dbg_asic.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/mpy_basic.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/mpy_mac.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/mpy_macs.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/mpy_mpy.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/mpy_mpys.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/nmi.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/op_modes.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/op_modes.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/op_modes_asic.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/sandbox.s43 ~ /openmsp430/trunk/core/sim/rtl_sim/src/sandbox.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/scan.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/submit.f ~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_capture.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_clkmux.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_compare.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_modes.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/tA_output.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/wdt_clkmux.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/wdt_interval.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/wdt_watchdog.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/wdt_wkup.v ~ /openmsp430/trunk/doc/html/core.html + /openmsp430/trunk/doc/html/dma_interface.html ~ /openmsp430/trunk/doc/html/images/core_integration.odg ~ /openmsp430/trunk/doc/html/images/core_integration.png ~ /openmsp430/trunk/doc/html/images/cpu_structure.odg ~ /openmsp430/trunk/doc/html/images/cpu_structure.png + /openmsp430/trunk/doc/html/images/dma_bootloader.png + /openmsp430/trunk/doc/html/images/dma_clock_domains.png + /openmsp430/trunk/doc/html/images/dma_interface.odg + /openmsp430/trunk/doc/html/images/dma_interface_complex_sys.png + /openmsp430/trunk/doc/html/images/dma_interface_simple_sys.png + /openmsp430/trunk/doc/html/images/dma_waveforms.odg + /openmsp430/trunk/doc/html/images/dma_waveform_bootloader.png + /openmsp430/trunk/doc/html/images/dma_waveform_error_resp.png + /openmsp430/trunk/doc/html/images/dma_waveform_multiple.png + /openmsp430/trunk/doc/html/images/dma_waveform_priority.png + /openmsp430/trunk/doc/html/images/dma_waveform_simple.png + /openmsp430/trunk/doc/html/images/dma_waveform_wait_states.png + /openmsp430/trunk/doc/html/images/wave_dma.odg + /openmsp430/trunk/doc/html/images/wave_dma.png ~ /openmsp430/trunk/doc/html/integration.html ~ /openmsp430/trunk/doc/html/overview.html ~ /openmsp430/trunk/doc/html/peripherals.html ~ /openmsp430/trunk/doc/html/serial_debug_interface.html ~ /openmsp430/trunk/doc/openMSP430.odt ~ /openmsp430/trunk/doc/openMSP430.pdf + /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/filelist.f ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_alu.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_and_gate.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_clock_gate.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_clock_module.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_clock_mux.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_dbg.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_dbg_hwbrk.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_dbg_i2c.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_dbg_uart.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_execution_unit.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_frontend.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_mem_backbone.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_multiplier.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_register_file.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_scan_mux.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_sfr.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_sync_cell.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_sync_reset.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_wakeup_cell.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_watchdog.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430_defines.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430_undefines.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openMSP430_fpga.v ~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/software/spacewar/linker.x + /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/filelist.f ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_alu.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_and_gate.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_clock_gate.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_clock_module.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_clock_mux.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_dbg.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_dbg_hwbrk.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_dbg_i2c.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_dbg_uart.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_execution_unit.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_frontend.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_mem_backbone.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_multiplier.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_register_file.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_scan_mux.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_sfr.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_sync_cell.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_sync_reset.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_wakeup_cell.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_watchdog.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/openMSP430.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/openMSP430_defines.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/openMSP430_undefines.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/OpenMSP430_fpga.v ~ /openmsp430/trunk/fpga/altera_de1_board/software/memledtest/link.ld ~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/omsp_system_0.v ~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/omsp_system_1.v ~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/omsp_uart.v + /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/filelist.f ~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/omsp_alu.v ~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/omsp_and_gate.v ~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/omsp_clock_gate.v ~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/omsp_clock_module.v ~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/omsp_clock_mux.v ~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/omsp_dbg.v ~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/omsp_dbg_hwbrk.v ~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/omsp_dbg_i2c.v ~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/omsp_dbg_uart.v ~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/omsp_execution_unit.v ~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/omsp_frontend.v ~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/omsp_mem_backbone.v ~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/omsp_multiplier.v ~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/omsp_register_file.v ~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/omsp_scan_mux.v ~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/omsp_sfr.v ~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/omsp_sync_cell.v ~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/omsp_sync_reset.v ~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/omsp_wakeup_cell.v ~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/omsp_watchdog.v ~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/openMSP430.v ~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/openMSP430_defines.v ~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/openMSP430_undefines.v ~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/sim/rtl_sim/src/submit.f ~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/software/leds/linker.x ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/omsp_uart.v + /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/filelist.f ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_alu.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_and_gate.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_clock_gate.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_clock_module.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_clock_mux.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_dbg.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_dbg_hwbrk.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_dbg_i2c.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_dbg_uart.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_execution_unit.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_frontend.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_mem_backbone.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_multiplier.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_register_file.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_scan_mux.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_sfr.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_sync_cell.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_sync_reset.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_wakeup_cell.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_watchdog.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430_defines.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430_undefines.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openMSP430_fpga.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/src/submit.f ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/software/hw_uart/linker.x ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/software/leds/linker.x olivier.girard Wed, 01 Jul 2015 21:13:32 +0100 https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fdoc%2Fhtml%2F&rev=202 Update HTML documentation with configurable number of IRQ option. https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fdoc%2Fhtml%2F&rev=195 <div>Rev 195 - olivier.girard (6 file(s) modified)</div><div>Update HTML documentation with configurable number of IRQ option.</div>~ /openmsp430/trunk/doc/html/core.html + /openmsp430/trunk/doc/html/images/cpu_irq_mapping.odg + /openmsp430/trunk/doc/html/images/cpu_irq_mapping.png ~ /openmsp430/trunk/doc/html/integration.html ~ /openmsp430/trunk/doc/html/overview.html + /openmsp430/trunk/doc/html/peripherals.html olivier.girard Tue, 17 Dec 2013 21:18:49 +0100 https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fdoc%2Fhtml%2F&rev=195 Update documentation with new I2C based serial debug interface https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fdoc%2Fhtml%2F&rev=166 <div>Rev 166 - olivier.girard (32 file(s) modified)</div><div>Update documentation with new I2C based serial debug interface</div>~ /openmsp430/trunk/doc/html/core.html ~ /openmsp430/trunk/doc/html/files_directory_description.html ~ /openmsp430/trunk/doc/html/images/core_integration.odg ~ /openmsp430/trunk/doc/html/images/core_integration.png ~ /openmsp430/trunk/doc/html/images/cpu_structure.odg ~ /openmsp430/trunk/doc/html/images/cpu_structure.png + /openmsp430/trunk/doc/html/images/dbg_i2c.png + /openmsp430/trunk/doc/html/images/dbg_i2c_cmd_frame.png + /openmsp430/trunk/doc/html/images/dbg_i2c_cmd_read.png + /openmsp430/trunk/doc/html/images/dbg_i2c_cmd_read_burst.png + /openmsp430/trunk/doc/html/images/dbg_i2c_cmd_write.png + /openmsp430/trunk/doc/html/images/dbg_i2c_cmd_write_burst.png + /openmsp430/trunk/doc/html/images/dbg_i2c_sda_io.png ~ /openmsp430/trunk/doc/html/images/dbg_uart_8N1.odg ~ /openmsp430/trunk/doc/html/images/dbg_uart_cmd_frame.odg ~ /openmsp430/trunk/doc/html/images/dbg_uart_cmd_read.odg ~ /openmsp430/trunk/doc/html/images/dbg_uart_cmd_read_burst.odg ~ /openmsp430/trunk/doc/html/images/dbg_uart_cmd_write.odg ~ /openmsp430/trunk/doc/html/images/dbg_uart_cmd_write_burst.odg ~ /openmsp430/trunk/doc/html/images/openmsp430-gdbproxy.png ~ /openmsp430/trunk/doc/html/images/openmsp430-loader_lin.png ~ /openmsp430/trunk/doc/html/images/openmsp430-minidebug.png + /openmsp430/trunk/doc/html/images/USB-ISS.png + /openmsp430/trunk/doc/html/images/usb2uart.png + /openmsp430/trunk/doc/html/images/usb2uart_ttl.png + /openmsp430/trunk/doc/html/images/wave_sdi_i2c.png ~ /openmsp430/trunk/doc/html/integration.html ~ /openmsp430/trunk/doc/html/overview.html ~ /openmsp430/trunk/doc/html/serial_debug_interface.html ~ /openmsp430/trunk/doc/html/software_development_tools.html ~ /openmsp430/trunk/doc/openMSP430.odt ~ /openmsp430/trunk/doc/openMSP430.pdf olivier.girard Tue, 27 Nov 2012 22:09:53 +0100 https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fdoc%2Fhtml%2F&rev=166 Update ChangeLog https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fdoc%2Fhtml%2F&rev=140 <div>Rev 140 - olivier.girard (2 file(s) modified)</div><div>Update ChangeLog</div>~ /openmsp430/trunk/ChangeLog_core.txt ~ /openmsp430/trunk/doc/html/overview.html olivier.girard Mon, 23 Apr 2012 19:58:54 +0100 https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fdoc%2Fhtml%2F&rev=140 Update documentation to reflect the ASIC implementation options. https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fdoc%2Fhtml%2F&rev=135 <div>Rev 135 - olivier.girard (37 file(s) modified)</div><div>Update documentation to reflect the ASIC implementation options.</div>+ /openmsp430/trunk/doc/area_speed_analysis.ods + /openmsp430/trunk/doc/area_speed_analysis.odt + /openmsp430/trunk/doc/area_speed_analysis.pdf ~ /openmsp430/trunk/doc/html/area_speed.html + /openmsp430/trunk/doc/html/asic_implementation.html ~ /openmsp430/trunk/doc/html/core.html ~ /openmsp430/trunk/doc/html/files_directory_description.html ~ /openmsp430/trunk/doc/html/images/clock_diagram.odg + /openmsp430/trunk/doc/html/images/clock_diagram_asic.png + /openmsp430/trunk/doc/html/images/clock_diagram_asic_config.png + /openmsp430/trunk/doc/html/images/clock_diagram_fpga.png + /openmsp430/trunk/doc/html/images/clock_divider.png + /openmsp430/trunk/doc/html/images/clock_divider_lowpower.png + /openmsp430/trunk/doc/html/images/clock_gate_latch.png + /openmsp430/trunk/doc/html/images/clock_gate_nand2.png + /openmsp430/trunk/doc/html/images/clock_mux.png ~ /openmsp430/trunk/doc/html/images/core_integration.odg ~ /openmsp430/trunk/doc/html/images/core_integration.png + /openmsp430/trunk/doc/html/images/dft_clock_gate.png + /openmsp430/trunk/doc/html/images/dft_clock_mux.png + /openmsp430/trunk/doc/html/images/dft_reset.png + /openmsp430/trunk/doc/html/images/lpm1_bis.png + /openmsp430/trunk/doc/html/images/lpm1_reti.png + /openmsp430/trunk/doc/html/images/lpm1_wakeup.png ~ /openmsp430/trunk/doc/html/images/openmsp430-gdbproxy-eclipse.png + /openmsp430/trunk/doc/html/images/openMSP430_tmax.png + /openmsp430/trunk/doc/html/images/sync_cell.png + /openmsp430/trunk/doc/html/images/sync_reset.png + /openmsp430/trunk/doc/html/images/wakeup_cell.png + /openmsp430/trunk/doc/html/images/wakeup_watchdog.png ~ /openmsp430/trunk/doc/html/integration.html ~ /openmsp430/trunk/doc/html/overview.html ~ /openmsp430/trunk/doc/html/serial_debug_interface.html ~ /openmsp430/trunk/doc/html/software_development_tools.html ~ /openmsp430/trunk/doc/openMSP430.odt ~ /openmsp430/trunk/doc/openMSP430.pdf - /openmsp430/trunk/doc/size_speed_analysis.ods olivier.girard Thu, 22 Mar 2012 21:11:54 +0100 https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fdoc%2Fhtml%2F&rev=135 Update documentation to reflect the latest core updates. https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fdoc%2Fhtml%2F&rev=116 <div>Rev 116 - olivier.girard (21 file(s) modified)</div><div>Update documentation to reflect the latest core updates.</div>~ /openmsp430/trunk/ChangeLog_core.txt ~ /openmsp430/trunk/ChangeLog_tools.txt ~ /openmsp430/trunk/doc/html/area_speed.html ~ /openmsp430/trunk/doc/html/core.html ~ /openmsp430/trunk/doc/html/files_directory_description.html ~ /openmsp430/trunk/doc/html/images/core_integration.odg ~ /openmsp430/trunk/doc/html/images/core_integration.png + /openmsp430/trunk/doc/html/images/cpu_mem_space.odg + /openmsp430/trunk/doc/html/images/cpu_mem_space.png + /openmsp430/trunk/doc/html/images/openmsp430-extra_info.png ~ /openmsp430/trunk/doc/html/images/openmsp430-gdbproxy-ddd.png ~ /openmsp430/trunk/doc/html/images/openmsp430-gdbproxy-eclipse.png ~ /openmsp430/trunk/doc/html/images/openmsp430-gdbproxy.png ~ /openmsp430/trunk/doc/html/images/openmsp430-loader_lin.png ~ /openmsp430/trunk/doc/html/images/openmsp430-minidebug.png ~ /openmsp430/trunk/doc/html/integration.html ~ /openmsp430/trunk/doc/html/overview.html ~ /openmsp430/trunk/doc/html/serial_debug_interface.html ~ /openmsp430/trunk/doc/html/software_development_tools.html ~ /openmsp430/trunk/doc/openMSP430.odt ~ /openmsp430/trunk/doc/openMSP430.pdf olivier.girard Tue, 07 Jun 2011 19:10:27 +0100 https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fdoc%2Fhtml%2F&rev=116 Update HTML documentation with Actel's FPGA implementation example (file & ... https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fdoc%2Fhtml%2F&rev=100 <div>Rev 100 - olivier.girard (8 file(s) modified)</div><div>Update HTML documentation with Actel's FPGA implementation example (file & ...</div>~ /openmsp430/trunk/doc/html/files_directory_description.html ~ /openmsp430/trunk/doc/html/images/openmsp430-minidebug.png + /openmsp430/trunk/doc/html/images/spacewar.png ~ /openmsp430/trunk/doc/html/overview.html ~ /openmsp430/trunk/doc/html/software_development_tools.html ~ /openmsp430/trunk/doc/openMSP430.odt ~ /openmsp430/trunk/doc/openMSP430.pdf ~ /openmsp430/trunk/fpga/altera_de1_board/software/memledtest olivier.girard Tue, 01 Mar 2011 21:15:13 +0100 https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fdoc%2Fhtml%2F&rev=100 Update serial debug interface to support memories with a size ... https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fdoc%2Fhtml%2F&rev=74 <div>Rev 74 - olivier.girard (22 file(s) modified)</div><div>Update serial debug interface to support memories with a size ...</div>~ /openmsp430/trunk/core/rtl/verilog/omsp_dbg.v ~ /openmsp430/trunk/core/rtl/verilog/omsp_dbg_uart.v ~ /openmsp430/trunk/core/rtl/verilog/openMSP430_defines.v ~ /openmsp430/trunk/core/rtl/verilog/openMSP430_undefines.v ~ /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart.v ~ /openmsp430/trunk/doc/html/overview.html ~ /openmsp430/trunk/doc/html/serial_debug_interface.html ~ /openmsp430/trunk/doc/openMSP430.odt ~ /openmsp430/trunk/doc/openMSP430.pdf ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_dbg.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_dbg_uart.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/openMSP430_defines.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/openMSP430_undefines.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/periph/template_periph_8b.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/periph/template_periph_16b.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_dbg.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_dbg_uart.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430_defines.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430_undefines.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/periph/template_periph_8b.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/periph/template_periph_16b.v ~ /openmsp430/trunk/tools/lib/tcl-lib/dbg_functions.tcl olivier.girard Sat, 28 Aug 2010 19:53:08 +0100 https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fdoc%2Fhtml%2F&rev=74 Expand configurability options of the program and data memory sizes. https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fdoc%2Fhtml%2F&rev=72 <div>Rev 72 - olivier.girard (16 file(s) modified)</div><div>Expand configurability options of the program and data memory sizes.</div>~ /openmsp430/trunk/core/bench/verilog/ram.v ~ /openmsp430/trunk/core/bench/verilog/tb_openMSP430.v ~ /openmsp430/trunk/core/rtl/verilog/openMSP430_defines.v ~ /openmsp430/trunk/core/rtl/verilog/openMSP430_undefines.v ~ /openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim ~ /openmsp430/trunk/doc/html/core.html ~ /openmsp430/trunk/doc/html/overview.html ~ /openmsp430/trunk/doc/html/software_development_tools.html ~ /openmsp430/trunk/doc/openMSP430.odt ~ /openmsp430/trunk/doc/openMSP430.pdf ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/openMSP430_defines.v ~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/openMSP430_undefines.v ~ /openmsp430/trunk/fpga/altera_de1_board/sim/rtl_sim/bin/msp430sim ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430_defines.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430_undefines.v ~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/sim/rtl_sim/bin/msp430sim olivier.girard Sun, 01 Aug 2010 18:54:37 +0100 https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fdoc%2Fhtml%2F&rev=72 Add Area and Speed documentation. https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fdoc%2Fhtml%2F&rev=70 <div>Rev 70 - olivier.girard (5 file(s) modified)</div><div>Add Area and Speed documentation.</div>+ /openmsp430/trunk/doc/html/area_speed.html ~ /openmsp430/trunk/doc/html/overview.html ~ /openmsp430/trunk/doc/openMSP430.odt ~ /openmsp430/trunk/doc/openMSP430.pdf + /openmsp430/trunk/doc/size_speed_analysis.ods olivier.girard Sun, 07 Mar 2010 17:04:34 +0100 https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fdoc%2Fhtml%2F&rev=70 Update HTML documentation with 16x16 hardware multiplier info. https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fdoc%2Fhtml%2F&rev=69 <div>Rev 69 - olivier.girard (6 file(s) modified)</div><div>Update HTML documentation with 16x16 hardware multiplier info.</div>~ /openmsp430/trunk/doc/html/core.html ~ /openmsp430/trunk/doc/html/files_directory_description.html ~ /openmsp430/trunk/doc/html/images/cpu_structure.odg ~ /openmsp430/trunk/doc/html/images/cpu_structure.png ~ /openmsp430/trunk/doc/html/overview.html ~ /openmsp430/trunk/doc/html/software_development_tools.html olivier.girard Sun, 07 Mar 2010 12:52:15 +0100 https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fdoc%2Fhtml%2F&rev=69 Re-add html documentation. https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fdoc%2Fhtml%2F&rev=50 <div>Rev 50 - olivier.girard (52 file(s) modified)</div><div>Re-add html documentation.</div>+ /openmsp430/trunk/doc + /openmsp430/trunk/doc/html + /openmsp430/trunk/doc/html/core.html + /openmsp430/trunk/doc/html/files_directory_description.html + /openmsp430/trunk/doc/html/images + /openmsp430/trunk/doc/html/images/clock_diagram.odg + /openmsp430/trunk/doc/html/images/clock_diagram.png + /openmsp430/trunk/doc/html/images/clock_example.odg + /openmsp430/trunk/doc/html/images/clock_example.png + /openmsp430/trunk/doc/html/images/core_integration.odg + /openmsp430/trunk/doc/html/images/core_integration.png + /openmsp430/trunk/doc/html/images/cpu_structure.odg + /openmsp430/trunk/doc/html/images/cpu_structure.png + /openmsp430/trunk/doc/html/images/dbg_uart_8N1.odg + /openmsp430/trunk/doc/html/images/dbg_uart_8N1.png + /openmsp430/trunk/doc/html/images/dbg_uart_cmd_frame.odg + /openmsp430/trunk/doc/html/images/dbg_uart_cmd_frame.png + /openmsp430/trunk/doc/html/images/dbg_uart_cmd_read.odg + /openmsp430/trunk/doc/html/images/dbg_uart_cmd_read.png + /openmsp430/trunk/doc/html/images/dbg_uart_cmd_read_burst.odg + /openmsp430/trunk/doc/html/images/dbg_uart_cmd_read_burst.png + /openmsp430/trunk/doc/html/images/dbg_uart_cmd_write.odg + /openmsp430/trunk/doc/html/images/dbg_uart_cmd_write.png + /openmsp430/trunk/doc/html/images/dbg_uart_cmd_write_burst.odg + /openmsp430/trunk/doc/html/images/dbg_uart_cmd_write_burst.png + /openmsp430/trunk/doc/html/images/dbg_uart_sync_frame.odg + /openmsp430/trunk/doc/html/images/dbg_uart_sync_frame.png + /openmsp430/trunk/doc/html/images/gdbproxy_flow.odg + /openmsp430/trunk/doc/html/images/gdbproxy_flow.png + /openmsp430/trunk/doc/html/images/openmsp430-gdbproxy-ddd.png + /openmsp430/trunk/doc/html/images/openmsp430-gdbproxy-eclipse.png + /openmsp430/trunk/doc/html/images/openmsp430-gdbproxy.png + /openmsp430/trunk/doc/html/images/openmsp430-loader_lin.png + /openmsp430/trunk/doc/html/images/openmsp430-loader_win.png + /openmsp430/trunk/doc/html/images/openmsp430-minidebug.png + /openmsp430/trunk/doc/html/images/wave_clocks.odg + /openmsp430/trunk/doc/html/images/wave_clocks.png + /openmsp430/trunk/doc/html/images/wave_dmem.odg + /openmsp430/trunk/doc/html/images/wave_dmem.png + /openmsp430/trunk/doc/html/images/wave_irq.odg + /openmsp430/trunk/doc/html/images/wave_irq.png + /openmsp430/trunk/doc/html/images/wave_per.odg + /openmsp430/trunk/doc/html/images/wave_per.png + /openmsp430/trunk/doc/html/images/wave_pmem.odg + /openmsp430/trunk/doc/html/images/wave_pmem.png + /openmsp430/trunk/doc/html/images/wave_resets.odg + /openmsp430/trunk/doc/html/images/wave_resets.png + /openmsp430/trunk/doc/html/images/wave_sdi.png + /openmsp430/trunk/doc/html/integration.html + /openmsp430/trunk/doc/html/overview.html + /openmsp430/trunk/doc/html/serial_debug_interface.html + /openmsp430/trunk/doc/html/software_development_tools.html olivier.girard Fri, 22 Jan 2010 22:23:28 +0100 https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Fdoc%2Fhtml%2F&rev=50

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