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openmsp430
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https://opencores.org/websvn//websvn/listing?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Ffpga%2Fxilinx_avnet_lx9microbard%2Frtl%2Fverilog%2Fopenmsp430%2Fomsp_dbg.v&
Mon, 22 Jun 2026 03:14:45 +0100
FeedCreator 1.7.2
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Update FPGA projects with latest openMSP430 core RTL
https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Ffpga%2Fxilinx_avnet_lx9microbard%2Frtl%2Fverilog%2Fopenmsp430%2F&rev=176
<div><strong>Rev 176 - olivier.girard</strong> (19 file(s) modified)</div><div>Update FPGA projects with latest openMSP430 core RTL</div>~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_dbg.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_dbg_hwbrk.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_execution_unit.v<br />~ /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/openMSP430.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_dbg.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_dbg_hwbrk.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_execution_unit.v<br />~ /openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/openMSP430.v<br />~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/omsp_dbg.v<br />~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/omsp_dbg_hwbrk.v<br />~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/omsp_execution_unit.v<br />~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/openmsp430/openMSP430.v<br />~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/synthesis/xilinx/bitstreams/leds.bit<br />~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/synthesis/xilinx/bitstreams/leds.mcs<br />~ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/synthesis/xilinx/bitstreams/openMSP430_fpga.bit<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_dbg.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_dbg_hwbrk.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_execution_unit.v<br />~ /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430.v<br />
olivier.girard
Wed, 30 Jan 2013 21:22:50 +0100
https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Ffpga%2Fxilinx_avnet_lx9microbard%2Frtl%2Fverilog%2Fopenmsp430%2F&rev=176
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Re-create new LX9 Microboard project to show off the new ...
https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Ffpga%2Fxilinx_avnet_lx9microbard%2Frtl%2Fverilog%2Fopenmsp430%2F&rev=157
<div><strong>Rev 157 - olivier.girard</strong> (281 file(s) modified)</div><div>Re-create new LX9 Microboard project to show off the new ...</div>+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/bench<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/bench/verilog<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/bench/verilog/glbl.v<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/bench/verilog/msp_debug.v<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/bench/verilog/ram.v<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/bench/verilog/ram_16x2k.v<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/bench/verilog/ram_16x512.v<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/bench/verilog/registers.v<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/bench/verilog/tb_openMSP430_fpga.v<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/bench/verilog/timescale.v<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/doc<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/doc/Avt_S6LX9_MicroBoard_UCF_110804.ucf<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/doc/Spartan-6_LX9_RevB1_Schematic.pdf<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/doc/Spartan-6_SelectIO_Resources_ug381.pdf<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/doc/U75_Avnet_Spartan-6_LX9_MicroBoard_Configuration_Guide_v13_2_1.pdf<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/doc/Xilinx_Spartan-6_LX9_MicroBoard_Rev_B2_Hardware_User_Guide.pdf<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/coregen.cgc<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/coregen.cgp<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/coregen.log<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x2k<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x2k.asy<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x2k.gise<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x2k.ngc<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x2k.v<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x2k.veo<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x2k.xco<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x2k.xise<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x2k/blk_mem_gen_v7_2_readme.txt<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x2k/doc<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x2k/doc/blk_mem_gen_v7_2_vinfo.html<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x2k/doc/pg058-blk-mem-gen.pdf<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x2k/example_design<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x2k/example_design/ram_16x2k_exdes.ucf<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x2k/example_design/ram_16x2k_exdes.vhd<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x2k/example_design/ram_16x2k_exdes.xdc<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x2k/example_design/ram_16x2k_prod.vhd<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x2k/implement<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x2k/implement/implement.bat<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x2k/implement/implement.sh<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x2k/implement/planAhead_ise.bat<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x2k/implement/planAhead_ise.sh<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x2k/implement/planAhead_ise.tcl<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x2k/implement/xst.prj<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x2k/implement/xst.scr<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x2k/simulation<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x2k/simulation/addr_gen.vhd<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x2k/simulation/bmg_stim_gen.vhd<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x2k/simulation/bmg_tb_pkg.vhd<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x2k/simulation/checker.vhd<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x2k/simulation/data_gen.vhd<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x2k/simulation/functional<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x2k/simulation/functional/simcmds.tcl<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x2k/simulation/functional/simulate_isim.sh<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x2k/simulation/functional/simulate_mti.bat<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x2k/simulation/functional/simulate_mti.do<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x2k/simulation/functional/simulate_mti.sh<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x2k/simulation/functional/simulate_ncsim.sh<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x2k/simulation/functional/simulate_vcs.sh<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x2k/simulation/functional/ucli_commands.key<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x2k/simulation/functional/vcs_session.tcl<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x2k/simulation/functional/wave_mti.do<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x2k/simulation/functional/wave_ncsim.sv<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x2k/simulation/ram_16x2k_synth.vhd<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x2k/simulation/ram_16x2k_tb.vhd<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x2k/simulation/random.vhd<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x2k/simulation/timing<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x2k/simulation/timing/simcmds.tcl<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x2k/simulation/timing/simulate_isim.sh<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x2k/simulation/timing/simulate_mti.bat<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x2k/simulation/timing/simulate_mti.do<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x2k/simulation/timing/simulate_mti.sh<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x2k/simulation/timing/simulate_ncsim.sh<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x2k/simulation/timing/simulate_vcs.sh<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x2k/simulation/timing/ucli_commands.key<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x2k/simulation/timing/vcs_session.tcl<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x2k/simulation/timing/wave_mti.do<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x2k/simulation/timing/wave_ncsim.sv<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x2k_flist.txt<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x2k_synth.v<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x2k_xmdf.tcl<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x512<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x512.asy<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x512.gise<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x512.ngc<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x512.v<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x512.veo<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x512.xco<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x512.xise<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x512/blk_mem_gen_v7_2_readme.txt<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x512/doc<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x512/doc/blk_mem_gen_v7_2_vinfo.html<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x512/doc/pg058-blk-mem-gen.pdf<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x512/example_design<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x512/example_design/ram_16x512_exdes.ucf<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x512/example_design/ram_16x512_exdes.vhd<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x512/example_design/ram_16x512_exdes.xdc<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x512/example_design/ram_16x512_prod.vhd<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x512/implement<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x512/implement/implement.bat<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x512/implement/implement.sh<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x512/implement/planAhead_ise.bat<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x512/implement/planAhead_ise.sh<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x512/implement/planAhead_ise.tcl<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x512/implement/xst.prj<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x512/implement/xst.scr<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x512/simulation<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x512/simulation/addr_gen.vhd<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x512/simulation/bmg_stim_gen.vhd<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x512/simulation/bmg_tb_pkg.vhd<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x512/simulation/checker.vhd<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x512/simulation/data_gen.vhd<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x512/simulation/functional<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x512/simulation/functional/simcmds.tcl<br />+ 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/openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/synthesis/xilinx/scripts<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/synthesis/xilinx/scripts/ihex2mem.tcl<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/synthesis/xilinx/scripts/impact_generate_prom_file.batch<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/synthesis/xilinx/scripts/impact_program_fpga.batch<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/synthesis/xilinx/scripts/memory.bmm<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/synthesis/xilinx/scripts/openMSP430_fpga.prj<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/synthesis/xilinx/scripts/openMSP430_fpga.ucf<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/synthesis/xilinx/scripts/xst_verilog.opt<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/synthesis/xilinx/win_0_create_bitstream.bat<br />+ /openmsp430/trunk/fpga/xilinx_avnet_lx9microbard/synthesis/xilinx/win_1_initialize_pmem.bat<br />
olivier.girard
Mon, 15 Oct 2012 21:44:57 +0100
https://opencores.org/websvn//websvn/revision?repname=openmsp430&path=%2Fopenmsp430%2Ftrunk%2Ffpga%2Fxilinx_avnet_lx9microbard%2Frtl%2Fverilog%2Fopenmsp430%2F&rev=157
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