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https://opencores.org/websvn//websvn/listing?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1ksim%2FChangeLog&
Tue, 14 Apr 2026 10:38:15 +0100
FeedCreator 1.7.2
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Updates for Or1ksim 0.5.0rc3.
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1ksim%2F&rev=508
<div><strong>Rev 508 - jeremybennett</strong> (14 file(s) modified)</div><div>Updates for Or1ksim 0.5.0rc3.</div>+ /openrisc/trunk/or1ksim/brend-static.sh<br />~ /openrisc/trunk/or1ksim/brend.sh<br />+ /openrisc/trunk/or1ksim/brstart-static.sh<br />~ /openrisc/trunk/or1ksim/ChangeLog<br />~ /openrisc/trunk/or1ksim/configure<br />~ /openrisc/trunk/or1ksim/configure.ac<br />~ /openrisc/trunk/or1ksim/cpu/or1k/sprs.c<br />~ /openrisc/trunk/or1ksim/doc/or1ksim.info<br />~ /openrisc/trunk/or1ksim/doc/or1ksim.texi<br />~ /openrisc/trunk/or1ksim/NEWS<br />~ /openrisc/trunk/or1ksim/peripheral/eth.c<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure.ac<br />
jeremybennett
Thu, 07 Apr 2011 11:09:33 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1ksim%2F&rev=508
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Change to ensure handles ctrl-C correctly with empty line.
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1ksim%2F&rev=494
<div><strong>Rev 494 - jeremybennett</strong> (8 file(s) modified)</div><div>Change to ensure handles ctrl-C correctly with empty line.</div>~ /openrisc/trunk/or1ksim/ChangeLog<br />~ /openrisc/trunk/or1ksim/configure<br />~ /openrisc/trunk/or1ksim/configure.ac<br />~ /openrisc/trunk/or1ksim/doc/version.texi<br />~ /openrisc/trunk/or1ksim/sim-cmd.c<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure.ac<br />
jeremybennett
Thu, 24 Feb 2011 18:07:27 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1ksim%2F&rev=494
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Updated with new opcodes to generate random numbers and to ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1ksim%2F&rev=483
<div><strong>Rev 483 - jeremybennett</strong> (20 file(s) modified)</div><div>Updated with new opcodes to generate random numbers and to ...</div>~ /openrisc/trunk/or1ksim/ChangeLog<br />~ /openrisc/trunk/or1ksim/configure<br />~ /openrisc/trunk/or1ksim/configure.ac<br />~ /openrisc/trunk/or1ksim/cpu/or1k/spr-defs.h<br />~ /openrisc/trunk/or1ksim/cpu/or32/insnset.c<br />~ /openrisc/trunk/or1ksim/doc/or1ksim.info<br />~ /openrisc/trunk/or1ksim/doc/or1ksim.texi<br />~ /openrisc/trunk/or1ksim/libtoplevel.c<br />~ /openrisc/trunk/or1ksim/NEWS<br />~ /openrisc/trunk/or1ksim/peripheral/memory.c<br />~ /openrisc/trunk/or1ksim/sim-config.c<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure.ac<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/support/spr-defs.h<br />~ /openrisc/trunk/or1ksim/toplevel-mprofile.c<br />~ /openrisc/trunk/or1ksim/toplevel-profile.c<br />~ /openrisc/trunk/or1ksim/toplevel-support.c<br />~ /openrisc/trunk/or1ksim/toplevel-support.h<br />~ /openrisc/trunk/or1ksim/toplevel.c<br />
jeremybennett
Tue, 01 Feb 2011 09:18:23 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1ksim%2F&rev=483
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Various changes which improve the quality of the tracing.
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1ksim%2F&rev=472
<div><strong>Rev 472 - jeremybennett</strong> (8 file(s) modified)</div><div>Various changes which improve the quality of the tracing.</div>~ /openrisc/trunk/or1ksim/ChangeLog<br />~ /openrisc/trunk/or1ksim/cpu/common/abstract.c<br />~ /openrisc/trunk/or1ksim/cpu/common/abstract.h<br />~ /openrisc/trunk/or1ksim/cpu/or32/execute.c<br />~ /openrisc/trunk/or1ksim/doc/or1ksim.info<br />~ /openrisc/trunk/or1ksim/doc/or1ksim.texi<br />~ /openrisc/trunk/or1ksim/sim-config.c<br />~ /openrisc/trunk/or1ksim/sim-config.h<br />
jeremybennett
Thu, 13 Jan 2011 08:22:43 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1ksim%2F&rev=472
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Merged in changes from Jeremy to Ethernet, updated documentation of ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1ksim%2F&rev=460
<div><strong>Rev 460 - jeremybennett</strong> (87 file(s) modified)</div><div>Merged in changes from Jeremy to Ethernet, updated documentation of ...</div>~ /openrisc/trunk/or1ksim/aclocal.m4<br />~ /openrisc/trunk/or1ksim/argtable2/Makefile.in<br />~ /openrisc/trunk/or1ksim/bpb/Makefile.in<br />~ /openrisc/trunk/or1ksim/cache/Makefile.in<br />~ /openrisc/trunk/or1ksim/ChangeLog<br />~ /openrisc/trunk/or1ksim/configure<br />~ /openrisc/trunk/or1ksim/configure.ac<br />~ /openrisc/trunk/or1ksim/cpu/common/Makefile.in<br />~ /openrisc/trunk/or1ksim/cpu/dlx/Makefile.in<br />~ /openrisc/trunk/or1ksim/cpu/Makefile.in<br />~ /openrisc/trunk/or1ksim/cpu/or1k/Makefile.in<br />~ /openrisc/trunk/or1ksim/cpu/or1k/spr-defs.h<br />~ /openrisc/trunk/or1ksim/cpu/or32/insnset.c<br />~ /openrisc/trunk/or1ksim/cpu/or32/Makefile.in<br />~ /openrisc/trunk/or1ksim/cuc/Makefile.in<br />~ /openrisc/trunk/or1ksim/debug/Makefile.in<br />~ /openrisc/trunk/or1ksim/doc/Makefile.in<br />~ /openrisc/trunk/or1ksim/doc/or1ksim.info<br />~ /openrisc/trunk/or1ksim/doc/or1ksim.texi<br />~ /openrisc/trunk/or1ksim/doc/version.texi<br />~ /openrisc/trunk/or1ksim/Makefile.in<br />~ /openrisc/trunk/or1ksim/mmu/Makefile.in<br />~ /openrisc/trunk/or1ksim/peripheral/channels/Makefile.in<br />~ /openrisc/trunk/or1ksim/peripheral/eth.c<br />~ /openrisc/trunk/or1ksim/peripheral/Makefile.in<br />~ /openrisc/trunk/or1ksim/pic/Makefile.in<br />~ /openrisc/trunk/or1ksim/pm/Makefile.in<br />~ /openrisc/trunk/or1ksim/port/Makefile.in<br />~ /openrisc/trunk/or1ksim/softfloat/Makefile.in<br />~ /openrisc/trunk/or1ksim/support/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/ChangeLog<br />~ /openrisc/trunk/or1ksim/testsuite/config/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/lib/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/libsim.tests/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/or1ksim.tests/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/README<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/aclocal.m4<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/acv-gpio/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/acv-uart/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/basic/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/cache/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/cbasic/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/cfg/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure.ac<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/dhry/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/dmatest/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/eth/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/except-test/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/except/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/exit/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ext/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/fbtest/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/flag/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/fp/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/functest/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/inst-set-test/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/int-logger/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/int-test/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/kbdtest/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/local-global/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/loop/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-async/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-common/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-dram/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-ssram/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-sync/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mem-test/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mmu/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mul/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mycompress/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/support/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/support/spr-defs.h<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/testfloat/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/tick/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/uos/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/upcalls/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-iftest/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-inttest/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-jtag/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-upcalls/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code/Makefile.in<br />~ /openrisc/trunk/or1ksim/tick/Makefile.in<br />~ /openrisc/trunk/or1ksim/vapi/Makefile.in<br />
jeremybennett
Wed, 05 Jan 2011 10:08:41 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1ksim%2F&rev=460
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or1ksim testsuite updates
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1ksim%2F&rev=458
<div><strong>Rev 458 - julius</strong> (55 file(s) modified)</div><div>or1ksim testsuite updates</div>~ /openrisc/trunk/or1ksim/ChangeLog<br />~ /openrisc/trunk/or1ksim/cpu/common/abstract.c<br />~ /openrisc/trunk/or1ksim/cpu/or1k/opcode/or32.h<br />~ /openrisc/trunk/or1ksim/cpu/or32/or32.c<br />~ /openrisc/trunk/or1ksim/testsuite/ChangeLog<br />~ /openrisc/trunk/or1ksim/testsuite/libsim.tests/default.cfg<br />~ /openrisc/trunk/or1ksim/testsuite/libsim.tests/int-edge.cfg<br />~ /openrisc/trunk/or1ksim/testsuite/libsim.tests/int-level.cfg<br />~ /openrisc/trunk/or1ksim/testsuite/libsim.tests/upcalls.cfg<br />~ /openrisc/trunk/or1ksim/testsuite/or1ksim.tests/cache.exp<br />~ /openrisc/trunk/or1ksim/testsuite/or1ksim.tests/default.cfg<br />~ /openrisc/trunk/or1ksim/testsuite/or1ksim.tests/eth.cfg<br />~ /openrisc/trunk/or1ksim/testsuite/or1ksim.tests/fp.cfg<br />~ /openrisc/trunk/or1ksim/testsuite/or1ksim.tests/int-test.exp<br />~ /openrisc/trunk/or1ksim/testsuite/or1ksim.tests/kbdtest.cfg<br />~ /openrisc/trunk/or1ksim/testsuite/or1ksim.tests/mem-test.exp<br />~ /openrisc/trunk/or1ksim/testsuite/or1ksim.tests/mmu.cfg<br />~ /openrisc/trunk/or1ksim/testsuite/or1ksim.tests/mmu.exp<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/basic/basic.S<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/basic/Makefile.am<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/basic/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/cache/cache-asm.S<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/cache/cache.c<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/cache/cache.ld<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/cfg/cfg.S<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure.ac<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/default.ld<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/dhry/dhry.c<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/except-mc.ld<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/except-test/except-test-s.S<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/except-test/except-test.c<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/except/except.S<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ext/ext.S<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/flag/flag.S<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/fp/fp.S<br />- /openrisc/trunk/or1ksim/testsuite/test-code-or1k/int-test/int-test.ld<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/int-test/int-test.S<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/int-test/Makefile.am<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/int-test/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-async/Makefile.am<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-async/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-dram/Makefile.am<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-dram/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-ssram/Makefile.am<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-ssram/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-ssram/mc-ssram.c<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-sync/Makefile.am<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-sync/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mmu/mmu-asm.S<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mmu/mmu.c<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mul/mul.c<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/support/support.c<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/tick/tick.c<br />~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-upcalls/lib-upcalls.c<br />
julius
Tue, 04 Jan 2011 05:50:24 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1ksim%2F&rev=458
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or1ksim - couple of ethernet peripheral updates, fixup of ethernet ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1ksim%2F&rev=457
<div><strong>Rev 457 - julius</strong> (83 file(s) modified)</div><div>or1ksim - couple of ethernet peripheral updates, fixup of ethernet ...</div>~ /openrisc/trunk/or1ksim/aclocal.m4<br />~ /openrisc/trunk/or1ksim/argtable2/Makefile.in<br />~ /openrisc/trunk/or1ksim/autom4te.cache/output.0<br />~ /openrisc/trunk/or1ksim/autom4te.cache/output.1<br />~ /openrisc/trunk/or1ksim/autom4te.cache/traces.0<br />~ /openrisc/trunk/or1ksim/bpb/Makefile.in<br />~ /openrisc/trunk/or1ksim/cache/Makefile.in<br />~ /openrisc/trunk/or1ksim/ChangeLog<br />~ /openrisc/trunk/or1ksim/configure<br />~ /openrisc/trunk/or1ksim/cpu/common/Makefile.in<br />~ /openrisc/trunk/or1ksim/cpu/dlx/Makefile.in<br />~ /openrisc/trunk/or1ksim/cpu/Makefile.in<br />~ /openrisc/trunk/or1ksim/cpu/or1k/Makefile.in<br />~ /openrisc/trunk/or1ksim/cpu/or32/Makefile.in<br />~ /openrisc/trunk/or1ksim/cuc/Makefile.in<br />~ /openrisc/trunk/or1ksim/debug/Makefile.in<br />~ /openrisc/trunk/or1ksim/doc/Makefile.in<br />~ /openrisc/trunk/or1ksim/Makefile.in<br />~ /openrisc/trunk/or1ksim/mmu/Makefile.in<br />~ /openrisc/trunk/or1ksim/peripheral/channels/Makefile.in<br />~ /openrisc/trunk/or1ksim/peripheral/eth.c<br />~ /openrisc/trunk/or1ksim/peripheral/Makefile.in<br />~ /openrisc/trunk/or1ksim/pic/Makefile.in<br />~ /openrisc/trunk/or1ksim/pm/Makefile.in<br />~ /openrisc/trunk/or1ksim/port/Makefile.in<br />~ /openrisc/trunk/or1ksim/softfloat/Makefile.in<br />~ /openrisc/trunk/or1ksim/support/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/ChangeLog<br />~ /openrisc/trunk/or1ksim/testsuite/config/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/lib/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/libsim.tests/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/or1ksim.tests/eth.cfg<br />~ /openrisc/trunk/or1ksim/testsuite/or1ksim.tests/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/aclocal.m4<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/acv-gpio/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/acv-uart/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/basic/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/cache/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/cbasic/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/cfg/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/dhry/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/dmatest/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/eth/eth.c<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/eth/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/except-test/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/except/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/exit/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ext/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/fbtest/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/flag/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/fp/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/functest/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/inst-set-test/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/int-logger/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/int-test/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/kbdtest/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/local-global/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/loop/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-async/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-common/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-dram/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-ssram/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-sync/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mem-test/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mmu/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mul/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mycompress/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/support/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/testfloat/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/tick/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/uos/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/upcalls/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-iftest/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-inttest/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-jtag/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-upcalls/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code/Makefile.in<br />~ /openrisc/trunk/or1ksim/tick/Makefile.in<br />~ /openrisc/trunk/or1ksim/vapi/Makefile.in<br />
julius
Sun, 26 Dec 2010 15:31:35 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1ksim%2F&rev=457
-
More tidying up.
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1ksim%2F&rev=451
<div><strong>Rev 451 - jeremybennett</strong> (5 file(s) modified)</div><div>More tidying up.</div>~ /openrisc/trunk/or1ksim/ChangeLog<br />~ /openrisc/trunk/or1ksim/doc/or1ksim.info<br />~ /openrisc/trunk/or1ksim/doc/or1ksim.texi<br />~ /openrisc/trunk/or1ksim/doc/version.texi<br />~ /openrisc/trunk/or1ksim/peripheral/eth.c<br />
jeremybennett
Wed, 15 Dec 2010 19:25:29 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1ksim%2F&rev=451
-
Simplified (and hopefully more reliable) Ethernet MAC/PHY.
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1ksim%2F&rev=450
<div><strong>Rev 450 - jeremybennett</strong> (9 file(s) modified)</div><div>Simplified (and hopefully more reliable) Ethernet MAC/PHY.</div>~ /openrisc/trunk/or1ksim/ChangeLog<br />~ /openrisc/trunk/or1ksim/configure<br />~ /openrisc/trunk/or1ksim/configure.ac<br />~ /openrisc/trunk/or1ksim/doc/or1ksim.info<br />~ /openrisc/trunk/or1ksim/doc/version.texi<br />~ /openrisc/trunk/or1ksim/peripheral/eth.c<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure.ac<br />
jeremybennett
Wed, 15 Dec 2010 15:41:08 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1ksim%2F&rev=450
-
OR1Ksim - adding trace controlability by SIGUSR1 signal.
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1ksim%2F&rev=442
<div><strong>Rev 442 - julius</strong> (11 file(s) modified)</div><div>OR1Ksim - adding trace controlability by SIGUSR1 signal.</div>~ /openrisc/trunk/or1ksim/autom4te.cache/output.0<br />~ /openrisc/trunk/or1ksim/autom4te.cache/requests<br />~ /openrisc/trunk/or1ksim/autom4te.cache/traces.0<br />~ /openrisc/trunk/or1ksim/ChangeLog<br />~ /openrisc/trunk/or1ksim/doc/or1ksim.info<br />~ /openrisc/trunk/or1ksim/doc/or1ksim.texi<br />~ /openrisc/trunk/or1ksim/doc/version.texi<br />~ /openrisc/trunk/or1ksim/peripheral/eth.c<br />~ /openrisc/trunk/or1ksim/toplevel-support.c<br />~ /openrisc/trunk/or1ksim/toplevel-support.h<br />~ /openrisc/trunk/or1ksim/toplevel.c<br />
julius
Thu, 09 Dec 2010 21:08:47 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1ksim%2F&rev=442
-
Updated documentation to describe new Ethernet usage.
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1ksim%2F&rev=440
<div><strong>Rev 440 - jeremybennett</strong> (84 file(s) modified)</div><div>Updated documentation to describe new Ethernet usage.</div>~ /openrisc/trunk/or1ksim/aclocal.m4<br />~ /openrisc/trunk/or1ksim/argtable2/Makefile.in<br />~ /openrisc/trunk/or1ksim/bpb/Makefile.in<br />+ /openrisc/trunk/or1ksim/brend.sh<br />+ /openrisc/trunk/or1ksim/brstart.sh<br />~ /openrisc/trunk/or1ksim/cache/Makefile.in<br />~ /openrisc/trunk/or1ksim/ChangeLog<br />~ /openrisc/trunk/or1ksim/configure<br />~ /openrisc/trunk/or1ksim/configure.ac<br />~ /openrisc/trunk/or1ksim/cpu/common/Makefile.in<br />~ /openrisc/trunk/or1ksim/cpu/dlx/Makefile.in<br />~ /openrisc/trunk/or1ksim/cpu/Makefile.in<br />~ /openrisc/trunk/or1ksim/cpu/or1k/Makefile.in<br />~ /openrisc/trunk/or1ksim/cpu/or32/Makefile.in<br />~ /openrisc/trunk/or1ksim/cuc/Makefile.in<br />~ /openrisc/trunk/or1ksim/debug/Makefile.in<br />~ /openrisc/trunk/or1ksim/doc/Makefile.in<br />~ /openrisc/trunk/or1ksim/doc/or1ksim.info<br />~ /openrisc/trunk/or1ksim/doc/or1ksim.texi<br />~ /openrisc/trunk/or1ksim/doc/version.texi<br />~ /openrisc/trunk/or1ksim/Makefile.in<br />~ /openrisc/trunk/or1ksim/mmu/Makefile.in<br />~ /openrisc/trunk/or1ksim/peripheral/channels/Makefile.in<br />~ /openrisc/trunk/or1ksim/peripheral/Makefile.in<br />~ /openrisc/trunk/or1ksim/pic/Makefile.in<br />~ /openrisc/trunk/or1ksim/pic/pic.c<br />~ /openrisc/trunk/or1ksim/pm/Makefile.in<br />~ /openrisc/trunk/or1ksim/port/Makefile.in<br />~ /openrisc/trunk/or1ksim/softfloat/Makefile.in<br />~ /openrisc/trunk/or1ksim/support/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/config/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/lib/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/libsim.tests/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/or1ksim.tests/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/aclocal.m4<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/acv-gpio/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/acv-uart/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/basic/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/cache/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/cbasic/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/cfg/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure.ac<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/dhry/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/dmatest/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/eth/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/except-test/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/except/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/exit/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ext/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/fbtest/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/flag/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/fp/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/functest/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/inst-set-test/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/int-logger/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/int-test/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/kbdtest/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/local-global/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/loop/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-async/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-common/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-dram/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-ssram/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-sync/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mem-test/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mmu/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mul/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mycompress/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/support/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/testfloat/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/tick/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/uos/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/upcalls/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-iftest/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-inttest/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-jtag/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-upcalls/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code/Makefile.in<br />~ /openrisc/trunk/or1ksim/tick/Makefile.in<br />~ /openrisc/trunk/or1ksim/vapi/Makefile.in<br />
jeremybennett
Wed, 08 Dec 2010 19:35:51 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1ksim%2F&rev=440
-
Or1ksim - ethernet peripheral update, working much better.
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1ksim%2F&rev=437
<div><strong>Rev 437 - julius</strong> (2 file(s) modified)</div><div>Or1ksim - ethernet peripheral update, working much better.</div>~ /openrisc/trunk/or1ksim/ChangeLog<br />~ /openrisc/trunk/or1ksim/peripheral/eth.c<br />
julius
Wed, 01 Dec 2010 01:06:24 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1ksim%2F&rev=437
-
Or1ksim ethernet TAP updates. Ethernet test still failing.
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1ksim%2F&rev=436
<div><strong>Rev 436 - julius</strong> (83 file(s) modified)</div><div>Or1ksim ethernet TAP updates. Ethernet test still failing.</div>~ /openrisc/trunk/or1ksim/aclocal.m4<br />~ /openrisc/trunk/or1ksim/argtable2/Makefile.in<br />~ /openrisc/trunk/or1ksim/autom4te.cache/output.0<br />~ /openrisc/trunk/or1ksim/autom4te.cache/output.1<br />~ /openrisc/trunk/or1ksim/autom4te.cache/requests<br />~ /openrisc/trunk/or1ksim/autom4te.cache/traces.0<br />~ /openrisc/trunk/or1ksim/bpb/Makefile.in<br />~ /openrisc/trunk/or1ksim/cache/Makefile.in<br />~ /openrisc/trunk/or1ksim/ChangeLog<br />~ /openrisc/trunk/or1ksim/configure<br />~ /openrisc/trunk/or1ksim/cpu/common/Makefile.in<br />~ /openrisc/trunk/or1ksim/cpu/dlx/Makefile.in<br />~ /openrisc/trunk/or1ksim/cpu/Makefile.in<br />~ /openrisc/trunk/or1ksim/cpu/or1k/Makefile.in<br />~ /openrisc/trunk/or1ksim/cpu/or1k/sprs.c<br />~ /openrisc/trunk/or1ksim/cpu/or32/Makefile.in<br />~ /openrisc/trunk/or1ksim/cuc/Makefile.in<br />~ /openrisc/trunk/or1ksim/debug/Makefile.in<br />~ /openrisc/trunk/or1ksim/doc/Makefile.in<br />~ /openrisc/trunk/or1ksim/doc/or1ksim.info<br />~ /openrisc/trunk/or1ksim/Makefile.in<br />~ /openrisc/trunk/or1ksim/mmu/Makefile.in<br />~ /openrisc/trunk/or1ksim/peripheral/channels/Makefile.in<br />~ /openrisc/trunk/or1ksim/peripheral/eth.c<br />~ /openrisc/trunk/or1ksim/peripheral/Makefile.in<br />~ /openrisc/trunk/or1ksim/pic/Makefile.in<br />~ /openrisc/trunk/or1ksim/pic/pic.c<br />~ /openrisc/trunk/or1ksim/pm/Makefile.in<br />~ /openrisc/trunk/or1ksim/port/Makefile.in<br />~ /openrisc/trunk/or1ksim/softfloat/Makefile.in<br />~ /openrisc/trunk/or1ksim/support/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/config/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/lib/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/libsim.tests/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/or1ksim.tests/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/aclocal.m4<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/acv-gpio/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/acv-uart/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/basic/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/cache/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/cbasic/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/cfg/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/dhry/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/dmatest/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/eth/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/except-test/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/except/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/exit/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ext/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/fbtest/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/flag/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/fp/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/functest/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/inst-set-test/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/int-logger/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/int-test/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/kbdtest/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/local-global/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/loop/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-async/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-common/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-dram/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-ssram/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-sync/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mem-test/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mmu/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mul/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mycompress/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/support/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/testfloat/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/tick/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/uos/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/upcalls/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-iftest/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-inttest/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-jtag/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-upcalls/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code/Makefile.in<br />~ /openrisc/trunk/or1ksim/tick/Makefile.in<br />~ /openrisc/trunk/or1ksim/vapi/Makefile.in<br />
julius
Tue, 30 Nov 2010 00:50:00 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1ksim%2F&rev=436
-
Work in progress with new Ethernet TUN/TAP interface.
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1ksim%2F&rev=434
<div><strong>Rev 434 - jeremybennett</strong> (19 file(s) modified)</div><div>Work in progress with new Ethernet TUN/TAP interface.</div>~ /openrisc/trunk/or1ksim/ChangeLog<br />~ /openrisc/trunk/or1ksim/configure<br />~ /openrisc/trunk/or1ksim/configure.ac<br />~ /openrisc/trunk/or1ksim/doc/or1ksim.info<br />~ /openrisc/trunk/or1ksim/doc/version.texi<br />~ /openrisc/trunk/or1ksim/peripheral/eth.c<br />~ /openrisc/trunk/or1ksim/peripheral/eth.h<br />~ /openrisc/trunk/or1ksim/testsuite/ChangeLog<br />~ /openrisc/trunk/or1ksim/testsuite/libsim.tests/default.cfg<br />~ /openrisc/trunk/or1ksim/testsuite/libsim.tests/int-edge.cfg<br />~ /openrisc/trunk/or1ksim/testsuite/libsim.tests/int-level.cfg<br />~ /openrisc/trunk/or1ksim/testsuite/libsim.tests/upcalls.cfg<br />~ /openrisc/trunk/or1ksim/testsuite/or1ksim.tests/default.cfg<br />~ /openrisc/trunk/or1ksim/testsuite/or1ksim.tests/eth.cfg<br />~ /openrisc/trunk/or1ksim/testsuite/or1ksim.tests/fp.cfg<br />~ /openrisc/trunk/or1ksim/testsuite/or1ksim.tests/kbdtest.cfg<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure.ac<br />
jeremybennett
Fri, 26 Nov 2010 18:45:29 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1ksim%2F&rev=434
-
Updates to handle interrupts correctly.
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1ksim%2F&rev=432
<div><strong>Rev 432 - jeremybennett</strong> (99 file(s) modified)</div><div>Updates to handle interrupts correctly.</div>~ /openrisc/trunk/or1ksim/aclocal.m4<br />~ /openrisc/trunk/or1ksim/argtable2/Makefile.in<br />~ /openrisc/trunk/or1ksim/bpb/Makefile.in<br />~ /openrisc/trunk/or1ksim/cache/Makefile.in<br />~ /openrisc/trunk/or1ksim/ChangeLog<br />~ /openrisc/trunk/or1ksim/configure<br />~ /openrisc/trunk/or1ksim/configure.ac<br />~ /openrisc/trunk/or1ksim/cpu/common/Makefile.in<br />~ /openrisc/trunk/or1ksim/cpu/dlx/Makefile.in<br />~ /openrisc/trunk/or1ksim/cpu/Makefile.in<br />~ /openrisc/trunk/or1ksim/cpu/or1k/Makefile.in<br />~ /openrisc/trunk/or1ksim/cpu/or1k/spr-defs.h<br />~ /openrisc/trunk/or1ksim/cpu/or1k/sprs.c<br />~ /openrisc/trunk/or1ksim/cpu/or32/Makefile.in<br />~ /openrisc/trunk/or1ksim/cuc/Makefile.in<br />~ /openrisc/trunk/or1ksim/debug/Makefile.in<br />~ /openrisc/trunk/or1ksim/doc/Makefile.in<br />~ /openrisc/trunk/or1ksim/doc/or1ksim.info<br />~ /openrisc/trunk/or1ksim/doc/or1ksim.texi<br />~ /openrisc/trunk/or1ksim/doc/version.texi<br />~ /openrisc/trunk/or1ksim/libtoplevel.c<br />~ /openrisc/trunk/or1ksim/Makefile.in<br />~ /openrisc/trunk/or1ksim/mmu/Makefile.in<br />~ /openrisc/trunk/or1ksim/NEWS<br />~ /openrisc/trunk/or1ksim/peripheral/channels/Makefile.in<br />~ /openrisc/trunk/or1ksim/peripheral/Makefile.in<br />~ /openrisc/trunk/or1ksim/pic/Makefile.in<br />~ /openrisc/trunk/or1ksim/pic/pic.c<br />~ /openrisc/trunk/or1ksim/pm/Makefile.in<br />~ /openrisc/trunk/or1ksim/port/Makefile.in<br />~ /openrisc/trunk/or1ksim/sim-config.c<br />~ /openrisc/trunk/or1ksim/sim-config.h<br />~ /openrisc/trunk/or1ksim/softfloat/Makefile.in<br />~ /openrisc/trunk/or1ksim/support/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/ChangeLog<br />~ /openrisc/trunk/or1ksim/testsuite/config/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/lib/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/libsim.tests/int-edge.exp<br />~ /openrisc/trunk/or1ksim/testsuite/libsim.tests/int-level.exp<br />~ /openrisc/trunk/or1ksim/testsuite/libsim.tests/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/or1ksim.tests/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/README<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/aclocal.m4<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/acv-gpio/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/acv-uart/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/basic/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/cache/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/cbasic/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/cfg/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure.ac<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/dhry/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/dmatest/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/eth/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/except-test/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/except/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/exit/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ext/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/fbtest/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/flag/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/fp/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/functest/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/inst-set-test/Makefile.in<br />- /openrisc/trunk/or1ksim/testsuite/test-code-or1k/int-logger/int-logger-edge.c<br />- /openrisc/trunk/or1ksim/testsuite/test-code-or1k/int-logger/int-logger-level.c<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/int-logger/Makefile.am<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/int-logger/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/int-test/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/kbdtest/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/local-global/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/loop/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-async/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-common/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-dram/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-ssram/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-sync/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mem-test/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mmu/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mul/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mycompress/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/support/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/support/spr-defs.h<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/testfloat/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/tick/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/uos/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/upcalls/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-iftest/Makefile.in<br />- /openrisc/trunk/or1ksim/testsuite/test-code/lib-inttest/lib-inttest-edge.c<br />- /openrisc/trunk/or1ksim/testsuite/test-code/lib-inttest/lib-inttest-level.c<br />~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-inttest/Makefile.am<br />~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-inttest/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-jtag/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-upcalls/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code/Makefile.in<br />~ /openrisc/trunk/or1ksim/tick/Makefile.in<br />~ /openrisc/trunk/or1ksim/vapi/Makefile.in<br />
jeremybennett
Thu, 25 Nov 2010 15:29:36 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1ksim%2F&rev=432
-
or1ksim - clarifying interrupt behavior in code and documentation.
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1ksim%2F&rev=430
<div><strong>Rev 430 - julius</strong> (7 file(s) modified)</div><div>or1ksim - clarifying interrupt behavior in code and documentation.</div>~ /openrisc/trunk/or1ksim/ChangeLog<br />~ /openrisc/trunk/or1ksim/cpu/common/execute.h<br />~ /openrisc/trunk/or1ksim/cpu/or1k/sprs.c<br />~ /openrisc/trunk/or1ksim/doc/or1ksim.info<br />~ /openrisc/trunk/or1ksim/doc/or1ksim.texi<br />~ /openrisc/trunk/or1ksim/doc/version.texi<br />~ /openrisc/trunk/or1ksim/pic/pic.c<br />
julius
Mon, 22 Nov 2010 18:51:41 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1ksim%2F&rev=430
-
or1ksim update - remove debug printfs from eth MDIO emulation ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1ksim%2F&rev=429
<div><strong>Rev 429 - julius</strong> (4 file(s) modified)</div><div>or1ksim update - remove debug printfs from eth MDIO emulation ...</div>~ /openrisc/trunk/or1ksim/ChangeLog<br />~ /openrisc/trunk/or1ksim/cpu/or32/generate.c<br />~ /openrisc/trunk/or1ksim/doc/or1ksim.info<br />~ /openrisc/trunk/or1ksim/peripheral/eth.c<br />
julius
Mon, 22 Nov 2010 15:24:12 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1ksim%2F&rev=429
-
or1ksim - adding preliminary PHY emulation to ethernet peripheral.
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1ksim%2F&rev=428
<div><strong>Rev 428 - julius</strong> (83 file(s) modified)</div><div>or1ksim - adding preliminary PHY emulation to ethernet peripheral.</div>~ /openrisc/trunk/or1ksim/aclocal.m4<br />~ /openrisc/trunk/or1ksim/argtable2/Makefile.in<br />~ /openrisc/trunk/or1ksim/autom4te.cache/output.0<br />~ /openrisc/trunk/or1ksim/autom4te.cache/output.1<br />~ /openrisc/trunk/or1ksim/autom4te.cache/traces.0<br />~ /openrisc/trunk/or1ksim/autom4te.cache/traces.1<br />~ /openrisc/trunk/or1ksim/bpb/Makefile.in<br />~ /openrisc/trunk/or1ksim/cache/Makefile.in<br />~ /openrisc/trunk/or1ksim/ChangeLog<br />~ /openrisc/trunk/or1ksim/configure<br />~ /openrisc/trunk/or1ksim/cpu/common/Makefile.in<br />~ /openrisc/trunk/or1ksim/cpu/dlx/Makefile.in<br />~ /openrisc/trunk/or1ksim/cpu/Makefile.in<br />~ /openrisc/trunk/or1ksim/cpu/or1k/Makefile.in<br />~ /openrisc/trunk/or1ksim/cpu/or32/Makefile.in<br />~ /openrisc/trunk/or1ksim/cuc/Makefile.in<br />~ /openrisc/trunk/or1ksim/debug/Makefile.in<br />~ /openrisc/trunk/or1ksim/doc/Makefile.in<br />~ /openrisc/trunk/or1ksim/doc/or1ksim.texi<br />~ /openrisc/trunk/or1ksim/doc/version.texi<br />~ /openrisc/trunk/or1ksim/Makefile.in<br />~ /openrisc/trunk/or1ksim/mmu/Makefile.in<br />~ /openrisc/trunk/or1ksim/peripheral/channels/Makefile.in<br />~ /openrisc/trunk/or1ksim/peripheral/eth.c<br />~ /openrisc/trunk/or1ksim/peripheral/eth.h<br />~ /openrisc/trunk/or1ksim/peripheral/Makefile.in<br />~ /openrisc/trunk/or1ksim/pic/Makefile.in<br />~ /openrisc/trunk/or1ksim/pm/Makefile.in<br />~ /openrisc/trunk/or1ksim/port/Makefile.in<br />~ /openrisc/trunk/or1ksim/softfloat/Makefile.in<br />~ /openrisc/trunk/or1ksim/support/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/config/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/lib/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/libsim.tests/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/or1ksim.tests/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/aclocal.m4<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/acv-gpio/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/acv-uart/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/basic/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/cache/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/cbasic/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/cfg/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/dhry/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/dmatest/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/eth/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/except-test/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/except/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/exit/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ext/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/fbtest/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/flag/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/fp/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/functest/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/inst-set-test/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/int-logger/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/int-test/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/kbdtest/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/local-global/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/loop/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-async/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-common/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-dram/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-ssram/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-sync/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mem-test/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mmu/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mul/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mycompress/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/support/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/testfloat/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/tick/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/uos/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/upcalls/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-iftest/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-inttest/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-jtag/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-upcalls/Makefile.in<br />~ /openrisc/trunk/or1ksim/testsuite/test-code/Makefile.in<br />~ /openrisc/trunk/or1ksim/tick/Makefile.in<br />~ /openrisc/trunk/or1ksim/vapi/Makefile.in<br />
julius
Fri, 19 Nov 2010 19:38:03 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1ksim%2F&rev=428
-
New feature to trace instructions (option --trace). Manual updated to ...
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1ksim%2F&rev=420
<div><strong>Rev 420 - jeremybennett</strong> (17 file(s) modified)</div><div>New feature to trace instructions (option --trace). Manual updated to ...</div>~ /openrisc/trunk/or1ksim/ChangeLog<br />~ /openrisc/trunk/or1ksim/configure<br />~ /openrisc/trunk/or1ksim/configure.ac<br />~ /openrisc/trunk/or1ksim/cpu/common/abstract.c<br />~ /openrisc/trunk/or1ksim/cpu/common/abstract.h<br />~ /openrisc/trunk/or1ksim/cpu/common/execute.h<br />~ /openrisc/trunk/or1ksim/cpu/or1k/opcode/or32.h<br />~ /openrisc/trunk/or1ksim/cpu/or32/execute.c<br />~ /openrisc/trunk/or1ksim/cpu/or32/or32.c<br />~ /openrisc/trunk/or1ksim/doc/or1ksim.info<br />~ /openrisc/trunk/or1ksim/doc/or1ksim.texi<br />~ /openrisc/trunk/or1ksim/doc/version.texi<br />~ /openrisc/trunk/or1ksim/libtoplevel.c<br />~ /openrisc/trunk/or1ksim/NEWS<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure.ac<br />
jeremybennett
Thu, 11 Nov 2010 14:43:33 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1ksim%2F&rev=420
-
Or1ksim - adding new option when configuring memories, "exitnops"
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1ksim%2F&rev=418
<div><strong>Rev 418 - julius</strong> (8 file(s) modified)</div><div>Or1ksim - adding new option when configuring memories, "exitnops"</div>~ /openrisc/trunk/or1ksim/autom4te.cache/output.0<br />~ /openrisc/trunk/or1ksim/autom4te.cache/traces.0<br />~ /openrisc/trunk/or1ksim/ChangeLog<br />~ /openrisc/trunk/or1ksim/doc/or1ksim.info<br />~ /openrisc/trunk/or1ksim/doc/or1ksim.texi<br />~ /openrisc/trunk/or1ksim/doc/version.texi<br />~ /openrisc/trunk/or1ksim/peripheral/memory.c<br />~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure<br />
julius
Thu, 11 Nov 2010 11:51:01 +0100
https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2For1ksim%2F&rev=418
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