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        <link>https://opencores.org/websvn//websvn/listing?repname=openrisc&amp;path=%2Fopenrisc%2Ftrunk%2For1ksim%2Fconfig.h.in&amp;</link>
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        <item>
            <title>Changes to support Or1ksim 0.5.0rc1

Top level changes:

	* config.h.in: Regenerated.
	* debug. ...</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=openrisc&amp;path=%2Fopenrisc%2Ftrunk%2For1ksim%2F&amp;rev=346</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 346 - jeremybennett&lt;/strong&gt; (102 file(s) modified)&lt;/div&gt;&lt;div&gt;Changes to support Or1ksim 0.5.0rc1&lt;br /&gt;
&lt;br /&gt;
Top level changes:&lt;br /&gt;
&lt;br /&gt;
	* config.h.in: Regenerated.&lt;br /&gt;
	* debug.cfg, ...&lt;/div&gt;~ /openrisc/trunk/or1ksim/aclocal.m4&lt;br /&gt;~ /openrisc/trunk/or1ksim/argtable2/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/bpb/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cache/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/ChangeLog&lt;br /&gt;~ /openrisc/trunk/or1ksim/config.h.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/configure&lt;br /&gt;~ /openrisc/trunk/or1ksim/configure.ac&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/common/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/dlx/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/or1k/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/or32/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cuc/Makefile.in&lt;br /&gt;- /openrisc/trunk/or1ksim/debug.cfg&lt;br /&gt;~ /openrisc/trunk/or1ksim/debug/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/doc/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/doc/or1ksim.info&lt;br /&gt;~ /openrisc/trunk/or1ksim/doc/or1ksim.texi&lt;br /&gt;~ /openrisc/trunk/or1ksim/doc/version.texi&lt;br /&gt;~ /openrisc/trunk/or1ksim/Makefile.am&lt;br /&gt;~ /openrisc/trunk/or1ksim/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/mmu/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/NEWS&lt;br /&gt;~ /openrisc/trunk/or1ksim/or1ksim.h&lt;br /&gt;~ /openrisc/trunk/or1ksim/peripheral/channels/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/peripheral/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/pic/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/pm/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/port/Makefile.in&lt;br /&gt;- /openrisc/trunk/or1ksim/rsp.cfg&lt;br /&gt;~ /openrisc/trunk/or1ksim/sim-config.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/sim.cfg&lt;br /&gt;~ /openrisc/trunk/or1ksim/softfloat/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/support/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/ChangeLog&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/config/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/lib/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/libsim.tests/int-edge.exp&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/libsim.tests/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/or1ksim.tests/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/aclocal.m4&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/acv-gpio/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/acv-uart/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/basic/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/cache/cache-asm.S&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/cache/cache.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/cache/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/cbasic/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/cfg/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/config.h.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure.ac&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/dhry/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/dmatest/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/eth/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/except-test/except-test-s.S&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/except-test/except-test.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/except-test/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/except/except.S&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/except/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/exit/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ext/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/fbtest/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/flag/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/fp/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/functest/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/inst-set-test/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/int-logger/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/int-test/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/kbdtest/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/local-global/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/loop/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-async/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-common/except-mc.S&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-common/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-dram/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-ssram/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-sync/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mem-test/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mmu/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mmu/mmu-asm.S&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mmu/mmu.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mul/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mycompress/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/support/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/testfloat/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/testfloat/systfloat.S&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/tick/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/uos/except-or32.S&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/uos/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/upcalls/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-iftest/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-inttest/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-jtag/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-upcalls/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/tick/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/vapi/Makefile.in&lt;br /&gt;</description>
            <author>jeremybennett</author>
            <pubDate>Tue, 07 Sep 2010 11:55:53 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=openrisc&amp;path=%2Fopenrisc%2Ftrunk%2For1ksim%2F&amp;rev=346</guid>
        </item>
        <item>
            <title>Terminate execution on NOP_EXIT, even if debugging, add support for ...</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=openrisc&amp;path=%2Fopenrisc%2Ftrunk%2For1ksim%2F&amp;rev=236</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 236 - jeremybennett&lt;/strong&gt; (89 file(s) modified)&lt;/div&gt;&lt;div&gt;Terminate execution on NOP_EXIT, even if debugging, add support for ...&lt;/div&gt;~ /openrisc/trunk/or1ksim/aclocal.m4&lt;br /&gt;~ /openrisc/trunk/or1ksim/argtable2/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/bpb/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cache/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/ChangeLog&lt;br /&gt;~ /openrisc/trunk/or1ksim/config.h.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/configure&lt;br /&gt;~ /openrisc/trunk/or1ksim/configure.ac&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/common/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/dlx/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/or1k/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/or32/insnset.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/or32/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cuc/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/debug/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/debug/rsp-server.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/doc/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/doc/or1ksim.info&lt;br /&gt;~ /openrisc/trunk/or1ksim/doc/version.texi&lt;br /&gt;~ /openrisc/trunk/or1ksim/libtoplevel.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/mmu/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/peripheral/channels/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/peripheral/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/pic/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/pm/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/port/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/softfloat/host.h&lt;br /&gt;~ /openrisc/trunk/or1ksim/softfloat/Makefile.am&lt;br /&gt;~ /openrisc/trunk/or1ksim/softfloat/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/softfloat/README&lt;br /&gt;~ /openrisc/trunk/or1ksim/softfloat/softfloat-macros&lt;br /&gt;~ /openrisc/trunk/or1ksim/support/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/config/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/lib/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/libsim.tests/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/or1ksim.tests/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/aclocal.m4&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/acv-gpio/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/acv-uart/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/basic/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/cache/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/cbasic/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/cfg/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/config.h.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure.ac&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/dhry/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/dmatest/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/eth/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/except-test/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/except/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/exit/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ext/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/fbtest/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/flag/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/fp/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/functest/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/inst-set-test/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/int-logger/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/int-test/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/kbdtest/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/local-global/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/loop/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-async/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-common/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-dram/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-ssram/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-sync/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mem-test/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mmu/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mul/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mycompress/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/support/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/testfloat/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/tick/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/uos/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/upcalls/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-iftest/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-inttest/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-jtag/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-upcalls/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/tick/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/vapi/Makefile.in&lt;br /&gt;</description>
            <author>jeremybennett</author>
            <pubDate>Wed, 04 Aug 2010 16:24:21 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=openrisc&amp;path=%2Fopenrisc%2Ftrunk%2For1ksim%2F&amp;rev=236</guid>
        </item>
        <item>
            <title>Removed support for old OpenRISC JTAG Remote Protocol.</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=openrisc&amp;path=%2Fopenrisc%2Ftrunk%2For1ksim%2F&amp;rev=235</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 235 - jeremybennett&lt;/strong&gt; (93 file(s) modified)&lt;/div&gt;&lt;div&gt;Removed support for old OpenRISC JTAG Remote Protocol.&lt;/div&gt;~ /openrisc/trunk/or1ksim/aclocal.m4&lt;br /&gt;~ /openrisc/trunk/or1ksim/argtable2/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/bpb/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cache/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/ChangeLog&lt;br /&gt;~ /openrisc/trunk/or1ksim/config.h.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/configure&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/common/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/dlx/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/or1k/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/or32/execute.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/or32/insnset.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/or32/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cuc/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/debug/debug-unit.c&lt;br /&gt;- /openrisc/trunk/or1ksim/debug/gdbcomm.c&lt;br /&gt;- /openrisc/trunk/or1ksim/debug/gdbcomm.h&lt;br /&gt;~ /openrisc/trunk/or1ksim/debug/Makefile.am&lt;br /&gt;~ /openrisc/trunk/or1ksim/debug/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/doc/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/doc/or1ksim.info&lt;br /&gt;~ /openrisc/trunk/or1ksim/doc/or1ksim.texi&lt;br /&gt;~ /openrisc/trunk/or1ksim/doc/version.texi&lt;br /&gt;~ /openrisc/trunk/or1ksim/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/mmu/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/peripheral/channels/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/peripheral/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/pic/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/pm/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/port/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/sim-cmd.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/sim-config.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/sim-config.h&lt;br /&gt;~ /openrisc/trunk/or1ksim/softfloat/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/support/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/ChangeLog&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/config/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/lib/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/libsim.tests/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/or1ksim.tests/eth.cfg&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/or1ksim.tests/kbdtest.cfg&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/or1ksim.tests/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/aclocal.m4&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/acv-gpio/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/acv-uart/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/basic/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/cache/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/cbasic/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/cfg/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/config.h.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/dhry/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/dmatest/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/eth/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/except-test/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/except/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/exit/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ext/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/fbtest/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/flag/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/fp/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/functest/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/inst-set-test/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/int-logger/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/int-test/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/kbdtest/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/local-global/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/loop/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-async/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-common/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-dram/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-ssram/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-sync/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mem-test/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mmu/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mul/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mycompress/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/support/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/testfloat/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/tick/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/uos/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/upcalls/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-iftest/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-inttest/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-jtag/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-upcalls/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/tick/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/toplevel-support.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/vapi/Makefile.in&lt;br /&gt;</description>
            <author>jeremybennett</author>
            <pubDate>Wed, 04 Aug 2010 11:42:24 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=openrisc&amp;path=%2Fopenrisc%2Ftrunk%2For1ksim%2F&amp;rev=235</guid>
        </item>
        <item>
            <title>Minor tidy ups. DOS end of line chars fixed.</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=openrisc&amp;path=%2Fopenrisc%2Ftrunk%2For1ksim%2F&amp;rev=234</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 234 - jeremybennett&lt;/strong&gt; (115 file(s) modified)&lt;/div&gt;&lt;div&gt;Minor tidy ups. DOS end of line chars fixed.&lt;/div&gt;~ /openrisc/trunk/or1ksim/aclocal.m4&lt;br /&gt;~ /openrisc/trunk/or1ksim/argtable2/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/bpb/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cache/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/ChangeLog&lt;br /&gt;~ /openrisc/trunk/or1ksim/config.h.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/configure&lt;br /&gt;~ /openrisc/trunk/or1ksim/configure.ac&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/common/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/dlx/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/or1k/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/or32/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cuc/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/debug/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/doc/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/doc/or1ksim.info&lt;br /&gt;~ /openrisc/trunk/or1ksim/doc/version.texi&lt;br /&gt;~ /openrisc/trunk/or1ksim/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/mmu/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/peripheral/channels/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/peripheral/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/pic/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/pm/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/port/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/softfloat/host.h&lt;br /&gt;~ /openrisc/trunk/or1ksim/softfloat/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/softfloat/milieu.h&lt;br /&gt;~ /openrisc/trunk/or1ksim/softfloat/softfloat.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/softfloat/softfloat.h&lt;br /&gt;~ /openrisc/trunk/or1ksim/support/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/ChangeLog&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/config/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/lib/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/libsim.tests/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/or1ksim.tests/Makefile.am&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/or1ksim.tests/Makefile.in&lt;br /&gt;- /openrisc/trunk/or1ksim/testsuite/or1ksim.tests/testfloat.cfg&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/or1ksim.tests/testfloat.exp&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/README&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/aclocal.m4&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/acv-gpio/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/acv-uart/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/basic/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/cache/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/cbasic/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/cfg/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/config.h.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure.ac&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/dhry/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/dmatest/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/eth/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/except-test/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/except/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/exit/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ext/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/fbtest/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/flag/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/fp/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/functest/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/inst-set-test/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/int-logger/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/int-test/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/kbdtest/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/local-global/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/loop/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-async/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-common/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-dram/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-ssram/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-sync/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mem-test/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mmu/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mul/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mycompress/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/support/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/testfloat/fail.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/testfloat/fail.h&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/testfloat/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/testfloat/milieu.h&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/testfloat/random.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/testfloat/random.h&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/testfloat/slowfloat.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/testfloat/slowfloat.h&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/testfloat/softfloat.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/testfloat/softfloat.h&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/testfloat/systflags.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/testfloat/systflags.h&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/testfloat/systfloat.h&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/testfloat/systmodes.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/testfloat/systmodes.h&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/testfloat/testCases.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/testfloat/testCases.h&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/testfloat/testfloat.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/testfloat/testFunction.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/testfloat/testFunction.h&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/testfloat/testLoops.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/testfloat/testLoops.h&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/testfloat/testsoftfloat.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/testfloat/writeHex.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/testfloat/writeHex.h&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/tick/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/uos/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/upcalls/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-iftest/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-inttest/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-jtag/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-upcalls/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/tick/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/vapi/Makefile.in&lt;br /&gt;</description>
            <author>jeremybennett</author>
            <pubDate>Tue, 03 Aug 2010 10:10:12 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=openrisc&amp;path=%2Fopenrisc%2Ftrunk%2For1ksim%2F&amp;rev=234</guid>
        </item>
        <item>
            <title>New softfloat FPU and testfloat sw for or1ksim</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=openrisc&amp;path=%2Fopenrisc%2Ftrunk%2For1ksim%2F&amp;rev=233</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 233 - julius&lt;/strong&gt; (137 file(s) modified)&lt;/div&gt;&lt;div&gt;New softfloat FPU and testfloat sw for or1ksim&lt;/div&gt;~ /openrisc/trunk/or1ksim/aclocal.m4&lt;br /&gt;~ /openrisc/trunk/or1ksim/argtable2/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/autom4te.cache/output.0&lt;br /&gt;~ /openrisc/trunk/or1ksim/autom4te.cache/output.1&lt;br /&gt;~ /openrisc/trunk/or1ksim/autom4te.cache/traces.0&lt;br /&gt;~ /openrisc/trunk/or1ksim/autom4te.cache/traces.1&lt;br /&gt;~ /openrisc/trunk/or1ksim/bpb/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cache/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/ChangeLog&lt;br /&gt;~ /openrisc/trunk/or1ksim/config.h.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/configure&lt;br /&gt;~ /openrisc/trunk/or1ksim/configure.ac&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/common/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/dlx/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/or1k/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/or1k/spr-defs.h&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/or32/execute.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/or32/insnset.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/or32/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cuc/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/debug/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/doc/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/doc/or1ksim.info&lt;br /&gt;~ /openrisc/trunk/or1ksim/doc/version.texi&lt;br /&gt;~ /openrisc/trunk/or1ksim/Makefile.am&lt;br /&gt;~ /openrisc/trunk/or1ksim/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/mmu/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/peripheral/channels/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/peripheral/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/pic/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/pm/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/port/Makefile.in&lt;br /&gt;+ /openrisc/trunk/or1ksim/softfloat&lt;br /&gt;+ /openrisc/trunk/or1ksim/softfloat/host.h&lt;br /&gt;+ /openrisc/trunk/or1ksim/softfloat/Makefile.am&lt;br /&gt;+ /openrisc/trunk/or1ksim/softfloat/Makefile.in&lt;br /&gt;+ /openrisc/trunk/or1ksim/softfloat/milieu.h&lt;br /&gt;+ /openrisc/trunk/or1ksim/softfloat/README&lt;br /&gt;+ /openrisc/trunk/or1ksim/softfloat/softfloat-macros&lt;br /&gt;+ /openrisc/trunk/or1ksim/softfloat/softfloat-specialize&lt;br /&gt;+ /openrisc/trunk/or1ksim/softfloat/softfloat.c&lt;br /&gt;+ /openrisc/trunk/or1ksim/softfloat/softfloat.h&lt;br /&gt;~ /openrisc/trunk/or1ksim/support/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/config/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/lib/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/libsim.tests/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/or1ksim.tests/fp.cfg&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/or1ksim.tests/fp.exp&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/or1ksim.tests/Makefile.in&lt;br /&gt;+ /openrisc/trunk/or1ksim/testsuite/or1ksim.tests/testfloat.cfg&lt;br /&gt;+ /openrisc/trunk/or1ksim/testsuite/or1ksim.tests/testfloat.exp&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/aclocal.m4&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/acv-gpio/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/acv-uart/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/basic/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/cache/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/cbasic/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/cfg/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/config.h.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure.ac&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/default.ld&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/dhry/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/dmatest/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/eth/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/except-test/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/except/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/exit/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ext/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/fbtest/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/flag/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/fp/fp.S&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/fp/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/functest/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/inst-set-test/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/int-logger/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/int-test/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/kbdtest/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/local-global/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/loop/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/Makefile.am&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-async/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-common/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-dram/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-ssram/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-sync/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mem-test/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mmu/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mul/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mycompress/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/support/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/support/spr-defs.h&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/support/support.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/support/support.h&lt;br /&gt;+ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/testfloat&lt;br /&gt;+ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/testfloat/fail.c&lt;br /&gt;+ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/testfloat/fail.h&lt;br /&gt;+ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/testfloat/Makefile.am&lt;br /&gt;+ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/testfloat/Makefile.in&lt;br /&gt;+ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/testfloat/milieu.h&lt;br /&gt;+ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/testfloat/or1k-gcc.h&lt;br /&gt;+ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/testfloat/random.c&lt;br /&gt;+ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/testfloat/random.h&lt;br /&gt;+ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/testfloat/README&lt;br /&gt;+ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/testfloat/slowfloat.c&lt;br /&gt;+ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/testfloat/slowfloat.h&lt;br /&gt;+ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/testfloat/softfloat.c&lt;br /&gt;+ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/testfloat/softfloat.h&lt;br /&gt;+ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/testfloat/systflags.c&lt;br /&gt;+ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/testfloat/systflags.h&lt;br /&gt;+ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/testfloat/systfloat.h&lt;br /&gt;+ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/testfloat/systfloat.S&lt;br /&gt;+ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/testfloat/systmodes.c&lt;br /&gt;+ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/testfloat/systmodes.h&lt;br /&gt;+ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/testfloat/testCases.c&lt;br /&gt;+ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/testfloat/testCases.h&lt;br /&gt;+ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/testfloat/testfloat.c&lt;br /&gt;+ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/testfloat/testFunction.c&lt;br /&gt;+ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/testfloat/testFunction.h&lt;br /&gt;+ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/testfloat/testLoops.c&lt;br /&gt;+ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/testfloat/testLoops.h&lt;br /&gt;+ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/testfloat/testsoftfloat.c&lt;br /&gt;+ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/testfloat/writeHex.c&lt;br /&gt;+ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/testfloat/writeHex.h&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/tick/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/uos/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/upcalls/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-iftest/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-inttest/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-jtag/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-upcalls/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/tick/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/vapi/Makefile.in&lt;br /&gt;</description>
            <author>julius</author>
            <pubDate>Mon, 02 Aug 2010 23:25:25 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=openrisc&amp;path=%2Fopenrisc%2Ftrunk%2For1ksim%2F&amp;rev=233</guid>
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        <item>
            <title>Changed library interface. Fixed namespace problems with instruction lookup in ...</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=openrisc&amp;path=%2Fopenrisc%2Ftrunk%2For1ksim%2F&amp;rev=230</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 230 - jeremybennett&lt;/strong&gt; (56 file(s) modified)&lt;/div&gt;&lt;div&gt;Changed library interface. Fixed namespace problems with instruction lookup in ...&lt;/div&gt;~ /openrisc/trunk/or1ksim/aclocal.m4&lt;br /&gt;~ /openrisc/trunk/or1ksim/argtable2/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/bpb/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cache/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/ChangeLog&lt;br /&gt;~ /openrisc/trunk/or1ksim/config.h.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/configure&lt;br /&gt;~ /openrisc/trunk/or1ksim/configure.ac&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/common/abstract.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/common/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/common/parse.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/common/stats.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/dlx/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/or1k/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/or1k/opcode/or32.h&lt;br /&gt;- /openrisc/trunk/or1ksim/cpu/or32/execute-fp.h&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/or32/execute.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/or32/generate.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/or32/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/or32/or32.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/cuc/cuc.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/cuc/load.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/cuc/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/debug/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/doc/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/doc/or1ksim.info&lt;br /&gt;~ /openrisc/trunk/or1ksim/doc/version.texi&lt;br /&gt;~ /openrisc/trunk/or1ksim/libtoplevel.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/mmu/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/or1ksim.h&lt;br /&gt;~ /openrisc/trunk/or1ksim/peripheral/channels/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/peripheral/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/pic/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/pm/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/port/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/support/dumpverilog.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/support/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/config/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/lib/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/libsim.tests/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/or1ksim.tests/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure.ac&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/support/spr-defs.h&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-iftest/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-inttest/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-jtag/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-upcalls/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/tick/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/toplevel-support.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/vapi/Makefile.in&lt;br /&gt;</description>
            <author>jeremybennett</author>
            <pubDate>Sun, 01 Aug 2010 18:29:47 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=openrisc&amp;path=%2Fopenrisc%2Ftrunk%2For1ksim%2F&amp;rev=230</guid>
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            <title>Orksim floating point support additions, spr-defs.h updates, newlib cache init ...</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=openrisc&amp;path=%2Fopenrisc%2Ftrunk%2For1ksim%2F&amp;rev=226</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 226 - julius&lt;/strong&gt; (54 file(s) modified)&lt;/div&gt;&lt;div&gt;Orksim floating point support additions, spr-defs.h updates, newlib cache init ...&lt;/div&gt;~ /openrisc/trunk/gnu-src/newlib-1.18.0/libgloss/ChangeLog&lt;br /&gt;~ /openrisc/trunk/gnu-src/newlib-1.18.0/libgloss/or32/crt0.S&lt;br /&gt;~ /openrisc/trunk/gnu-src/newlib-1.18.0/libgloss/or32/or1ksim-board.h&lt;br /&gt;~ /openrisc/trunk/gnu-src/newlib-1.18.0/libgloss/or32/spr-defs.h&lt;br /&gt;~ /openrisc/trunk/or1ksim/aclocal.m4&lt;br /&gt;~ /openrisc/trunk/or1ksim/argtable2/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/autom4te.cache/output.0&lt;br /&gt;~ /openrisc/trunk/or1ksim/autom4te.cache/output.1&lt;br /&gt;~ /openrisc/trunk/or1ksim/autom4te.cache/requests&lt;br /&gt;~ /openrisc/trunk/or1ksim/autom4te.cache/traces.0&lt;br /&gt;~ /openrisc/trunk/or1ksim/autom4te.cache/traces.1&lt;br /&gt;~ /openrisc/trunk/or1ksim/bpb/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cache/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/ChangeLog&lt;br /&gt;~ /openrisc/trunk/or1ksim/config.h.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/configure&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/common/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/dlx/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/or1k/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/or1k/spr-defs.h&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/or1k/sprs.c&lt;br /&gt;+ /openrisc/trunk/or1ksim/cpu/or32/execute-fp.h&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/or32/execute.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/or32/generate.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/or32/insnset.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/or32/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/or32/simpl32-defs.h&lt;br /&gt;~ /openrisc/trunk/or1ksim/cuc/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/debug/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/doc/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/doc/or1ksim.info&lt;br /&gt;~ /openrisc/trunk/or1ksim/doc/version.texi&lt;br /&gt;~ /openrisc/trunk/or1ksim/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/mmu/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/peripheral/channels/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/peripheral/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/pic/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/pm/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/port/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/support/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/config/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/lib/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/libsim.tests/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/or1ksim.tests/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/support/spr-defs.h&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-iftest/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-inttest/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-jtag/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-upcalls/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/tick/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/vapi/Makefile.in&lt;br /&gt;</description>
            <author>julius</author>
            <pubDate>Fri, 30 Jul 2010 18:06:55 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=openrisc&amp;path=%2Fopenrisc%2Ftrunk%2For1ksim%2F&amp;rev=226</guid>
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            <title>Updated library interface to take a full command line (this ...</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=openrisc&amp;path=%2Fopenrisc%2Ftrunk%2For1ksim%2F&amp;rev=220</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 220 - jeremybennett&lt;/strong&gt; (28 file(s) modified)&lt;/div&gt;&lt;div&gt;Updated library interface to take a full command line (this ...&lt;/div&gt;~ /openrisc/trunk/or1ksim/ChangeLog&lt;br /&gt;~ /openrisc/trunk/or1ksim/config.h.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/configure&lt;br /&gt;~ /openrisc/trunk/or1ksim/configure.ac&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/common/abstract.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/common/parse.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/or1k/opcode/or32.h&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/or32/generate.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/or32/insnset.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/or32/or32.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/doc/or1ksim.info&lt;br /&gt;~ /openrisc/trunk/or1ksim/doc/version.texi&lt;br /&gt;~ /openrisc/trunk/or1ksim/libtoplevel.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/or1ksim.h&lt;br /&gt;~ /openrisc/trunk/or1ksim/pic/pic.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/sim-config.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/sim-config.h&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/ChangeLog&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/libsim.tests/jtag-write-control.exp&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/libsim.tests/upcalls.exp&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/or1ksim.tests/except-test.exp&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-iftest/lib-iftest.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-inttest/lib-inttest-edge.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-inttest/lib-inttest-level.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-jtag/lib-jtag-full.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-jtag/lib-jtag.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-upcalls/lib-upcalls.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/toplevel-support.c&lt;br /&gt;</description>
            <author>jeremybennett</author>
            <pubDate>Fri, 23 Jul 2010 19:15:28 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=openrisc&amp;path=%2Fopenrisc%2Ftrunk%2For1ksim%2F&amp;rev=220</guid>
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            <title>Adding executed log in binary format capability to or1ksim</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=openrisc&amp;path=%2Fopenrisc%2Ftrunk%2For1ksim%2F&amp;rev=202</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 202 - julius&lt;/strong&gt; (14 file(s) modified)&lt;/div&gt;&lt;div&gt;Adding executed log in binary format capability to or1ksim&lt;/div&gt;~ /openrisc/trunk/or1ksim/autom4te.cache/output.0&lt;br /&gt;~ /openrisc/trunk/or1ksim/autom4te.cache/requests&lt;br /&gt;~ /openrisc/trunk/or1ksim/autom4te.cache/traces.0&lt;br /&gt;~ /openrisc/trunk/or1ksim/ChangeLog&lt;br /&gt;~ /openrisc/trunk/or1ksim/config.h.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/common/execute.h&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/or32/execute.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/doc/or1ksim.info&lt;br /&gt;~ /openrisc/trunk/or1ksim/doc/or1ksim.texi&lt;br /&gt;~ /openrisc/trunk/or1ksim/doc/version.texi&lt;br /&gt;~ /openrisc/trunk/or1ksim/sim-config.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/sim-config.h&lt;br /&gt;~ /openrisc/trunk/or1ksim/toplevel-support.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/toplevel.c&lt;br /&gt;</description>
            <author>julius</author>
            <pubDate>Sat, 17 Jul 2010 15:14:01 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=openrisc&amp;path=%2Fopenrisc%2Ftrunk%2For1ksim%2F&amp;rev=202</guid>
        </item>
        <item>
            <title>New config option to allow l.xori with unsigned operand.</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=openrisc&amp;path=%2Fopenrisc%2Ftrunk%2For1ksim%2F&amp;rev=127</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 127 - jeremybennett&lt;/strong&gt; (14 file(s) modified)&lt;/div&gt;&lt;div&gt;New config option to allow l.xori with unsigned operand.&lt;/div&gt;~ /openrisc/trunk/or1ksim/ChangeLog&lt;br /&gt;~ /openrisc/trunk/or1ksim/config.h.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/configure&lt;br /&gt;~ /openrisc/trunk/or1ksim/configure.ac&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/or32/insnset.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/or32/or32.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/doc/or1ksim.info&lt;br /&gt;~ /openrisc/trunk/or1ksim/doc/or1ksim.texi&lt;br /&gt;~ /openrisc/trunk/or1ksim/doc/version.texi&lt;br /&gt;~ /openrisc/trunk/or1ksim/NEWS&lt;br /&gt;~ /openrisc/trunk/or1ksim/README&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure.ac&lt;br /&gt;</description>
            <author>jeremybennett</author>
            <pubDate>Wed, 16 Jun 2010 14:23:06 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=openrisc&amp;path=%2Fopenrisc%2Ftrunk%2For1ksim%2F&amp;rev=127</guid>
        </item>
        <item>
            <title>Overflow handling now in line with architecture manual. Tests added.</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=openrisc&amp;path=%2Fopenrisc%2Ftrunk%2For1ksim%2F&amp;rev=124</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 124 - jeremybennett&lt;/strong&gt; (22 file(s) modified)&lt;/div&gt;&lt;div&gt;Overflow handling now in line with architecture manual. Tests added.&lt;/div&gt;~ /openrisc/trunk/or1ksim/ChangeLog&lt;br /&gt;~ /openrisc/trunk/or1ksim/config.h.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/configure&lt;br /&gt;~ /openrisc/trunk/or1ksim/configure.ac&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/common/execute.h&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/or32/execute.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/or32/insnset.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/doc/or1ksim.info&lt;br /&gt;~ /openrisc/trunk/or1ksim/doc/or1ksim.texi&lt;br /&gt;~ /openrisc/trunk/or1ksim/doc/version.texi&lt;br /&gt;~ /openrisc/trunk/or1ksim/NEWS&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/ChangeLog&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/or1ksim.tests/inst-set-test.exp&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/README&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog&lt;br /&gt;+ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/inst-set-test/is-and-test.S&lt;br /&gt;+ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/inst-set-test/is-or-test.S&lt;br /&gt;+ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/inst-set-test/is-shift-test.S&lt;br /&gt;+ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/inst-set-test/is-sub-test.S&lt;br /&gt;+ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/inst-set-test/is-xor-test.S&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/inst-set-test/Makefile.am&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/inst-set-test/Makefile.in&lt;br /&gt;</description>
            <author>jeremybennett</author>
            <pubDate>Tue, 15 Jun 2010 18:41:00 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=openrisc&amp;path=%2Fopenrisc%2Ftrunk%2For1ksim%2F&amp;rev=124</guid>
        </item>
        <item>
            <title>Adds exception handling to l.jalr and l.jr. Adds appropriate tests.</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=openrisc&amp;path=%2Fopenrisc%2Ftrunk%2For1ksim%2F&amp;rev=121</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 121 - jeremybennett&lt;/strong&gt; (88 file(s) modified)&lt;/div&gt;&lt;div&gt;Adds exception handling to l.jalr and l.jr. Adds appropriate tests.&lt;/div&gt;~ /openrisc/trunk/or1ksim/aclocal.m4&lt;br /&gt;~ /openrisc/trunk/or1ksim/argtable2/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/bpb/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cache/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/ChangeLog&lt;br /&gt;~ /openrisc/trunk/or1ksim/config.h.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/configure&lt;br /&gt;~ /openrisc/trunk/or1ksim/configure.ac&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/common/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/dlx/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/or1k/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/or32/generate.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/or32/insnset.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/or32/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cuc/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/debug/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/doc/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/doc/or1ksim.info&lt;br /&gt;~ /openrisc/trunk/or1ksim/doc/version.texi&lt;br /&gt;~ /openrisc/trunk/or1ksim/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/mmu/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/NEWS&lt;br /&gt;~ /openrisc/trunk/or1ksim/peripheral/channels/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/peripheral/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/pic/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/pm/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/port/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/support/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/ChangeLog&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/config/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/lib/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/libsim.tests/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/or1ksim.tests/inst-set-test.exp&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/or1ksim.tests/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/README&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/aclocal.m4&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/acv-gpio/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/acv-uart/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/basic/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/cache/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/cbasic/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/cfg/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/config.h.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/dhry/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/dmatest/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/eth/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/except-test/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/except/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/exit/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ext/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/fbtest/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/flag/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/fp/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/functest/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/inst-set-test/inst-set-test.S&lt;br /&gt;+ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/inst-set-test/is-jump-test.S&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/inst-set-test/Makefile.am&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/inst-set-test/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/int-logger/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/int-test/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/kbdtest/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/local-global/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/loop/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-async/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-common/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-dram/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-ssram/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-sync/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mem-test/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mmu/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mul/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mycompress/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/support/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/tick/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/uos/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/upcalls/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-iftest/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-inttest/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-jtag/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-upcalls/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/tick/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/vapi/Makefile.in&lt;br /&gt;</description>
            <author>jeremybennett</author>
            <pubDate>Mon, 14 Jun 2010 18:01:01 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=openrisc&amp;path=%2Fopenrisc%2Ftrunk%2For1ksim%2F&amp;rev=121</guid>
        </item>
        <item>
            <title>New tests of multiply. Improved tests of exception handling for ...</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=openrisc&amp;path=%2Fopenrisc%2Ftrunk%2For1ksim%2F&amp;rev=118</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 118 - jeremybennett&lt;/strong&gt; (95 file(s) modified)&lt;/div&gt;&lt;div&gt;New tests of multiply. Improved tests of exception handling for ...&lt;/div&gt;~ /openrisc/trunk/or1ksim/aclocal.m4&lt;br /&gt;~ /openrisc/trunk/or1ksim/argtable2/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/bpb/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cache/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/ChangeLog&lt;br /&gt;~ /openrisc/trunk/or1ksim/config.h.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/configure&lt;br /&gt;~ /openrisc/trunk/or1ksim/configure.ac&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/common/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/dlx/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/or1k/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/or32/generate.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/or32/insnset.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/or32/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/or32/or32.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/cuc/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/debug/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/doc/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/doc/or1ksim.info&lt;br /&gt;~ /openrisc/trunk/or1ksim/doc/version.texi&lt;br /&gt;~ /openrisc/trunk/or1ksim/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/mmu/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/NEWS&lt;br /&gt;~ /openrisc/trunk/or1ksim/peripheral/channels/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/peripheral/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/pic/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/pm/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/port/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/support/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/ChangeLog&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/config/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/lib/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/libsim.tests/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/or1ksim.tests/inst-set-test.exp&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/or1ksim.tests/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/README&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/aclocal.m4&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/acv-gpio/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/acv-uart/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/basic/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/cache/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/cbasic/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/cfg/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/config.h.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/dhry/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/dmatest/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/eth/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/except-test/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/except/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/exit/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ext/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/fbtest/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/flag/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/fp/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/functest/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/inst-set-test/inst-set-test.h&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/inst-set-test/inst-set-test.S&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/inst-set-test/is-add-test.S&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/inst-set-test/is-div-test.S&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/inst-set-test/is-find-test.S&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/inst-set-test/is-lws-test.S&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/inst-set-test/is-mac-test.S&lt;br /&gt;+ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/inst-set-test/is-mul-test.S&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/inst-set-test/Makefile.am&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/inst-set-test/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/int-logger/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/int-test/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/kbdtest/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/local-global/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/loop/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-async/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-common/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-dram/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-ssram/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-sync/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mem-test/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mmu/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mul/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mycompress/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/support/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/tick/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/uos/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/upcalls/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-iftest/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-inttest/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-jtag/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-upcalls/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/tick/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/vapi/Makefile.in&lt;br /&gt;</description>
            <author>jeremybennett</author>
            <pubDate>Sun, 13 Jun 2010 21:07:24 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=openrisc&amp;path=%2Fopenrisc%2Ftrunk%2For1ksim%2F&amp;rev=118</guid>
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            <title>Tidy ups to Ethernet test fixes. new tests for l.add. ...</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=openrisc&amp;path=%2Fopenrisc%2Ftrunk%2For1ksim%2F&amp;rev=112</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 112 - jeremybennett&lt;/strong&gt; (28 file(s) modified)&lt;/div&gt;&lt;div&gt;Tidy ups to Ethernet test fixes. new tests for l.add. ...&lt;/div&gt;~ /openrisc/trunk/or1ksim/ChangeLog&lt;br /&gt;~ /openrisc/trunk/or1ksim/config.h.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/configure&lt;br /&gt;~ /openrisc/trunk/or1ksim/configure.ac&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/common/execute.h&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/or32/insnset.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/doc/or1ksim.info&lt;br /&gt;~ /openrisc/trunk/or1ksim/doc/or1ksim.texi&lt;br /&gt;~ /openrisc/trunk/or1ksim/doc/version.texi&lt;br /&gt;~ /openrisc/trunk/or1ksim/peripheral/Makefile.am&lt;br /&gt;~ /openrisc/trunk/or1ksim/peripheral/Makefile.in&lt;br /&gt;+ /openrisc/trunk/or1ksim/peripheral/mc-defines.h&lt;br /&gt;~ /openrisc/trunk/or1ksim/peripheral/mc.h&lt;br /&gt;- /openrisc/trunk/or1ksim/peripheral/mc_defines.h&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/ChangeLog&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/or1ksim.tests/inst-set-test.exp&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/README&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog&lt;br /&gt;+ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/eth/fields.h&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/eth/Makefile.am&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/eth/Makefile.in&lt;br /&gt;+ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/inst-set-test/is-add-test.S&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/inst-set-test/Makefile.am&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/inst-set-test/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-async/mc-async.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-dram/mc-dram.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-ssram/mc-ssram.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-sync/mc-sync.c&lt;br /&gt;</description>
            <author>jeremybennett</author>
            <pubDate>Wed, 09 Jun 2010 18:24:44 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=openrisc&amp;path=%2Fopenrisc%2Ftrunk%2For1ksim%2F&amp;rev=112</guid>
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            <title>ChangeLog updated for floating point support. Fixed bug in generic ...</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=openrisc&amp;path=%2Fopenrisc%2Ftrunk%2For1ksim%2F&amp;rev=101</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 101 - jeremybennett&lt;/strong&gt; (79 file(s) modified)&lt;/div&gt;&lt;div&gt;ChangeLog updated for floating point support. Fixed bug in generic ...&lt;/div&gt;~ /openrisc/trunk/or1ksim/aclocal.m4&lt;br /&gt;~ /openrisc/trunk/or1ksim/argtable2/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/bpb/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cache/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/ChangeLog&lt;br /&gt;~ /openrisc/trunk/or1ksim/config.h.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/configure&lt;br /&gt;~ /openrisc/trunk/or1ksim/configure.ac&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/common/abstract.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/common/labels.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/common/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/dlx/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/or1k/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/or32/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cuc/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/debug/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/doc/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/doc/or1ksim.texi&lt;br /&gt;~ /openrisc/trunk/or1ksim/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/mmu/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/peripheral/channels/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/peripheral/generic.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/peripheral/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/pic/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/pm/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/port/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/support/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/config/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/lib/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/libsim.tests/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/or1ksim.tests/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/aclocal.m4&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/acv-gpio/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/acv-uart/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/basic/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/cache/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/cbasic/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/cfg/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/config.h.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/dhry/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/dmatest/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/eth/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/except-test/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/except/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/exit/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ext/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/fbtest/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/flag/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/functest/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/inst-set-test/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/int-logger/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/int-test/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/kbdtest/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/local-global/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/loop/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-async/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-common/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-dram/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-ssram/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-sync/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mem-test/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mmu/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mul/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mycompress/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/support/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/tick/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/uos/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/upcalls/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-iftest/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-inttest/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-jtag/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-upcalls/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/tick/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/vapi/Makefile.in&lt;br /&gt;</description>
            <author>jeremybennett</author>
            <pubDate>Tue, 25 May 2010 16:27:58 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=openrisc&amp;path=%2Fopenrisc%2Ftrunk%2For1ksim%2F&amp;rev=101</guid>
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            <title>Comprehensive testing of the library JTAG interface. Updates to the ...</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=openrisc&amp;path=%2Fopenrisc%2Ftrunk%2For1ksim%2F&amp;rev=98</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 98 - jeremybennett&lt;/strong&gt; (105 file(s) modified)&lt;/div&gt;&lt;div&gt;Comprehensive testing of the library JTAG interface. Updates to the ...&lt;/div&gt;~ /openrisc/trunk/or1ksim/aclocal.m4&lt;br /&gt;~ /openrisc/trunk/or1ksim/argtable2/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/bpb/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cache/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/ChangeLog&lt;br /&gt;~ /openrisc/trunk/or1ksim/config.h.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/configure&lt;br /&gt;~ /openrisc/trunk/or1ksim/configure.ac&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/common/abstract.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/common/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/dlx/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/or1k/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/or1k/sprs.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/or32/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cuc/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/debug/jtag.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/debug/jtag.h&lt;br /&gt;~ /openrisc/trunk/or1ksim/debug/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/doc/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/doc/or1ksim.info&lt;br /&gt;~ /openrisc/trunk/or1ksim/doc/or1ksim.texi&lt;br /&gt;~ /openrisc/trunk/or1ksim/doc/version.texi&lt;br /&gt;~ /openrisc/trunk/or1ksim/libtoplevel.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/mmu/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/or1ksim.h&lt;br /&gt;~ /openrisc/trunk/or1ksim/peripheral/channels/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/peripheral/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/peripheral/mc.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/pic/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/pm/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/port/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/sim-config.h&lt;br /&gt;~ /openrisc/trunk/or1ksim/support/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/ChangeLog&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/config/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/lib/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/libsim.tests/default.cfg&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/libsim.tests/jtag-basic.exp&lt;br /&gt;- /openrisc/trunk/or1ksim/testsuite/libsim.tests/jtag-full.exp&lt;br /&gt;+ /openrisc/trunk/or1ksim/testsuite/libsim.tests/jtag-go-command-read.exp&lt;br /&gt;+ /openrisc/trunk/or1ksim/testsuite/libsim.tests/jtag-go-command-write.exp&lt;br /&gt;+ /openrisc/trunk/or1ksim/testsuite/libsim.tests/jtag-read-command.exp&lt;br /&gt;+ /openrisc/trunk/or1ksim/testsuite/libsim.tests/jtag-read-control.exp&lt;br /&gt;+ /openrisc/trunk/or1ksim/testsuite/libsim.tests/jtag-select-module.exp&lt;br /&gt;+ /openrisc/trunk/or1ksim/testsuite/libsim.tests/jtag-write-command.exp&lt;br /&gt;+ /openrisc/trunk/or1ksim/testsuite/libsim.tests/jtag-write-control.exp&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/libsim.tests/Makefile.am&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/libsim.tests/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/or1ksim.tests/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/README&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/aclocal.m4&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/acv-gpio/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/acv-uart/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/basic/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/cache/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/cbasic/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/cfg/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ChangeLog&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/config.h.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/dhry/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/dmatest/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/eth/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/except-test/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/except/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/exit/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ext/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/fbtest/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/flag/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/functest/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/inst-set-test/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/int-logger/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/int-test/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/kbdtest/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/local-global/Makefile.in&lt;br /&gt;+ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/loop/loop-init.c&lt;br /&gt;+ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/loop/loop-report.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/loop/Makefile.am&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/loop/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-async/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-common/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-dram/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-ssram/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-sync/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mem-test/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mmu/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mul/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mycompress/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/support/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/tick/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/uos/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/upcalls/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-iftest/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-inttest/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-jtag/lib-jtag-full.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-jtag/lib-jtag.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-jtag/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-upcalls/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/tick/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/vapi/Makefile.in&lt;br /&gt;</description>
            <author>jeremybennett</author>
            <pubDate>Wed, 19 May 2010 15:09:42 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=openrisc&amp;path=%2Fopenrisc%2Ftrunk%2For1ksim%2F&amp;rev=98</guid>
        </item>
        <item>
            <title>Updates to test the new JTAG library interface (not yet ...</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=openrisc&amp;path=%2Fopenrisc%2Ftrunk%2For1ksim%2F&amp;rev=97</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 97 - jeremybennett&lt;/strong&gt; (89 file(s) modified)&lt;/div&gt;&lt;div&gt;Updates to test the new JTAG library interface (not yet ...&lt;/div&gt;~ /openrisc/trunk/or1ksim/aclocal.m4&lt;br /&gt;~ /openrisc/trunk/or1ksim/argtable2/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/bpb/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cache/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/ChangeLog&lt;br /&gt;~ /openrisc/trunk/or1ksim/config.h.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/configure&lt;br /&gt;~ /openrisc/trunk/or1ksim/configure.ac&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/common/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/dlx/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/or1k/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/or32/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cuc/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/debug/jtag.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/debug/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/doc/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/libtoplevel.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/mmu/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/peripheral/channels/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/peripheral/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/pic/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/pm/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/port/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/support/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/ChangeLog&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/config/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/lib/Makefile.in&lt;br /&gt;+ /openrisc/trunk/or1ksim/testsuite/libsim.tests/jtag-basic.exp&lt;br /&gt;+ /openrisc/trunk/or1ksim/testsuite/libsim.tests/jtag-full.exp&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/libsim.tests/Makefile.am&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/libsim.tests/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/libsim.tests/upcalls.cfg&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/or1ksim.tests/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/README&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/aclocal.m4&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/acv-gpio/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/acv-uart/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/basic/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/cache/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/cbasic/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/cfg/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/config.h.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/dhry/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/dmatest/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/eth/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/except-test/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/except/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/exit/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/ext/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/fbtest/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/flag/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/functest/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/inst-set-test/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/int-logger/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/int-test/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/kbdtest/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/local-global/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/loop/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-async/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-common/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-dram/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-ssram/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mc-sync/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mem-test/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mmu/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mul/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/mycompress/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/support/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/tick/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/uos/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code-or1k/upcalls/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-iftest/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-inttest/Makefile.in&lt;br /&gt;+ /openrisc/trunk/or1ksim/testsuite/test-code/lib-jtag&lt;br /&gt;+ /openrisc/trunk/or1ksim/testsuite/test-code/lib-jtag/lib-jtag-full.c&lt;br /&gt;+ /openrisc/trunk/or1ksim/testsuite/test-code/lib-jtag/lib-jtag.c&lt;br /&gt;+ /openrisc/trunk/or1ksim/testsuite/test-code/lib-jtag/Makefile.am&lt;br /&gt;+ /openrisc/trunk/or1ksim/testsuite/test-code/lib-jtag/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-upcalls/lib-upcalls.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-upcalls/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code/Makefile.am&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/tick/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/vapi/Makefile.in&lt;br /&gt;</description>
            <author>jeremybennett</author>
            <pubDate>Wed, 05 May 2010 09:07:45 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=openrisc&amp;path=%2Fopenrisc%2Ftrunk%2For1ksim%2F&amp;rev=97</guid>
        </item>
        <item>
            <title>Various changes which had not been picked up in earlier ...</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=openrisc&amp;path=%2Fopenrisc%2Ftrunk%2For1ksim%2F&amp;rev=96</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 96 - jeremybennett&lt;/strong&gt; (34 file(s) modified)&lt;/div&gt;&lt;div&gt;Various changes which had not been picked up in earlier ...&lt;/div&gt;~ /openrisc/trunk/or1ksim/aclocal.m4&lt;br /&gt;~ /openrisc/trunk/or1ksim/argtable2/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/bpb/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cache/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/ChangeLog&lt;br /&gt;~ /openrisc/trunk/or1ksim/config.h.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/configure&lt;br /&gt;~ /openrisc/trunk/or1ksim/configure.ac&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/common/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/dlx/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/or1k/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/or32/generate.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/or32/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cuc/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cuc/verilog.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/debug/jtag.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/debug/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/doc/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/doc/or1ksim.info&lt;br /&gt;~ /openrisc/trunk/or1ksim/doc/version.texi&lt;br /&gt;~ /openrisc/trunk/or1ksim/ltmain.sh&lt;br /&gt;~ /openrisc/trunk/or1ksim/m4/ltversion.m4&lt;br /&gt;~ /openrisc/trunk/or1ksim/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/mmu/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/peripheral/channels/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/peripheral/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/pic/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/pm/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/port/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/port/strndup.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/support/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/tick/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/vapi/Makefile.in&lt;br /&gt;</description>
            <author>jeremybennett</author>
            <pubDate>Tue, 04 May 2010 07:45:17 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=openrisc&amp;path=%2Fopenrisc%2Ftrunk%2For1ksim%2F&amp;rev=96</guid>
        </item>
        <item>
            <title>Tidy up of some obsolete configuration code.</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=openrisc&amp;path=%2Fopenrisc%2Ftrunk%2For1ksim%2F&amp;rev=91</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 91 - jeremybennett&lt;/strong&gt; (32 file(s) modified)&lt;/div&gt;&lt;div&gt;Tidy up of some obsolete configuration code.&lt;/div&gt;~ /openrisc/trunk/or1ksim/argtable2/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/bpb/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cache/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/config.h.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/configure&lt;br /&gt;~ /openrisc/trunk/or1ksim/configure.ac&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/common/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/dlx/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/or1k/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/or32/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cuc/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/debug/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/doc/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/mmu/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/peripheral/channels/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/peripheral/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/pic/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/pm/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/port/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/support/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/config/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/lib/Makefile.am&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/lib/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/libsim.tests/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/or1ksim.tests/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code/lib-iftest/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/testsuite/test-code/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/tick/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/vapi/Makefile.in&lt;br /&gt;</description>
            <author>jeremybennett</author>
            <pubDate>Wed, 21 Apr 2010 18:40:17 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=openrisc&amp;path=%2Fopenrisc%2Ftrunk%2For1ksim%2F&amp;rev=91</guid>
        </item>
        <item>
            <title>Major restructuring of the testbench, now named testsuite to bring ...</title>
            <link>https://opencores.org/websvn//websvn/revision?repname=openrisc&amp;path=%2Fopenrisc%2Ftrunk%2For1ksim%2F&amp;rev=82</link>
            <description>&lt;div&gt;&lt;strong&gt;Rev 82 - jeremybennett&lt;/strong&gt; (521 file(s) modified)&lt;/div&gt;&lt;div&gt;Major restructuring of the testbench, now named testsuite to bring ...&lt;/div&gt;~ /openrisc/trunk/or1ksim/aclocal.m4&lt;br /&gt;~ /openrisc/trunk/or1ksim/argtable2/argtable2.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/argtable2/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/bpb/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cache/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/ChangeLog&lt;br /&gt;~ /openrisc/trunk/or1ksim/compile&lt;br /&gt;~ /openrisc/trunk/or1ksim/config.guess&lt;br /&gt;~ /openrisc/trunk/or1ksim/config.h.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/config.sub&lt;br /&gt;~ /openrisc/trunk/or1ksim/configure&lt;br /&gt;~ /openrisc/trunk/or1ksim/configure.ac&lt;br /&gt;~ /openrisc/trunk/or1ksim/COPYING&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/common/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/common/parse.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/dlx/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/or1k/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/or1k/spr-defs.h&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/or32/execute.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/or32/generate.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/or32/insnset.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/cpu/or32/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cuc/bb.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/cuc/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/cuc/timings.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/debug/debug-unit.c&lt;br /&gt;+ /openrisc/trunk/or1ksim/debug/jtag.c&lt;br /&gt;+ /openrisc/trunk/or1ksim/debug/jtag.h&lt;br /&gt;~ /openrisc/trunk/or1ksim/debug/Makefile.am&lt;br /&gt;~ /openrisc/trunk/or1ksim/debug/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/depcomp&lt;br /&gt;~ /openrisc/trunk/or1ksim/doc/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/doc/mdate-sh&lt;br /&gt;~ /openrisc/trunk/or1ksim/doc/or1ksim.info&lt;br /&gt;~ /openrisc/trunk/or1ksim/doc/or1ksim.texi&lt;br /&gt;~ /openrisc/trunk/or1ksim/doc/texinfo.tex&lt;br /&gt;~ /openrisc/trunk/or1ksim/doc/version.texi&lt;br /&gt;~ /openrisc/trunk/or1ksim/INSTALL&lt;br /&gt;~ /openrisc/trunk/or1ksim/install-sh&lt;br /&gt;~ /openrisc/trunk/or1ksim/libtoplevel.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/ltmain.sh&lt;br /&gt;+ /openrisc/trunk/or1ksim/m4&lt;br /&gt;+ /openrisc/trunk/or1ksim/m4/libtool.m4&lt;br /&gt;+ /openrisc/trunk/or1ksim/m4/ltoptions.m4&lt;br /&gt;+ /openrisc/trunk/or1ksim/m4/ltsugar.m4&lt;br /&gt;+ /openrisc/trunk/or1ksim/m4/ltversion.m4&lt;br /&gt;+ /openrisc/trunk/or1ksim/m4/lt~obsolete.m4&lt;br /&gt;+ /openrisc/trunk/or1ksim/m4/m4&lt;br /&gt;+ /openrisc/trunk/or1ksim/m4/m4/libtool.m4&lt;br /&gt;+ /openrisc/trunk/or1ksim/m4/m4/ltoptions.m4&lt;br /&gt;+ /openrisc/trunk/or1ksim/m4/m4/ltsugar.m4&lt;br /&gt;+ /openrisc/trunk/or1ksim/m4/m4/ltversion.m4&lt;br /&gt;+ /openrisc/trunk/or1ksim/m4/m4/lt~obsolete.m4&lt;br /&gt;~ /openrisc/trunk/or1ksim/Makefile.am&lt;br /&gt;~ /openrisc/trunk/or1ksim/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/missing&lt;br /&gt;~ /openrisc/trunk/or1ksim/mkinstalldirs&lt;br /&gt;~ /openrisc/trunk/or1ksim/mmu/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/or1ksim.h&lt;br /&gt;~ /openrisc/trunk/or1ksim/peripheral/atadevice-cmdi.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/peripheral/atadevice.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/peripheral/channels/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/peripheral/channels/xterm.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/peripheral/eth.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/peripheral/eth.h&lt;br /&gt;~ /openrisc/trunk/or1ksim/peripheral/generic.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/peripheral/gpio.c&lt;br /&gt;~ /openrisc/trunk/or1ksim/peripheral/gpio.h&lt;br /&gt;~ /openrisc/trunk/or1ksim/peripheral/Makefile.in&lt;br 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/openrisc/trunk/or1ksim/testsuite/testsuite/test-code/uos/except-or32.S&lt;br /&gt;+ /openrisc/trunk/or1ksim/testsuite/testsuite/test-code/uos/ipc.h&lt;br /&gt;+ /openrisc/trunk/or1ksim/testsuite/testsuite/test-code/uos/Makefile.am&lt;br /&gt;+ /openrisc/trunk/or1ksim/testsuite/testsuite/test-code/uos/Makefile.in&lt;br /&gt;+ /openrisc/trunk/or1ksim/testsuite/testsuite/test-code/uos/README&lt;br /&gt;+ /openrisc/trunk/or1ksim/testsuite/testsuite/test-code/uos/task.c&lt;br /&gt;+ /openrisc/trunk/or1ksim/testsuite/testsuite/test-code/uos/tick.c&lt;br /&gt;+ /openrisc/trunk/or1ksim/testsuite/testsuite/test-code/uos/uos.c&lt;br /&gt;+ /openrisc/trunk/or1ksim/testsuite/testsuite/test-code/uos/uos.h&lt;br /&gt;~ /openrisc/trunk/or1ksim/tick/Makefile.in&lt;br /&gt;~ /openrisc/trunk/or1ksim/vapi/Makefile.in&lt;br /&gt;</description>
            <author>jeremybennett</author>
            <pubDate>Tue, 20 Apr 2010 18:16:05 +0100</pubDate>
            <guid>https://opencores.org/websvn//websvn/revision?repname=openrisc&amp;path=%2Fopenrisc%2Ftrunk%2For1ksim%2F&amp;rev=82</guid>
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