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openrisc WebSVN RSS feed - openrisc https://opencores.org/websvn//websvn/listing?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fbench%2Fsysc%2Finclude%2FOrpsocAccess.h& Sun, 05 Apr 2026 02:57:34 +0100 FeedCreator 1.7.2 ORPSoC SystemC wrapper updates, monitor output more similar to or1ksim. RAM ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fbench%2Fsysc%2Finclude%2F&rev=462 <div>Rev 462 - julius (53 file(s) modified)</div><div>ORPSoC SystemC wrapper updates, monitor output more similar to or1ksim. RAM ...</div>~ /openrisc/trunk/orpsocv2/bench/sysc/include/coff.h ~ /openrisc/trunk/orpsocv2/bench/sysc/include/DebugUnitSC.h ~ /openrisc/trunk/orpsocv2/bench/sysc/include/elf.h ~ /openrisc/trunk/orpsocv2/bench/sysc/include/GdbServerSC.h ~ /openrisc/trunk/orpsocv2/bench/sysc/include/JtagDriverSC.h ~ /openrisc/trunk/orpsocv2/bench/sysc/include/JtagSC.h ~ /openrisc/trunk/orpsocv2/bench/sysc/include/JtagSC_includes.h ~ /openrisc/trunk/orpsocv2/bench/sysc/include/MemCache.h ~ /openrisc/trunk/orpsocv2/bench/sysc/include/MemoryLoad.h ~ /openrisc/trunk/orpsocv2/bench/sysc/include/MpHash.h ~ /openrisc/trunk/orpsocv2/bench/sysc/include/Or1200MonitorSC.h ~ /openrisc/trunk/orpsocv2/bench/sysc/include/OrpsocAccess.h ~ /openrisc/trunk/orpsocv2/bench/sysc/include/OrpsocMain.h ~ /openrisc/trunk/orpsocv2/bench/sysc/include/ResetSC.h ~ /openrisc/trunk/orpsocv2/bench/sysc/include/RspConnection.h ~ /openrisc/trunk/orpsocv2/bench/sysc/include/RspPacket.h ~ /openrisc/trunk/orpsocv2/bench/sysc/include/SprCache.h ~ /openrisc/trunk/orpsocv2/bench/sysc/include/TapAction.h ~ /openrisc/trunk/orpsocv2/bench/sysc/include/TapActionDRScan.h ~ /openrisc/trunk/orpsocv2/bench/sysc/include/TapActionIRScan.h ~ /openrisc/trunk/orpsocv2/bench/sysc/include/TapActionReset.h ~ /openrisc/trunk/orpsocv2/bench/sysc/include/TapStateMachine.h ~ /openrisc/trunk/orpsocv2/bench/sysc/include/TraceSC.h ~ /openrisc/trunk/orpsocv2/bench/sysc/include/UartSC.h ~ /openrisc/trunk/orpsocv2/bench/sysc/include/Utils.h ~ /openrisc/trunk/orpsocv2/bench/sysc/src/DebugUnitSC.cpp ~ /openrisc/trunk/orpsocv2/bench/sysc/src/GdbServerSC.cpp ~ /openrisc/trunk/orpsocv2/bench/sysc/src/JtagDriverSC.cpp ~ /openrisc/trunk/orpsocv2/bench/sysc/src/JtagSC.cpp ~ /openrisc/trunk/orpsocv2/bench/sysc/src/MemCache.cpp ~ /openrisc/trunk/orpsocv2/bench/sysc/src/MemoryLoad.cpp ~ /openrisc/trunk/orpsocv2/bench/sysc/src/MpHash.cpp ~ /openrisc/trunk/orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp ~ /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocAccess.cpp ~ /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocMain.cpp ~ /openrisc/trunk/orpsocv2/bench/sysc/src/ResetSC.cpp ~ /openrisc/trunk/orpsocv2/bench/sysc/src/RspConnection.cpp ~ /openrisc/trunk/orpsocv2/bench/sysc/src/RspPacket.cpp ~ /openrisc/trunk/orpsocv2/bench/sysc/src/SprCache.cpp ~ /openrisc/trunk/orpsocv2/bench/sysc/src/TapAction.cpp ~ /openrisc/trunk/orpsocv2/bench/sysc/src/TapActionDRScan.cpp ~ /openrisc/trunk/orpsocv2/bench/sysc/src/TapActionIRScan.cpp ~ /openrisc/trunk/orpsocv2/bench/sysc/src/TapActionReset.cpp ~ /openrisc/trunk/orpsocv2/bench/sysc/src/TapStateMachine.cpp ~ /openrisc/trunk/orpsocv2/bench/sysc/src/TraceSC.cpp ~ /openrisc/trunk/orpsocv2/bench/sysc/src/UartSC.cpp ~ /openrisc/trunk/orpsocv2/bench/sysc/src/Utils.cpp ~ /openrisc/trunk/orpsocv2/rtl/verilog/include/or1200_defines.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_dpram.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_rfram_generic.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/ram_wb/ram_wb_b3.v + /openrisc/trunk/orpsocv2/sw/tests/or1200/board/or1200-mmu.c ~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-mmu.c julius Fri, 07 Jan 2011 06:51:10 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fbench%2Fsysc%2Finclude%2F&rev=462 ORPSoC update Ethernet MAC synthesis issues with Actel Synplify D-2009.12A Ethernet MAC ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fbench%2Fsysc%2Finclude%2F&rev=439 <div>Rev 439 - julius (45 file(s) modified)</div><div>ORPSoC update Ethernet MAC synthesis issues with Actel Synplify D-2009.12A Ethernet MAC ...</div>~ /openrisc/trunk/orpsocv2/bench/sysc/include/OrpsocAccess.h ~ /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocAccess.cpp ~ /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v ~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/backend/par/bin/Makefile ~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/bench/verilog/include/eth_stim.v ~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include/ethmac_defines.v ~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/include/orpsoc-params.v ~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/orpsoc_top/orpsoc_top.v ~ /openrisc/trunk/orpsocv2/boards/actel/ordb1a3pe1500/syn/synplify/bin/Makefile ~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/bench/verilog/include/eth_stim.v ~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/include/ethmac_defines.v ~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/orpsoc_top/orpsoc_top.v ~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/xilinx_ddr2/xilinx_ddr2.v ~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/xilinx_ddr2/xilinx_ddr2_if.v ~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/sw/board/include/board.h ~ /openrisc/trunk/orpsocv2/boards/xilinx/ml501/syn/xst/bin/Makefile ~ /openrisc/trunk/orpsocv2/doc/orpsoc.texi ~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/ethmac.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_clockgen.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_fifo.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_miim.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_receivecontrol.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_registers.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_rxcounters.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_rxethmac.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_rxstatem.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_shiftreg.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_spram_256x32.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_transmitcontrol.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_txcounters.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_txethmac.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_wishbone.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/include/ethmac_defines.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/orpsoc_top/orpsoc_top.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/ram_wb/ram_wb.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/ram_wb/ram_wb_b3.v ~ /openrisc/trunk/orpsocv2/sw/drivers/or1200/link.ld ~ /openrisc/trunk/orpsocv2/sw/tests/ethmac/sim/ethmac-rx.c ~ /openrisc/trunk/orpsocv2/sw/tests/ethmac/sim/ethmac-rxtx.c ~ /openrisc/trunk/orpsocv2/sw/tests/ethmac/sim/ethmac-tx.c + /openrisc/trunk/orpsocv2/sw/tests/or1200/board/or1200-div.c + /openrisc/trunk/orpsocv2/sw/tests/or1200/board/or1200-mul.c ~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-dctest.c ~ /openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-mmu.c + /openrisc/trunk/orpsocv2/sw/tests/uart/sim/uart-interruptloopback.c julius Mon, 06 Dec 2010 15:22:50 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fbench%2Fsysc%2Finclude%2F&rev=439 ORPSoC's RTL code fixed to pass linting by Verilator. ORPSoC's debug ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fbench%2Fsysc%2Finclude%2F&rev=363 <div>Rev 363 - julius (38 file(s) modified)</div><div>ORPSoC's RTL code fixed to pass linting by Verilator. ORPSoC's debug ...</div>~ /openrisc/trunk/orpsocv2/bench/sysc/include/OrpsocAccess.h ~ /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocAccess.cpp ~ /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocMain.cpp ~ /openrisc/trunk/orpsocv2/rtl/verilog/arbiter/arbiter_ibus.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/clkgen/clkgen.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_cpu.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_if.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/dbg_if/dbg_wb.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/include/dbg_cpu_defines.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/include/dbg_wb_defines.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/include/or1200_defines.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/include/orpsoc-defines.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/jtag_tap/jtag_tap.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_alu.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_ctrl.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_dc_fsm.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_dmmu_top.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_du.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_except.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_freeze.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_genpc.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_lsu.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_mult_mac.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_operandmuxes.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_reg2mem.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_sprs.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_top.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_wbmux.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200/or1200_wb_biu.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/orpsoc_top/orpsoc_top.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart_receiver.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart_regs.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart_rfifo.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart_tfifo.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/uart16550/uart_transmitter.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/wb_ram_b3/wb_ram_b3.v ~ /openrisc/trunk/orpsocv2/sim/bin/Makefile ~ /openrisc/trunk/orpsocv2/sw/dhry/Makefile julius Sun, 12 Sep 2010 07:57:53 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fbench%2Fsysc%2Finclude%2F&rev=363 ORPSoCv2 verilator building working again. Board build fixes to follow https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fbench%2Fsysc%2Finclude%2F&rev=362 <div>Rev 362 - julius (7 file(s) modified)</div><div>ORPSoCv2 verilator building working again. Board build fixes to follow</div>~ /openrisc/trunk/orpsocv2/bench/sysc/include/OrpsocAccess.h ~ /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocAccess.cpp ~ /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocMain.cpp ~ /openrisc/trunk/orpsocv2/rtl/verilog/arbiter/arbiter_dbus.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/clkgen/clkgen.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/wb_ram_b3/wb_ram_b3.v ~ /openrisc/trunk/orpsocv2/sim/bin/Makefile julius Fri, 10 Sep 2010 22:42:38 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fbench%2Fsysc%2Finclude%2F&rev=362 OR1200 RTL and ORPSoCv2 update, fixing Verilator build capability. ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fbench%2Fsysc%2Finclude%2F&rev=353 <div>Rev 353 - julius (19 file(s) modified)</div><div>OR1200 RTL and ORPSoCv2 update, fixing Verilator build capability. * or1200/rtl/verilog/or1200_sprs.v: ...</div>~ /openrisc/trunk/bootloaders/orpmon/config.mk ~ /openrisc/trunk/bootloaders/orpmon/flash.ld ~ /openrisc/trunk/bootloaders/orpmon/include/build.h ~ /openrisc/trunk/bootloaders/orpmon/ram.ld ~ /openrisc/trunk/bootloaders/orpmon/reset.S ~ /openrisc/trunk/docs/openrisc1200_supplementary_prm.odt ~ /openrisc/trunk/or1200/rtl/verilog/or1200_ctrl.v ~ /openrisc/trunk/or1200/rtl/verilog/or1200_except.v ~ /openrisc/trunk/or1200/rtl/verilog/or1200_sprs.v ~ /openrisc/trunk/orpsocv2/bench/sysc/include/Or1200MonitorSC.h ~ /openrisc/trunk/orpsocv2/bench/sysc/include/OrpsocAccess.h ~ /openrisc/trunk/orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp ~ /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocAccess.cpp ~ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_ctrl.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_except.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200/or1200_sprs.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/components/wb_ram_b3/wb_ram_b3.v ~ /openrisc/trunk/or_debug_proxy/Makefile ~ /openrisc/trunk/or_debug_proxy/src/gdb.c julius Wed, 08 Sep 2010 15:42:13 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fbench%2Fsysc%2Finclude%2F&rev=353 Fixed the simulator-assisted printf l.nop in cycle accurate, and supporting ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fbench%2Fsysc%2Finclude%2F&rev=66 <div>Rev 66 - julius (8 file(s) modified)</div><div>Fixed the simulator-assisted printf l.nop in cycle accurate, and supporting ...</div>~ /openrisc/trunk/orpsocv2/bench/sysc/include/Or1200MonitorSC.h ~ /openrisc/trunk/orpsocv2/bench/sysc/include/OrpsocAccess.h ~ /openrisc/trunk/orpsocv2/bench/sysc/src/GdbServerSC.cpp ~ /openrisc/trunk/orpsocv2/bench/sysc/src/MemoryLoad.cpp ~ /openrisc/trunk/orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp ~ /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocAccess.cpp ~ /openrisc/trunk/orpsocv2/sim/bin/Makefile ~ /openrisc/trunk/orpsocv2/sw/support/support.c julius Wed, 27 Jan 2010 10:49:09 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fbench%2Fsysc%2Finclude%2F&rev=66 Finally adding RSP server to cycle accurate model, based on ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fbench%2Fsysc%2Finclude%2F&rev=63 <div>Rev 63 - julius (49 file(s) modified)</div><div>Finally adding RSP server to cycle accurate model, based on ...</div>+ /openrisc/trunk/orpsocv2/bench/sysc/include/DebugUnitSC.h + /openrisc/trunk/orpsocv2/bench/sysc/include/GdbServerSC.h + /openrisc/trunk/orpsocv2/bench/sysc/include/JtagDriverSC.h + /openrisc/trunk/orpsocv2/bench/sysc/include/JtagSC.h + /openrisc/trunk/orpsocv2/bench/sysc/include/jtagsc.h + /openrisc/trunk/orpsocv2/bench/sysc/include/MemCache.h + /openrisc/trunk/orpsocv2/bench/sysc/include/MpHash.h ~ /openrisc/trunk/orpsocv2/bench/sysc/include/Or1200MonitorSC.h ~ /openrisc/trunk/orpsocv2/bench/sysc/include/OrpsocAccess.h ~ /openrisc/trunk/orpsocv2/bench/sysc/include/OrpsocMain.h + /openrisc/trunk/orpsocv2/bench/sysc/include/RspConnection.h + /openrisc/trunk/orpsocv2/bench/sysc/include/RspPacket.h + /openrisc/trunk/orpsocv2/bench/sysc/include/SprCache.h + /openrisc/trunk/orpsocv2/bench/sysc/include/TapAction.h + /openrisc/trunk/orpsocv2/bench/sysc/include/TapActionDRScan.h + /openrisc/trunk/orpsocv2/bench/sysc/include/TapActionIRScan.h + /openrisc/trunk/orpsocv2/bench/sysc/include/TapActionReset.h + /openrisc/trunk/orpsocv2/bench/sysc/include/TapStateMachine.h ~ /openrisc/trunk/orpsocv2/bench/sysc/include/UartSC.h + /openrisc/trunk/orpsocv2/bench/sysc/include/Utils.h + /openrisc/trunk/orpsocv2/bench/sysc/src/DebugUnitSC.cpp + /openrisc/trunk/orpsocv2/bench/sysc/src/GdbServerSC.cpp + /openrisc/trunk/orpsocv2/bench/sysc/src/JtagDriverSC.cpp + /openrisc/trunk/orpsocv2/bench/sysc/src/JtagSC.cpp + /openrisc/trunk/orpsocv2/bench/sysc/src/MemCache.cpp ~ /openrisc/trunk/orpsocv2/bench/sysc/src/MemoryLoad.cpp ~ /openrisc/trunk/orpsocv2/bench/sysc/src/Modules.make + /openrisc/trunk/orpsocv2/bench/sysc/src/MpHash.cpp ~ /openrisc/trunk/orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp ~ /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocAccess.cpp ~ /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocMain.cpp + /openrisc/trunk/orpsocv2/bench/sysc/src/RspConnection.cpp + /openrisc/trunk/orpsocv2/bench/sysc/src/RspPacket.cpp + /openrisc/trunk/orpsocv2/bench/sysc/src/SprCache.cpp + /openrisc/trunk/orpsocv2/bench/sysc/src/TapAction.cpp + /openrisc/trunk/orpsocv2/bench/sysc/src/TapActionDRScan.cpp + /openrisc/trunk/orpsocv2/bench/sysc/src/TapActionIRScan.cpp + /openrisc/trunk/orpsocv2/bench/sysc/src/TapActionReset.cpp + /openrisc/trunk/orpsocv2/bench/sysc/src/TapStateMachine.cpp + /openrisc/trunk/orpsocv2/bench/sysc/src/Utils.cpp ~ /openrisc/trunk/orpsocv2/rtl/verilog/components/debug_if/dbg_cpu.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_ctrl.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_du.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/components/wb_conbus/wb_conbus_top.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200_defines.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/orpsoc_top.v ~ /openrisc/trunk/orpsocv2/sim/bin/Makefile + /openrisc/trunk/orpsocv2/sw/utils/binlog2readable.cpp ~ /openrisc/trunk/orpsocv2/sw/utils/Makefile julius Sun, 10 Jan 2010 12:31:11 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fbench%2Fsysc%2Finclude%2F&rev=63 ORPSoCv2 updates: cycle accurate profiling, ELF loading https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fbench%2Fsysc%2Finclude%2F&rev=51 <div>Rev 51 - julius (17 file(s) modified)</div><div>ORPSoCv2 updates: cycle accurate profiling, ELF loading</div>+ /openrisc/trunk/orpsocv2/bench/sysc/include/coff.h + /openrisc/trunk/orpsocv2/bench/sysc/include/elf.h + /openrisc/trunk/orpsocv2/bench/sysc/include/MemoryLoad.h ~ /openrisc/trunk/orpsocv2/bench/sysc/include/Or1200MonitorSC.h ~ /openrisc/trunk/orpsocv2/bench/sysc/include/OrpsocAccess.h + /openrisc/trunk/orpsocv2/bench/sysc/src/MemoryLoad.cpp ~ /openrisc/trunk/orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp ~ /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocAccess.cpp ~ /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocMain.cpp ~ /openrisc/trunk/orpsocv2/bench/verilog/smii_phy.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_ctrl.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_except.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/components/ram_wb/ram_wb_sc_sw.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/eth_defines.v ~ /openrisc/trunk/orpsocv2/sim/bin/Makefile ~ /openrisc/trunk/orpsocv2/sw/support/except.S ~ /openrisc/trunk/orpsocv2/sw/support/time.c julius Thu, 01 Oct 2009 14:17:18 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fbench%2Fsysc%2Finclude%2F&rev=51 Lots of ORPSoC Updates. Cycle accurate model update. Enabled block ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fbench%2Fsysc%2Finclude%2F&rev=49 <div>Rev 49 - julius (39 file(s) modified)</div><div>Lots of ORPSoC Updates. Cycle accurate model update. Enabled block ...</div>~ /openrisc/trunk/orpsocv2/bench/sysc/include/Or1200MonitorSC.h ~ /openrisc/trunk/orpsocv2/bench/sysc/include/OrpsocAccess.h ~ /openrisc/trunk/orpsocv2/bench/sysc/include/TraceSC.h ~ /openrisc/trunk/orpsocv2/bench/sysc/src/Modules.make ~ /openrisc/trunk/orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp ~ /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocAccess.cpp ~ /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocMain.cpp ~ /openrisc/trunk/orpsocv2/bench/sysc/src/TraceSC.cpp ~ /openrisc/trunk/orpsocv2/bench/verilog/eth_phy.v ~ /openrisc/trunk/orpsocv2/bench/verilog/eth_phy_defines.v ~ /openrisc/trunk/orpsocv2/bench/verilog/eth_stim.v ~ /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v ~ /openrisc/trunk/orpsocv2/bench/verilog/orpsoc_testbench.v ~ /openrisc/trunk/orpsocv2/bench/verilog/smii_phy.v ~ /openrisc/trunk/orpsocv2/bench/verilog/vpi/c/gdb.c ~ /openrisc/trunk/orpsocv2/bench/verilog/vpi/c/gdb.h ~ /openrisc/trunk/orpsocv2/bench/verilog/vpi/c/rsp-rtl_sim.c ~ /openrisc/trunk/orpsocv2/bench/verilog/vpi/c/rsp-rtl_sim.h ~ /openrisc/trunk/orpsocv2/bench/verilog/vpi/verilog/vpi_debug_module.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/components/debug_if/dbg_cpu.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_cfgr.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_ctrl.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_du.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_except.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_genpc.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_ic_ram.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/components/smii/smii_txrx.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/or1200_defines.v ~ /openrisc/trunk/orpsocv2/sim/bin/Makefile ~ /openrisc/trunk/orpsocv2/sw/dhry/dhry.c ~ /openrisc/trunk/orpsocv2/sw/dhry/Makefile ~ /openrisc/trunk/orpsocv2/sw/support/except.S ~ /openrisc/trunk/orpsocv2/sw/support/int.c ~ /openrisc/trunk/orpsocv2/sw/support/Makefile ~ /openrisc/trunk/orpsocv2/sw/support/orp.ld ~ /openrisc/trunk/orpsocv2/sw/support/support.c ~ /openrisc/trunk/orpsocv2/sw/support/support.h + /openrisc/trunk/orpsocv2/sw/support/time.c + /openrisc/trunk/orpsocv2/sw/support/time.h julius Sat, 12 Sep 2009 20:25:34 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fbench%2Fsysc%2Finclude%2F&rev=49 New SystemC model monitoring functions, ethernet PHY model and test ... https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fbench%2Fsysc%2Finclude%2F&rev=44 <div>Rev 44 - julius (35 file(s) modified)</div><div>New SystemC model monitoring functions, ethernet PHY model and test ...</div>~ /openrisc/trunk/orpsocv2/bench/sysc/include/Or1200MonitorSC.h ~ /openrisc/trunk/orpsocv2/bench/sysc/include/OrpsocAccess.h ~ /openrisc/trunk/orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp ~ /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocAccess.cpp ~ /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocMain.cpp ~ /openrisc/trunk/orpsocv2/bench/sysc/src/TraceSC.cpp + /openrisc/trunk/orpsocv2/bench/verilog/eth_phy.v + /openrisc/trunk/orpsocv2/bench/verilog/eth_phy_defines.v + /openrisc/trunk/orpsocv2/bench/verilog/eth_stim.v ~ /openrisc/trunk/orpsocv2/bench/verilog/mt48lc16m16a2.v ~ /openrisc/trunk/orpsocv2/bench/verilog/orpsoc_testbench.v ~ /openrisc/trunk/orpsocv2/bench/verilog/orpsoc_testbench_defines.v + /openrisc/trunk/orpsocv2/bench/verilog/smii_phy.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_dpram.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_except.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/components/or1200r2/or1200_sprs.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/components/smii/smii_sync.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/components/smii/smii_txrx.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/components/uart16550/uart_top.v ~ /openrisc/trunk/orpsocv2/rtl/verilog/orpsoc_top.v ~ /openrisc/trunk/orpsocv2/sim/bin/Makefile ~ /openrisc/trunk/orpsocv2/sim/bin/verilator.scr ~ /openrisc/trunk/orpsocv2/sw/dhry/dhry.c ~ /openrisc/trunk/orpsocv2/sw/dhry/Makefile + /openrisc/trunk/orpsocv2/sw/eth + /openrisc/trunk/orpsocv2/sw/eth/eth-basic.c + /openrisc/trunk/orpsocv2/sw/eth/eth-int.c + /openrisc/trunk/orpsocv2/sw/eth/ethphy_micrel.h + /openrisc/trunk/orpsocv2/sw/eth/except.S + /openrisc/trunk/orpsocv2/sw/eth/Makefile + /openrisc/trunk/orpsocv2/sw/eth/open_eth.h ~ /openrisc/trunk/orpsocv2/sw/support/board.h ~ /openrisc/trunk/orpsocv2/sw/support/except.S ~ /openrisc/trunk/orpsocv2/sw/support/int.h ~ /openrisc/trunk/orpsocv2/sw/support/Makefile.inc julius Thu, 23 Jul 2009 09:52:09 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fbench%2Fsysc%2Finclude%2F&rev=44 Checking in ORPSoCv2 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fbench%2Fsysc%2Finclude%2F&rev=6 <div>Rev 6 - julius (307 file(s) modified)</div><div>Checking in ORPSoCv2</div>+ /openrisc/trunk/orpsocv2 + /openrisc/trunk/orpsocv2/backend + /openrisc/trunk/orpsocv2/backend/gbuf.v + /openrisc/trunk/orpsocv2/backend/sim_lib.v + /openrisc/trunk/orpsocv2/bench + /openrisc/trunk/orpsocv2/bench/sysc + /openrisc/trunk/orpsocv2/bench/sysc/include + /openrisc/trunk/orpsocv2/bench/sysc/include/Or1200MonitorSC.h + /openrisc/trunk/orpsocv2/bench/sysc/include/OrpsocAccess.h + /openrisc/trunk/orpsocv2/bench/sysc/include/OrpsocMain.h + /openrisc/trunk/orpsocv2/bench/sysc/include/ResetSC.h + /openrisc/trunk/orpsocv2/bench/sysc/include/TraceSC.h + /openrisc/trunk/orpsocv2/bench/sysc/include/UartSC.h + /openrisc/trunk/orpsocv2/bench/sysc/src + /openrisc/trunk/orpsocv2/bench/sysc/src/Modules.make + /openrisc/trunk/orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp + /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocAccess.cpp + /openrisc/trunk/orpsocv2/bench/sysc/src/OrpsocMain.cpp + /openrisc/trunk/orpsocv2/bench/sysc/src/ResetSC.cpp + /openrisc/trunk/orpsocv2/bench/sysc/src/TraceSC.cpp + /openrisc/trunk/orpsocv2/bench/sysc/src/UartSC.cpp + /openrisc/trunk/orpsocv2/bench/verilog + /openrisc/trunk/orpsocv2/bench/verilog/AT26DFxxx.v + /openrisc/trunk/orpsocv2/bench/verilog/clk_gen.v + /openrisc/trunk/orpsocv2/bench/verilog/mt48lc16m16a2.v + /openrisc/trunk/orpsocv2/bench/verilog/or1200_monitor.v + /openrisc/trunk/orpsocv2/bench/verilog/orpsoc_testbench.v + /openrisc/trunk/orpsocv2/bench/verilog/orpsoc_testbench_defines.v + /openrisc/trunk/orpsocv2/bench/verilog/timescale.v + /openrisc/trunk/orpsocv2/bench/verilog/uart_decoder.v + /openrisc/trunk/orpsocv2/rtl + /openrisc/trunk/orpsocv2/rtl/verilog + /openrisc/trunk/orpsocv2/rtl/verilog/components + /openrisc/trunk/orpsocv2/rtl/verilog/components/debug_if + /openrisc/trunk/orpsocv2/rtl/verilog/components/debug_if/dbg_cpu.v + /openrisc/trunk/orpsocv2/rtl/verilog/components/debug_if/dbg_cpu_defines.v + /openrisc/trunk/orpsocv2/rtl/verilog/components/debug_if/dbg_cpu_registers.v + /openrisc/trunk/orpsocv2/rtl/verilog/components/debug_if/dbg_crc32_d1.v + /openrisc/trunk/orpsocv2/rtl/verilog/components/debug_if/dbg_defines.v + /openrisc/trunk/orpsocv2/rtl/verilog/components/debug_if/dbg_defines_old.v + /openrisc/trunk/orpsocv2/rtl/verilog/components/debug_if/dbg_register.v + /openrisc/trunk/orpsocv2/rtl/verilog/components/debug_if/dbg_top.v + /openrisc/trunk/orpsocv2/rtl/verilog/components/debug_if/dbg_top_ip.v + /openrisc/trunk/orpsocv2/rtl/verilog/components/debug_if/dbg_wb.v + /openrisc/trunk/orpsocv2/rtl/verilog/components/debug_if/dbg_wb_defines.v + /openrisc/trunk/orpsocv2/rtl/verilog/components/debug_if/debug_if_ip.v + /openrisc/trunk/orpsocv2/rtl/verilog/components/debug_if/Makefile + /openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet + /openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/BUGS + /openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/eth_clockgen.v + /openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/eth_cop.v + /openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/eth_crc.v + /openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/eth_defines.v + /openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/eth_fifo.v + /openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/eth_maccontrol.v + /openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/eth_macstatus.v + /openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/eth_miim.v + /openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/eth_outputcontrol.v + /openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/eth_random.v + /openrisc/trunk/orpsocv2/rtl/verilog/components/ethernet/eth_receivecontrol.v + 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/openrisc/trunk/orpsocv2/sw/except/except_test.c + /openrisc/trunk/orpsocv2/sw/except/except_test_s.S + /openrisc/trunk/orpsocv2/sw/except/Makefile + /openrisc/trunk/orpsocv2/sw/icm + /openrisc/trunk/orpsocv2/sw/icm/icm.S + /openrisc/trunk/orpsocv2/sw/icm/Makefile + /openrisc/trunk/orpsocv2/sw/mmu + /openrisc/trunk/orpsocv2/sw/mmu/except.S + /openrisc/trunk/orpsocv2/sw/mmu/Makefile + /openrisc/trunk/orpsocv2/sw/mmu/mmu.c + /openrisc/trunk/orpsocv2/sw/mmu/mmu_asm.S + /openrisc/trunk/orpsocv2/sw/mul + /openrisc/trunk/orpsocv2/sw/mul/Makefile + /openrisc/trunk/orpsocv2/sw/mul/mul.c + /openrisc/trunk/orpsocv2/sw/support + /openrisc/trunk/orpsocv2/sw/support/board.h + /openrisc/trunk/orpsocv2/sw/support/except.S + /openrisc/trunk/orpsocv2/sw/support/int.c + /openrisc/trunk/orpsocv2/sw/support/int.h + /openrisc/trunk/orpsocv2/sw/support/Makefile + /openrisc/trunk/orpsocv2/sw/support/Makefile.inc + /openrisc/trunk/orpsocv2/sw/support/mc.h + /openrisc/trunk/orpsocv2/sw/support/orp.cfg + /openrisc/trunk/orpsocv2/sw/support/orp.cfg.old.org + /openrisc/trunk/orpsocv2/sw/support/orp.ld + /openrisc/trunk/orpsocv2/sw/support/reset.S + /openrisc/trunk/orpsocv2/sw/support/spr_defs.h + /openrisc/trunk/orpsocv2/sw/support/support.c + /openrisc/trunk/orpsocv2/sw/support/support.h + /openrisc/trunk/orpsocv2/sw/support/uart.c + /openrisc/trunk/orpsocv2/sw/support/uart.h + /openrisc/trunk/orpsocv2/sw/support/vfnprintf.c + /openrisc/trunk/orpsocv2/sw/support/vfnprintf.h + /openrisc/trunk/orpsocv2/sw/support/virtex.tim + /openrisc/trunk/orpsocv2/sw/syscall + /openrisc/trunk/orpsocv2/sw/syscall/Makefile + /openrisc/trunk/orpsocv2/sw/syscall/syscall.S + /openrisc/trunk/orpsocv2/sw/tick + /openrisc/trunk/orpsocv2/sw/tick/Makefile + /openrisc/trunk/orpsocv2/sw/tick/tick.S + /openrisc/trunk/orpsocv2/sw/uart + /openrisc/trunk/orpsocv2/sw/uart/Makefile + /openrisc/trunk/orpsocv2/sw/uart/uart.c + /openrisc/trunk/orpsocv2/sw/uart/uart.h + /openrisc/trunk/orpsocv2/sw/utils + /openrisc/trunk/orpsocv2/sw/utils/bin2c.c + /openrisc/trunk/orpsocv2/sw/utils/bin2flimg.c + /openrisc/trunk/orpsocv2/sw/utils/bin2hex.c + /openrisc/trunk/orpsocv2/sw/utils/bin2srec.c + /openrisc/trunk/orpsocv2/sw/utils/bin2vmem.c + /openrisc/trunk/orpsocv2/sw/utils/loader.c + /openrisc/trunk/orpsocv2/sw/utils/Makefile + /openrisc/trunk/orpsocv2/sw/utils/marksec + /openrisc/trunk/orpsocv2/sw/utils/merge2srec + /openrisc/trunk/orpsocv2/sw/utils/or32-idecode + /openrisc/trunk/orpsocv2/sw/utils/or32-idecode/ansidecl.h + /openrisc/trunk/orpsocv2/sw/utils/or32-idecode/bfd.h + /openrisc/trunk/orpsocv2/sw/utils/or32-idecode/dis-asm.h + /openrisc/trunk/orpsocv2/sw/utils/or32-idecode/example_input + /openrisc/trunk/orpsocv2/sw/utils/or32-idecode/Makefile + /openrisc/trunk/orpsocv2/sw/utils/or32-idecode/or32-dis.c + /openrisc/trunk/orpsocv2/sw/utils/or32-idecode/or32-opc.c + /openrisc/trunk/orpsocv2/sw/utils/or32-idecode/or32.h + /openrisc/trunk/orpsocv2/sw/utils/or32-idecode/symcat.h julius Thu, 21 May 2009 21:32:57 +0100 https://opencores.org/websvn//websvn/revision?repname=openrisc&path=%2Fopenrisc%2Ftrunk%2Forpsocv2%2Fbench%2Fsysc%2Finclude%2F&rev=6

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